| # Copyright 2021 The Chromium OS Authors. All rights reserved. |
| # Use of this source code is governed by a BSD-style license that can be |
| # found in the LICENSE file. |
| |
| Rail,Parent |
| PPVAR_VDDCR,PPVAR_SYS |
| PPVAR_PCORE_SOC_IN,PPVAR_SYS |
| PPVAR_VDDCR_SOC_S0,PPVAR_SYS |
| PPVAR_VDDCR_S0_PH3,PPVAR_VDDCR |
| PPVAR_VDDCR_S0_PH2,PPVAR_VDDCR |
| PP3300_VDDBT_RTC,PP3300_Z5 |
| PPVAR_VDDCR_S0_PH1,PPVAR_VDDCR |
| PP3300_S5_VDD_33_S5,PP3300_S5 |
| PP3300_S0_VDD_33,PP3300_S0 |
| PP1800_S5_VDD_18_S5,PP1800_S5 |
| PP1800_S0_VDD_18,PP1800_S0 |
| PP1800_S0_VDDIO_VPH,PP1800_S0 |
| PP1800_S5_VDDIO_AUDIO,PP1800_S5 |
| PP0750_VDDP_S5,PPVAR_SYS |
| PP0750_VDDP_S0,PPVAR_SYS |
| PP1100_SOC_MEM_S3,PP1100_MEM_S3 |
| PP1100_MEM_S3,PPVAR_SYS |
| PP1800_MEM_S3,PP1800_Z1 |
| PP0600_MEM,PP3300_Z1 |
| PP3300_EC_Z1,PP3300_Z1 |
| PP1800_Z1,PPVAR_SYS |
| PP3300_Z1,PPVAR_SYS |
| PP3300_S0,PP3300_Z1 |
| PP3300_GSC_Z1,PP3300_Z1 |
| PP1800_GSC_Z1,PP1800_Z1 |
| PP5000_S5,PPVAR_SYS |
| PPVAR_SYS_KB_BL,PPVAR_SYS |
| PP3300_DISP_X,PP3300_Z1 |
| PPVAR_BL_PWR,PPVAR_SYS |
| PP3300_WWAN_X,PPVAR_SYS |
| PP3300_WLAN_X,PP3300_Z1 |
| PP1800_S0,PP1800_Z1 |
| PP1800_EC_Z1,PP1800_Z1 |
| PP3300_S5,PP3300_Z1 |
| PP1800_S5,PP1800_Z1 |
| PP3300_SD_S0,PP3300_S0 |
| PP3300_SSD_S0,PP3300_S0 |
| PP3300_Z5,PPVAR_SYS |
| PPVAR_SYS_DB,PPVAR_SYS |
| PPVAR_SYS,PPVAR_BAT_Q |
| PPVAR_BAT_Q,NA |
| PPVAR_VBUS_IN,NA |
| PP5000_S5_DB,PPVAR_SYS_DB |
| PP3300_S5_DB,PP3300_S5 |
| PP1200_S5_DB,PP5000_S5_DB |
