| From 4725c65145c93003b85b2a7827b30bfac749aa39 Mon Sep 17 00:00:00 2001 |
| From: Azhar Shaikh <azhar.shaikh@intel.com> |
| Date: Wed, 23 Jan 2019 10:23:38 -0800 |
| Subject: [PATCH] Revert "VPP: clear a surface using media pipeline on GEN8+" |
| |
| This reverts commit 5bdb6754ae91c6d54290c541fc2aeaf20f6550e5. |
| --- |
| src/gen75_picture_process.c | 85 ++++- |
| src/gen8_post_processing.c | 304 ------------------ |
| src/gen9_post_processing.c | 304 ------------------ |
| src/i965_post_processing.c | 9 - |
| src/intel_common_vpp_internal.c | 14 - |
| src/intel_common_vpp_internal.h | 20 -- |
| src/intel_gen_vppapi.h | 6 - |
| src/shaders/post_processing/gen8/Makefile.am | 27 +- |
| .../post_processing/gen8/clear_bgrx.g8b | 21 -- |
| .../post_processing/gen8/clear_bgrx.gxa | 87 ----- |
| .../post_processing/gen8/clear_pl2_8bit.g8b | 18 -- |
| .../post_processing/gen8/clear_pl2_8bit.gxa | 96 ------ |
| .../post_processing/gen8/clear_pl3_8bit.g8b | 20 -- |
| .../post_processing/gen8/clear_pl3_8bit.gxa | 109 ------- |
| .../post_processing/gen8/clear_rgbx.g8b | 21 -- |
| .../post_processing/gen8/clear_rgbx.gxa | 87 ----- |
| .../post_processing/gen8/clear_uyvy.g8b | 16 - |
| .../post_processing/gen8/clear_uyvy.gxa | 84 ----- |
| .../post_processing/gen8/clear_yuy2.g8b | 16 - |
| .../post_processing/gen8/clear_yuy2.gxa | 84 ----- |
| src/shaders/post_processing/gen9/Makefile.am | 26 +- |
| .../post_processing/gen9/clear_bgrx.g9b | 21 -- |
| .../post_processing/gen9/clear_bgrx.gxa | 87 ----- |
| .../post_processing/gen9/clear_pl2_8bit.g9b | 18 -- |
| .../post_processing/gen9/clear_pl2_8bit.gxa | 96 ------ |
| .../post_processing/gen9/clear_pl3_8bit.g9b | 20 -- |
| .../post_processing/gen9/clear_pl3_8bit.gxa | 109 ------- |
| .../post_processing/gen9/clear_rgbx.g9b | 21 -- |
| .../post_processing/gen9/clear_rgbx.gxa | 87 ----- |
| .../post_processing/gen9/clear_uyvy.g9b | 16 - |
| .../post_processing/gen9/clear_uyvy.gxa | 84 ----- |
| .../post_processing/gen9/clear_yuy2.g9b | 16 - |
| .../post_processing/gen9/clear_yuy2.gxa | 84 ----- |
| 33 files changed, 78 insertions(+), 2035 deletions(-) |
| delete mode 100644 src/shaders/post_processing/gen8/clear_bgrx.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_bgrx.gxa |
| delete mode 100644 src/shaders/post_processing/gen8/clear_pl2_8bit.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_pl2_8bit.gxa |
| delete mode 100644 src/shaders/post_processing/gen8/clear_pl3_8bit.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_pl3_8bit.gxa |
| delete mode 100644 src/shaders/post_processing/gen8/clear_rgbx.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_rgbx.gxa |
| delete mode 100644 src/shaders/post_processing/gen8/clear_uyvy.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_uyvy.gxa |
| delete mode 100644 src/shaders/post_processing/gen8/clear_yuy2.g8b |
| delete mode 100644 src/shaders/post_processing/gen8/clear_yuy2.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_bgrx.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_bgrx.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_pl2_8bit.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_pl2_8bit.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_pl3_8bit.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_pl3_8bit.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_rgbx.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_rgbx.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_uyvy.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_uyvy.gxa |
| delete mode 100644 src/shaders/post_processing/gen9/clear_yuy2.g9b |
| delete mode 100644 src/shaders/post_processing/gen9/clear_yuy2.gxa |
| |
| diff --git a/src/gen75_picture_process.c b/src/gen75_picture_process.c |
| index 8eae208d20c8..0ae28cbe26af 100644 |
| --- a/src/gen75_picture_process.c |
| +++ b/src/gen75_picture_process.c |
| @@ -113,23 +113,81 @@ gen8plus_vpp_clear_surface(VADriverContextP ctx, |
| struct object_surface *obj_surface, |
| unsigned int color) |
| { |
| + struct intel_batchbuffer *batch = pp_context->batch; |
| + unsigned int blt_cmd, br13; |
| + unsigned int tiling = 0, swizzle = 0; |
| + int pitch; |
| unsigned char y, u, v, a = 0; |
| + int region_width, region_height; |
| |
| - if (!obj_surface || |
| - !obj_surface->bo || |
| - !(color & 0xFF000000)) |
| + /* Currently only support NV12 surface */ |
| + if (!obj_surface || obj_surface->fourcc != VA_FOURCC_NV12) |
| return; |
| |
| - if (obj_surface->fourcc == VA_FOURCC_RGBA || |
| - obj_surface->fourcc == VA_FOURCC_RGBX || |
| - obj_surface->fourcc == VA_FOURCC_BGRA || |
| - obj_surface->fourcc == VA_FOURCC_BGRX) |
| - intel_common_clear_surface(ctx, pp_context, obj_surface, color); |
| - else { |
| - rgb_to_yuv(color, &y, &u, &v, &a); |
| - intel_common_clear_surface(ctx, pp_context, obj_surface, |
| - a << 24 | y << 16 | v << 8 | u); |
| + rgb_to_yuv(color, &y, &u, &v, &a); |
| + |
| + if (a == 0) |
| + return; |
| + |
| + dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); |
| + blt_cmd = GEN8_XY_COLOR_BLT_CMD; |
| + pitch = obj_surface->width; |
| + |
| + if (tiling != I915_TILING_NONE) { |
| + assert(tiling == I915_TILING_Y); |
| + // blt_cmd |= XY_COLOR_BLT_DST_TILED; |
| + // pitch >>= 2; |
| } |
| + |
| + br13 = 0xf0 << 16; |
| + br13 |= BR13_8; |
| + br13 |= pitch; |
| + |
| + intel_batchbuffer_start_atomic_blt(batch, 56); |
| + BEGIN_BLT_BATCH(batch, 14); |
| + |
| + region_width = obj_surface->width; |
| + region_height = obj_surface->height; |
| + |
| + OUT_BATCH(batch, blt_cmd); |
| + OUT_BATCH(batch, br13); |
| + OUT_BATCH(batch, |
| + 0 << 16 | |
| + 0); |
| + OUT_BATCH(batch, |
| + region_height << 16 | |
| + region_width); |
| + OUT_RELOC64(batch, obj_surface->bo, |
| + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |
| + 0); |
| + OUT_BATCH(batch, y); |
| + |
| + br13 = 0xf0 << 16; |
| + br13 |= BR13_565; |
| + br13 |= pitch; |
| + |
| + region_width = obj_surface->width / 2; |
| + region_height = obj_surface->height / 2; |
| + |
| + if (tiling == I915_TILING_Y) { |
| + region_height = ALIGN(obj_surface->height / 2, 32); |
| + } |
| + |
| + OUT_BATCH(batch, blt_cmd); |
| + OUT_BATCH(batch, br13); |
| + OUT_BATCH(batch, |
| + 0 << 16 | |
| + 0); |
| + OUT_BATCH(batch, |
| + region_height << 16 | |
| + region_width); |
| + OUT_RELOC64(batch, obj_surface->bo, |
| + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |
| + obj_surface->width * obj_surface->y_cb_offset); |
| + OUT_BATCH(batch, v << 8 | u); |
| + |
| + ADVANCE_BATCH(batch); |
| + intel_batchbuffer_end_atomic(batch); |
| } |
| |
| VAStatus |
| @@ -239,7 +297,8 @@ gen75_proc_picture(VADriverContextP ctx, |
| assert(gpe_proc_ctx != NULL); // gpe_proc_ctx must be a non-NULL pointer |
| |
| if ((gpe_proc_ctx->pp_context.scaling_gpe_context_initialized & VPPGPE_8BIT_8BIT) && |
| - (pipeline_param->output_background_color & 0xFF000000)) |
| + (obj_dst_surf->fourcc == VA_FOURCC_NV12) && |
| + pipeline_param->output_background_color) |
| gen8plus_vpp_clear_surface(ctx, |
| &gpe_proc_ctx->pp_context, |
| obj_dst_surf, |
| diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c |
| index c3a911b9a713..945af132cbd5 100644 |
| --- a/src/gen8_post_processing.c |
| +++ b/src/gen8_post_processing.c |
| @@ -350,80 +350,6 @@ struct i965_kernel pp_common_scaling_gen8[] = { |
| }, |
| }; |
| |
| -static const uint32_t pp_clear_yuy2_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_yuy2.g8b" |
| -}; |
| - |
| -static const uint32_t pp_clear_uyvy_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_uyvy.g8b" |
| -}; |
| - |
| -static const uint32_t pp_clear_pl2_8bit_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_pl2_8bit.g8b" |
| -}; |
| - |
| -static const uint32_t pp_clear_pl3_8bit_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_pl3_8bit.g8b" |
| -}; |
| - |
| -static const uint32_t pp_clear_rgbx_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_rgbx.g8b" |
| -}; |
| - |
| -static const uint32_t pp_clear_bgrx_gen8[][4] = { |
| -#include "shaders/post_processing/gen8/clear_bgrx.g8b" |
| -}; |
| - |
| -struct i965_kernel pp_clear_gen8[] = { |
| - { |
| - "pl2 8bit", |
| - 0, |
| - pp_clear_pl2_8bit_gen8, |
| - sizeof(pp_clear_pl2_8bit_gen8), |
| - NULL, |
| - }, |
| - |
| - { |
| - "pl3 8bit", |
| - 1, |
| - pp_clear_pl3_8bit_gen8, |
| - sizeof(pp_clear_pl3_8bit_gen8), |
| - NULL, |
| - }, |
| - |
| - { |
| - "yuy2", |
| - 2, |
| - pp_clear_yuy2_gen8, |
| - sizeof(pp_clear_yuy2_gen8), |
| - NULL, |
| - }, |
| - |
| - { |
| - "uyvy", |
| - 3, |
| - pp_clear_uyvy_gen8, |
| - sizeof(pp_clear_uyvy_gen8), |
| - NULL, |
| - }, |
| - |
| - { |
| - "rgbx", |
| - 4, |
| - pp_clear_rgbx_gen8, |
| - sizeof(pp_clear_rgbx_gen8), |
| - NULL, |
| - }, |
| - |
| - { |
| - "bgrx", |
| - 5, |
| - pp_clear_bgrx_gen8, |
| - sizeof(pp_clear_bgrx_gen8), |
| - NULL, |
| - }, |
| -}; |
| - |
| static void |
| gen8_pp_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling) |
| { |
| @@ -1799,36 +1725,6 @@ gen8_post_processing_context_init(VADriverContextP ctx, |
| gen8_gpe_context_init(ctx, gpe_context); |
| pp_context->scaling_gpe_context_initialized |= (VPPGPE_8BIT_8BIT | VPPGPE_8BIT_420_RGB32); |
| |
| - gpe_context = &pp_context->clear_gpe_context; |
| - gen8_gpe_load_kernels(ctx, gpe_context, pp_clear_gen8, ARRAY_ELEMS(pp_clear_gen8)); |
| - gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64); |
| - gpe_context->idrt.max_entries = ALIGN(ARRAY_ELEMS(pp_clear_gen8), 2); |
| - gpe_context->sampler.entry_size = ALIGN(sizeof(struct gen8_sampler_state), 64); |
| - gpe_context->sampler.max_entries = 1; |
| - gpe_context->curbe.length = ALIGN(sizeof(struct clear_input_parameter), 64); |
| - |
| - gpe_context->surface_state_binding_table.max_entries = MAX_SCALING_SURFACES; |
| - gpe_context->surface_state_binding_table.binding_table_offset = 0; |
| - gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_SCALING_SURFACES * 4, 64); |
| - gpe_context->surface_state_binding_table.length = ALIGN(MAX_SCALING_SURFACES * 4, 64) + ALIGN(MAX_SCALING_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64); |
| - |
| - if (i965->intel.eu_total > 0) { |
| - gpe_context->vfe_state.max_num_threads = i965->intel.eu_total * 6; |
| - } else { |
| - if (i965->intel.has_bsd2) |
| - gpe_context->vfe_state.max_num_threads = 300; |
| - else |
| - gpe_context->vfe_state.max_num_threads = 60; |
| - } |
| - |
| - gpe_context->vfe_state.curbe_allocation_size = 37; |
| - gpe_context->vfe_state.urb_entry_size = 16; |
| - gpe_context->vfe_state.num_urb_entries = 127; |
| - gpe_context->vfe_state.gpgpu_mode = 0; |
| - |
| - gen8_gpe_context_init(ctx, gpe_context); |
| - pp_context->clear_gpe_context_initialized = 1; |
| - |
| return; |
| } |
| |
| @@ -2485,203 +2381,3 @@ gen8_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx, |
| |
| return VA_STATUS_SUCCESS; |
| } |
| - |
| -static void |
| -gen8_clear_surface_sample_state(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface) |
| -{ |
| - struct gen8_sampler_state *sampler_state; |
| - |
| - if (gpe_context == NULL) |
| - return; |
| - |
| - dri_bo_map(gpe_context->sampler.bo, 1); |
| - |
| - if (gpe_context->sampler.bo->virtual == NULL) |
| - return; |
| - |
| - sampler_state = (struct gen8_sampler_state *)(gpe_context->sampler.bo->virtual + gpe_context->sampler.offset); |
| - |
| - memset(sampler_state, 0, sizeof(*sampler_state)); |
| - |
| - dri_bo_unmap(gpe_context->sampler.bo); |
| -} |
| - |
| -static void |
| -gen8_clear_surface_curbe(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color) |
| -{ |
| - struct clear_input_parameter *clear_curbe; |
| - |
| - if (gpe_context == NULL || !obj_surface) |
| - return; |
| - |
| - clear_curbe = i965_gpe_context_map_curbe(gpe_context); |
| - |
| - if (!clear_curbe) |
| - return; |
| - |
| - memset(clear_curbe, 0, sizeof(struct clear_input_parameter)); |
| - clear_curbe->color = color; |
| - |
| - i965_gpe_context_unmap_curbe(gpe_context); |
| -} |
| - |
| -static void |
| -gen8_clear_surface_state(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface) |
| -{ |
| - struct i965_surface src_surface; |
| - VARectangle rect; |
| - dri_bo *bo; |
| - unsigned int fourcc; |
| - int width[3], height[3], pitch[3], bo_offset[3]; |
| - int bti; |
| - |
| - src_surface.base = (struct object_base *)obj_surface; |
| - src_surface.type = I965_SURFACE_TYPE_SURFACE; |
| - src_surface.flags = I965_SURFACE_FLAG_FRAME; |
| - |
| - fourcc = obj_surface->fourcc; |
| - rect.x = 0; |
| - rect.y = 0; |
| - rect.width = obj_surface->orig_width; |
| - rect.height = obj_surface->orig_height; |
| - |
| - gen8_pp_context_get_surface_conf(ctx, &src_surface, |
| - &rect, |
| - width, |
| - height, |
| - pitch, |
| - bo_offset); |
| - |
| - bti = 1; |
| - bo = obj_surface->bo; |
| - |
| - if (fourcc == VA_FOURCC_RGBA || |
| - fourcc == VA_FOURCC_RGBX || |
| - fourcc == VA_FOURCC_BGRA || |
| - fourcc == VA_FOURCC_BGRX) { |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0] * 4, height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) { |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0] * 2, height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - } else { |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0], height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - |
| - if (fourcc == VA_FOURCC_NV12) { |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[1], |
| - width[1] * 2, height[1], |
| - pitch[1], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 1, 0); |
| - } else { |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[1], |
| - width[1], height[1], |
| - pitch[1], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 1, 0); |
| - |
| - gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[2], |
| - width[2], height[2], |
| - pitch[2], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 2, 0); |
| - } |
| - } |
| -} |
| - |
| -void |
| -gen8_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color) |
| -{ |
| - struct i965_gpe_context *gpe_context; |
| - struct gpe_media_object_walker_parameter media_object_walker_param; |
| - struct intel_vpp_kernel_walker_parameter kernel_walker_param; |
| - int index = 0; |
| - |
| - if (!pp_context || !obj_surface) |
| - return; |
| - |
| - if (!pp_context->clear_gpe_context_initialized) |
| - return; |
| - |
| - switch (obj_surface->fourcc) { |
| - case VA_FOURCC_NV12: |
| - index = 0; |
| - break; |
| - |
| - case VA_FOURCC_I420: |
| - case VA_FOURCC_YV12: |
| - case VA_FOURCC_IMC1: |
| - case VA_FOURCC_IMC3: |
| - index = 1; |
| - break; |
| - |
| - case VA_FOURCC_YUY2: |
| - index = 2; |
| - break; |
| - |
| - case VA_FOURCC_UYVY: |
| - index = 3; |
| - break; |
| - |
| - case VA_FOURCC_RGBA: |
| - case VA_FOURCC_RGBX: |
| - index = 4; |
| - break; |
| - |
| - case VA_FOURCC_BGRA: |
| - case VA_FOURCC_BGRX: |
| - index = 5; |
| - break; |
| - |
| - default: |
| - /* TODO: add support for other fourccs */ |
| - return; |
| - } |
| - |
| - gpe_context = &pp_context->clear_gpe_context; |
| - |
| - gen8_gpe_context_init(ctx, gpe_context); |
| - gen8_clear_surface_sample_state(ctx, gpe_context, obj_surface); |
| - gen8_gpe_reset_binding_table(ctx, gpe_context); |
| - gen8_clear_surface_curbe(ctx, gpe_context, obj_surface, color); |
| - gen8_clear_surface_state(ctx, gpe_context, obj_surface); |
| - gen8_gpe_setup_interface_data(ctx, gpe_context); |
| - |
| - memset(&kernel_walker_param, 0, sizeof(kernel_walker_param)); |
| - kernel_walker_param.resolution_x = ALIGN(obj_surface->orig_width, 16) >> 4; |
| - kernel_walker_param.resolution_y = ALIGN(obj_surface->orig_height, 16) >> 4; |
| - kernel_walker_param.no_dependency = 1; |
| - |
| - intel_vpp_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param); |
| - media_object_walker_param.interface_offset = index; |
| - gen8_run_kernel_media_object_walker(ctx, |
| - pp_context->batch, |
| - gpe_context, |
| - &media_object_walker_param); |
| -} |
| diff --git a/src/gen9_post_processing.c b/src/gen9_post_processing.c |
| index 7e1ccd387564..eede36f7fca3 100644 |
| --- a/src/gen9_post_processing.c |
| +++ b/src/gen9_post_processing.c |
| @@ -124,30 +124,6 @@ static const uint32_t pp_8bit_420_rgb32_scaling_gen9[][4] = { |
| #include "shaders/post_processing/gen9/conv_8bit_420_rgb32.g9b" |
| }; |
| |
| -static const uint32_t pp_clear_yuy2_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_yuy2.g9b" |
| -}; |
| - |
| -static const uint32_t pp_clear_uyvy_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_uyvy.g9b" |
| -}; |
| - |
| -static const uint32_t pp_clear_pl2_8bit_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_pl2_8bit.g9b" |
| -}; |
| - |
| -static const uint32_t pp_clear_pl3_8bit_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_pl3_8bit.g9b" |
| -}; |
| - |
| -static const uint32_t pp_clear_rgbx_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_rgbx.g9b" |
| -}; |
| - |
| -static const uint32_t pp_clear_bgrx_gen9[][4] = { |
| -#include "shaders/post_processing/gen9/clear_bgrx.g9b" |
| -}; |
| - |
| struct i965_kernel pp_common_scaling_gen9[] = { |
| { |
| "10bit to 10bit", |
| @@ -182,56 +158,6 @@ struct i965_kernel pp_common_scaling_gen9[] = { |
| }, |
| }; |
| |
| -struct i965_kernel pp_clear_gen9[] = { |
| - { |
| - "pl2 8bit", |
| - 0, |
| - pp_clear_pl2_8bit_gen9, |
| - sizeof(pp_clear_pl2_8bit_gen9), |
| - NULL, |
| - }, |
| - |
| - { |
| - "pl3 8bit", |
| - 1, |
| - pp_clear_pl3_8bit_gen9, |
| - sizeof(pp_clear_pl3_8bit_gen9), |
| - NULL, |
| - }, |
| - |
| - { |
| - "yuy2", |
| - 2, |
| - pp_clear_yuy2_gen9, |
| - sizeof(pp_clear_yuy2_gen9), |
| - NULL, |
| - }, |
| - |
| - { |
| - "uyvy", |
| - 3, |
| - pp_clear_uyvy_gen9, |
| - sizeof(pp_clear_uyvy_gen9), |
| - NULL, |
| - }, |
| - |
| - { |
| - "rgbx", |
| - 4, |
| - pp_clear_rgbx_gen9, |
| - sizeof(pp_clear_rgbx_gen9), |
| - NULL, |
| - }, |
| - |
| - { |
| - "bgrx", |
| - 5, |
| - pp_clear_bgrx_gen9, |
| - sizeof(pp_clear_bgrx_gen9), |
| - NULL, |
| - }, |
| -}; |
| - |
| static struct pp_module pp_modules_gen9[] = { |
| { |
| { |
| @@ -649,36 +575,6 @@ gen9_post_processing_context_init(VADriverContextP ctx, |
| gen8_gpe_context_init(ctx, gpe_context); |
| pp_context->scaling_gpe_context_initialized |= (VPPGPE_8BIT_8BIT | VPPGPE_10BIT_10BIT | VPPGPE_10BIT_8BIT | VPPGPE_8BIT_420_RGB32); |
| |
| - gpe_context = &pp_context->clear_gpe_context; |
| - gen8_gpe_load_kernels(ctx, gpe_context, pp_clear_gen9, ARRAY_ELEMS(pp_clear_gen9)); |
| - gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64); |
| - gpe_context->idrt.max_entries = ALIGN(ARRAY_ELEMS(pp_clear_gen9), 2); |
| - gpe_context->sampler.entry_size = ALIGN(sizeof(struct gen8_sampler_state), 64); |
| - gpe_context->sampler.max_entries = 1; |
| - gpe_context->curbe.length = ALIGN(sizeof(struct clear_input_parameter), 64); |
| - |
| - gpe_context->surface_state_binding_table.max_entries = MAX_SCALING_SURFACES; |
| - gpe_context->surface_state_binding_table.binding_table_offset = 0; |
| - gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_SCALING_SURFACES * 4, 64); |
| - gpe_context->surface_state_binding_table.length = ALIGN(MAX_SCALING_SURFACES * 4, 64) + ALIGN(MAX_SCALING_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64); |
| - |
| - if (i965->intel.eu_total > 0) { |
| - gpe_context->vfe_state.max_num_threads = i965->intel.eu_total * 6; |
| - } else { |
| - if (i965->intel.has_bsd2) |
| - gpe_context->vfe_state.max_num_threads = 300; |
| - else |
| - gpe_context->vfe_state.max_num_threads = 60; |
| - } |
| - |
| - gpe_context->vfe_state.curbe_allocation_size = 37; |
| - gpe_context->vfe_state.urb_entry_size = 16; |
| - gpe_context->vfe_state.num_urb_entries = 127; |
| - gpe_context->vfe_state.gpgpu_mode = 0; |
| - |
| - gen8_gpe_context_init(ctx, gpe_context); |
| - pp_context->clear_gpe_context_initialized = 1; |
| - |
| return; |
| } |
| |
| @@ -1803,203 +1699,3 @@ gen9_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx, |
| |
| return VA_STATUS_SUCCESS; |
| } |
| - |
| -static void |
| -gen9_clear_surface_sample_state(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface) |
| -{ |
| - struct gen8_sampler_state *sampler_state; |
| - |
| - if (gpe_context == NULL) |
| - return; |
| - |
| - dri_bo_map(gpe_context->sampler.bo, 1); |
| - |
| - if (gpe_context->sampler.bo->virtual == NULL) |
| - return; |
| - |
| - sampler_state = (struct gen8_sampler_state *)(gpe_context->sampler.bo->virtual + gpe_context->sampler.offset); |
| - |
| - memset(sampler_state, 0, sizeof(*sampler_state)); |
| - |
| - dri_bo_unmap(gpe_context->sampler.bo); |
| -} |
| - |
| -static void |
| -gen9_clear_surface_curbe(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color) |
| -{ |
| - struct clear_input_parameter *clear_curbe; |
| - |
| - if (gpe_context == NULL || !obj_surface) |
| - return; |
| - |
| - clear_curbe = i965_gpe_context_map_curbe(gpe_context); |
| - |
| - if (!clear_curbe) |
| - return; |
| - |
| - memset(clear_curbe, 0, sizeof(struct clear_input_parameter)); |
| - clear_curbe->color = color; |
| - |
| - i965_gpe_context_unmap_curbe(gpe_context); |
| -} |
| - |
| -static void |
| -gen9_clear_surface_state(VADriverContextP ctx, |
| - struct i965_gpe_context *gpe_context, |
| - const struct object_surface *obj_surface) |
| -{ |
| - struct i965_surface src_surface; |
| - VARectangle rect; |
| - dri_bo *bo; |
| - unsigned int fourcc; |
| - int width[3], height[3], pitch[3], bo_offset[3]; |
| - int bti; |
| - |
| - src_surface.base = (struct object_base *)obj_surface; |
| - src_surface.type = I965_SURFACE_TYPE_SURFACE; |
| - src_surface.flags = I965_SURFACE_FLAG_FRAME; |
| - |
| - fourcc = obj_surface->fourcc; |
| - rect.x = 0; |
| - rect.y = 0; |
| - rect.width = obj_surface->orig_width; |
| - rect.height = obj_surface->orig_height; |
| - |
| - gen9_pp_context_get_surface_conf(ctx, &src_surface, |
| - &rect, |
| - width, |
| - height, |
| - pitch, |
| - bo_offset); |
| - |
| - bti = 1; |
| - bo = obj_surface->bo; |
| - |
| - if (fourcc == VA_FOURCC_RGBA || |
| - fourcc == VA_FOURCC_RGBX || |
| - fourcc == VA_FOURCC_BGRA || |
| - fourcc == VA_FOURCC_BGRX) { |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0] * 4, height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) { |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0] * 2, height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - } else { |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[0], |
| - width[0], height[0], |
| - pitch[0], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti, 0); |
| - |
| - if (fourcc == VA_FOURCC_NV12) { |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[1], |
| - width[1] * 2, height[1], |
| - pitch[1], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 1, 0); |
| - } else { |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[1], |
| - width[1], height[1], |
| - pitch[1], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 1, 0); |
| - |
| - gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo, |
| - bo_offset[2], |
| - width[2], height[2], |
| - pitch[2], 1, |
| - I965_SURFACEFORMAT_R8_UINT, |
| - bti + 2, 0); |
| - } |
| - } |
| -} |
| - |
| -void |
| -gen9_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color) |
| -{ |
| - struct i965_gpe_context *gpe_context; |
| - struct gpe_media_object_walker_parameter media_object_walker_param; |
| - struct intel_vpp_kernel_walker_parameter kernel_walker_param; |
| - int index = 0; |
| - |
| - if (!pp_context || !obj_surface) |
| - return; |
| - |
| - if (!pp_context->clear_gpe_context_initialized) |
| - return; |
| - |
| - switch (obj_surface->fourcc) { |
| - case VA_FOURCC_NV12: |
| - index = 0; |
| - break; |
| - |
| - case VA_FOURCC_I420: |
| - case VA_FOURCC_YV12: |
| - case VA_FOURCC_IMC1: |
| - case VA_FOURCC_IMC3: |
| - index = 1; |
| - break; |
| - |
| - case VA_FOURCC_YUY2: |
| - index = 2; |
| - break; |
| - |
| - case VA_FOURCC_UYVY: |
| - index = 3; |
| - break; |
| - |
| - case VA_FOURCC_RGBA: |
| - case VA_FOURCC_RGBX: |
| - index = 4; |
| - break; |
| - |
| - case VA_FOURCC_BGRA: |
| - case VA_FOURCC_BGRX: |
| - index = 5; |
| - break; |
| - |
| - default: |
| - /* TODO: add support for other fourccs */ |
| - return; |
| - } |
| - |
| - gpe_context = &pp_context->clear_gpe_context; |
| - |
| - gen8_gpe_context_init(ctx, gpe_context); |
| - gen9_clear_surface_sample_state(ctx, gpe_context, obj_surface); |
| - gen9_gpe_reset_binding_table(ctx, gpe_context); |
| - gen9_clear_surface_curbe(ctx, gpe_context, obj_surface, color); |
| - gen9_clear_surface_state(ctx, gpe_context, obj_surface); |
| - gen8_gpe_setup_interface_data(ctx, gpe_context); |
| - |
| - memset(&kernel_walker_param, 0, sizeof(kernel_walker_param)); |
| - kernel_walker_param.resolution_x = ALIGN(obj_surface->orig_width, 16) >> 4; |
| - kernel_walker_param.resolution_y = ALIGN(obj_surface->orig_height, 16) >> 4; |
| - kernel_walker_param.no_dependency = 1; |
| - |
| - intel_vpp_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param); |
| - media_object_walker_param.interface_offset = index; |
| - gen9_run_kernel_media_object_walker(ctx, |
| - pp_context->batch, |
| - gpe_context, |
| - &media_object_walker_param); |
| -} |
| diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c |
| index 9a4cb05d86cc..ca1976e7655f 100644 |
| --- a/src/i965_post_processing.c |
| +++ b/src/i965_post_processing.c |
| @@ -4791,15 +4791,6 @@ i965_vpp_clear_surface(VADriverContextP ctx, |
| if (a == 0) |
| return; |
| |
| - if (IS_GEN8(i965->intel.device_info) || |
| - IS_GEN9(i965->intel.device_info) || |
| - IS_GEN10(i965->intel.device_info)) { |
| - intel_common_clear_surface(ctx, pp_context, obj_surface, |
| - a << 24 | y << 16 | u << 8 | v); |
| - |
| - return; |
| - } |
| - |
| dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); |
| blt_cmd = XY_COLOR_BLT_CMD; |
| pitch = obj_surface->width; |
| diff --git a/src/intel_common_vpp_internal.c b/src/intel_common_vpp_internal.c |
| index c3fddf1233c9..a5efcaabd9ab 100644 |
| --- a/src/intel_common_vpp_internal.c |
| +++ b/src/intel_common_vpp_internal.c |
| @@ -277,17 +277,3 @@ intel_common_scaling_post_processing(VADriverContextP ctx, |
| |
| return status; |
| } |
| - |
| -void |
| -intel_common_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color) |
| -{ |
| - struct i965_driver_data *i965 = i965_driver_data(ctx); |
| - |
| - if (IS_GEN8(i965->intel.device_info)) |
| - gen8_clear_surface(ctx, pp_context, obj_surface, color); |
| - else |
| - gen9_clear_surface(ctx, pp_context, obj_surface, color); |
| -} |
| diff --git a/src/intel_common_vpp_internal.h b/src/intel_common_vpp_internal.h |
| index 5ac71c28d318..b0c4e9befa5b 100644 |
| --- a/src/intel_common_vpp_internal.h |
| +++ b/src/intel_common_vpp_internal.h |
| @@ -29,8 +29,6 @@ |
| #ifndef _INTEL_COMMON_VPP_INTERNAL_H_ |
| #define _INTEL_COMMON_VPP_INTERNAL_H_ |
| |
| -struct object_surface; |
| - |
| /* the below is defined for YUV420 format scaling */ |
| #define SRC_MSB 0x0001 |
| #define DST_MSB 0x0002 |
| @@ -106,12 +104,6 @@ struct scaling_input_parameter { |
| unsigned int reserved[8]; |
| }; |
| |
| -/* 4 Registers or 32 DWs */ |
| -struct clear_input_parameter { |
| - unsigned int color; /* ayvu */ |
| - unsigned int reserved[31]; |
| -}; |
| - |
| VAStatus |
| gen9_yuv420p8_scaling_post_processing( |
| VADriverContextP ctx, |
| @@ -162,16 +154,4 @@ gen9_p010_scaling_post_processing(VADriverContextP ctx, |
| struct i965_surface *dst_surface, |
| VARectangle *dst_rect); |
| |
| -void |
| -gen8_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color); |
| - |
| -void |
| -gen9_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color); |
| - |
| #endif // _INTEL_COMMON_VPP_INTERNAL_H_ |
| diff --git a/src/intel_gen_vppapi.h b/src/intel_gen_vppapi.h |
| index 40aec7c737cd..f3253c46d8af 100644 |
| --- a/src/intel_gen_vppapi.h |
| +++ b/src/intel_gen_vppapi.h |
| @@ -45,10 +45,4 @@ intel_common_scaling_post_processing(VADriverContextP ctx, |
| struct i965_surface *dst_surface, |
| const VARectangle *dst_rect); |
| |
| -void |
| -intel_common_clear_surface(VADriverContextP ctx, |
| - struct i965_post_processing_context *pp_context, |
| - const struct object_surface *obj_surface, |
| - unsigned int color); |
| - |
| #endif // _INTE_GEN_VPPAPI_H_ |
| diff --git a/src/shaders/post_processing/gen8/Makefile.am b/src/shaders/post_processing/gen8/Makefile.am |
| index dfa7d31e1396..131e0fcfda85 100644 |
| --- a/src/shaders/post_processing/gen8/Makefile.am |
| +++ b/src/shaders/post_processing/gen8/Makefile.am |
| @@ -19,15 +19,6 @@ INTEL_PP_PRE_G8B = \ |
| conv_nv12.g8b \ |
| conv_8bit_420_rgb32.g8b |
| |
| -INTEL_PP2_G8B = \ |
| - clear_bgrx.g8b \ |
| - clear_pl2_8bit.g8b \ |
| - clear_pl3_8bit.g8b \ |
| - clear_rgbx.g8b \ |
| - clear_yuy2.g8b \ |
| - clear_uyvy.g8b \ |
| - $(NULL) |
| - |
| INTEL_PP_G8A = \ |
| EOT.g8a \ |
| PL2_AVS_Buf_0.g8a \ |
| @@ -61,12 +52,9 @@ INTEL_PP_G8A = \ |
| INTEL_PP_ASM = $(INTEL_PP_G8B:%.g8b=%.asm) |
| INTEL_PP_GEN8_ASM = $(INTEL_PP_G8B:%.g8b=%.g8s) |
| |
| -INTEL_PP2_GXA = $(INTEL_PP2_G8B:%.g8b=%.gxa) |
| -INTEL_PP2_GXS = $(INTEL_PP2_G8B:%.gxa=%.gxs) |
| - |
| TARGETS = |
| if HAVE_GEN4ASM |
| -TARGETS += $(INTEL_PP_G8B) $(INTEL_PP2_G8B) |
| +TARGETS += $(INTEL_PP_G8B) |
| endif |
| |
| all-local: $(TARGETS) |
| @@ -81,16 +69,9 @@ $(INTEL_PP_GEN8_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G8A) |
| rm _pp0.$@ |
| .g8s.g8b: |
| $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 8 $< |
| - |
| -.gxa.gxs: |
| - $(AM_V_GEN)cpp -P $< > _tmp.$@ && \ |
| - m4 _tmp.$@ > $@ && \ |
| - rm _tmp.$@ |
| -.gxs.g8b: |
| - $(AM_V_GEN)$(GEN4ASM) -o $@ -g 8 $< |
| endif |
| |
| -CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM) $(INTEL_PP2_GXS) |
| +CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM) |
| |
| DISTCLEANFILES = $(TARGETS) |
| |
| @@ -98,9 +79,7 @@ EXTRA_DIST = \ |
| $(INTEL_PP_ASM) \ |
| $(INTEL_PP_G8A) \ |
| $(INTEL_PP_G8B) \ |
| - $(INTEL_PP_PRE_G8B) \ |
| - $(INTEL_PP2_G8B) \ |
| - $(NULL) |
| + $(INTEL_PP_PRE_G8B) |
| |
| # Extra clean files so that maintainer-clean removes *everything* |
| MAINTAINERCLEANFILES = Makefile.in |
| diff --git a/src/shaders/post_processing/gen8/clear_bgrx.g8b b/src/shaders/post_processing/gen8/clear_bgrx.g8b |
| deleted file mode 100644 |
| index e88addb70769..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_bgrx.g8b |
| +++ /dev/null |
| @@ -1,21 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_bgrx.gxa b/src/shaders/post_processing/gen8/clear_bgrx.gxa |
| deleted file mode 100644 |
| index 0e2e4067db09..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_bgrx.gxa |
| +++ /dev/null |
| @@ -1,87 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Red */ |
| -define(`R', `g1.2<0,1,0>UB') |
| -/* Green */ |
| -define(`G', `g1.1<0,1,0>UB') |
| -/* Blue */ |
| -define(`B', `g1.0<0,1,0>UB') |
| - |
| -define(`BGRX_BTI', `1') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* RGBA/RGBX */ |
| -shl(1) g16.0<1>UD ORIGX 6:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(1) g17.3<1>UB ALPHA {align1}; |
| -mov(1) g17.2<1>UB B {align1}; |
| -mov(1) g17.1<1>UB G {align1}; |
| -mov(1) g17.0<1>UB R {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b b/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b |
| deleted file mode 100644 |
| index 534c02ba60fb..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b |
| +++ /dev/null |
| @@ -1,18 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00040004 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x0007000f }, |
| - { 0x00200001, 0x22201248, 0x00000020, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x0a0a8002 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa b/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa |
| deleted file mode 100644 |
| index ece0eb80b3d4..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa |
| +++ /dev/null |
| @@ -1,96 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(2) g16.0<1>UD ORIG 4:w {align1}; |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(4) g17.0<1>UB Y {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* UV */ |
| -shl(1) g16.0<1>UD ORIGX 4:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 3:w {align1}; |
| - |
| -/* 16x8 block */ |
| -mov(1) g16.8<1>UD 0x0007000fUD {align1}; |
| - |
| -mov(2) g17.0<1>UW CBCR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CBCR_BTI, 0, 10, 12) mlen 5 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b b/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b |
| deleted file mode 100644 |
| index 0c4c5ceac9dc..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b |
| +++ /dev/null |
| @@ -1,20 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00030003 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x00070007 }, |
| - { 0x00400001, 0x22202288, 0x00000020, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8002 }, |
| - { 0x00400001, 0x22202288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8003 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa b/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa |
| deleted file mode 100644 |
| index 67662681e8c7..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa |
| +++ /dev/null |
| @@ -1,109 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(2) g16.0<1>UD ORIG 4:w {align1}; |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(4) g17.0<1>UB Y {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* U */ |
| -shl(1) g16.0<1>UD ORIGX 3:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 3:w {align1}; |
| - |
| -/* 8x8 block */ |
| -mov(1) g16.8<1>UD 0x00070007UD {align1}; |
| - |
| -mov(4) g17.0<1>UB CB {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| - |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; |
| - |
| -/* V */ |
| -mov(4) g17.0<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| - |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen8/clear_rgbx.g8b b/src/shaders/post_processing/gen8/clear_rgbx.g8b |
| deleted file mode 100644 |
| index e88addb70769..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_rgbx.g8b |
| +++ /dev/null |
| @@ -1,21 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_rgbx.gxa b/src/shaders/post_processing/gen8/clear_rgbx.gxa |
| deleted file mode 100644 |
| index 5ca6ea758702..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_rgbx.gxa |
| +++ /dev/null |
| @@ -1,87 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Red */ |
| -define(`R', `g1.2<0,1,0>UB') |
| -/* Green */ |
| -define(`G', `g1.1<0,1,0>UB') |
| -/* Blue */ |
| -define(`B', `g1.0<0,1,0>UB') |
| - |
| -define(`RGBX_BTI', `1') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* RGBA/RGBX */ |
| -shl(1) g16.0<1>UD ORIGX 6:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(1) g17.3<1>UB ALPHA {align1}; |
| -mov(1) g17.2<1>UB B {align1}; |
| -mov(1) g17.1<1>UB G {align1}; |
| -mov(1) g17.0<1>UB R {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen8/clear_uyvy.g8b b/src/shaders/post_processing/gen8/clear_uyvy.g8b |
| deleted file mode 100644 |
| index b6675acb2f99..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_uyvy.g8b |
| +++ /dev/null |
| @@ -1,16 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00200001, 0x42212288, 0x00000022, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_uyvy.gxa b/src/shaders/post_processing/gen8/clear_uyvy.gxa |
| deleted file mode 100644 |
| index 8dffacc9e578..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_uyvy.gxa |
| +++ /dev/null |
| @@ -1,84 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(1) g16.0<1>UD ORIGX 5:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(2) g17.1<2>UB Y {align1}; |
| -mov(1) g17.0<1>UB CB {align1}; |
| -mov(1) g17.2<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen8/clear_yuy2.g8b b/src/shaders/post_processing/gen8/clear_yuy2.g8b |
| deleted file mode 100644 |
| index 493d7abffaab..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_yuy2.g8b |
| +++ /dev/null |
| @@ -1,16 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00200001, 0x42202288, 0x00000022, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22232288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen8/clear_yuy2.gxa b/src/shaders/post_processing/gen8/clear_yuy2.gxa |
| deleted file mode 100644 |
| index d6840a9abcf7..000000000000 |
| --- a/src/shaders/post_processing/gen8/clear_yuy2.gxa |
| +++ /dev/null |
| @@ -1,84 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(1) g16.0<1>UD ORIGX 5:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(2) g17.0<2>UB Y {align1}; |
| -mov(1) g17.1<1>UB CB {align1}; |
| -mov(1) g17.3<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/Makefile.am b/src/shaders/post_processing/gen9/Makefile.am |
| index eb127c3735c5..7fd91d3913e7 100644 |
| --- a/src/shaders/post_processing/gen9/Makefile.am |
| +++ b/src/shaders/post_processing/gen9/Makefile.am |
| @@ -21,15 +21,6 @@ INTEL_PP_G9B = \ |
| pa_to_pa.g9b \ |
| $(NULL) |
| |
| -INTEL_PP2_G9B = \ |
| - clear_bgrx.g9b \ |
| - clear_pl2_8bit.g9b \ |
| - clear_pl3_8bit.g9b \ |
| - clear_rgbx.g9b \ |
| - clear_yuy2.g9b \ |
| - clear_uyvy.g9b \ |
| - $(NULL) |
| - |
| INTEL_PP_G8A = \ |
| EOT.g8a \ |
| PL2_AVS_Buf_0.g8a \ |
| @@ -62,17 +53,14 @@ INTEL_PP_G9A = $(INTEL_PP_G8A) |
| INTEL_PP_ASM = $(INTEL_PP_G9B:%.g9b=%.asm) |
| INTEL_PP_GEN9_ASM = $(INTEL_PP_G9B:%.g9b=%.g9s) |
| |
| -INTEL_PP2_GXA = $(INTEL_PP2_G9B:%.g9b=%.gxa) |
| -INTEL_PP2_GXS = $(INTEL_PP2_G9B:%.gxa=%.gxs) |
| - |
| TARGETS = |
| if HAVE_GEN4ASM |
| -TARGETS += $(INTEL_PP_G9B) $(INTEL_PP2_G9B) |
| +TARGETS += $(INTEL_PP_G9B) |
| endif |
| |
| all-local: $(TARGETS) |
| |
| -SUFFIXES = .g9b .g9s .asm .gxa .gxs |
| +SUFFIXES = .g9b .g9s .asm |
| |
| if HAVE_GEN4ASM |
| $(INTEL_PP_GEN9_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G9A) |
| @@ -82,23 +70,15 @@ $(INTEL_PP_GEN9_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G9A) |
| rm _pp0.$@ |
| .g9s.g9b: |
| $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 9 $< |
| - |
| -.gxa.gxs: |
| - $(AM_V_GEN)cpp -P $< > _tmp.$@ && \ |
| - m4 _tmp.$@ > $@ && \ |
| - rm _tmp.$@ |
| -.gxs.g9b: |
| - $(AM_V_GEN)$(GEN4ASM) -o $@ -g 9 $< |
| endif |
| |
| -CLEANFILES = $(INTEL_PP_GEN9_ASM) $(INTEL_PP2_GXS) |
| +CLEANFILES = $(INTEL_PP_GEN9_ASM) |
| |
| DISTCLEANFILES = $(TARGETS) |
| |
| EXTRA_DIST = \ |
| $(INTEL_PP_G9B) \ |
| $(INTEL_PP_PRE_G9B) \ |
| - $(INTEL_PP2_G9B) \ |
| $(NULL) |
| |
| # Extra clean files so that maintainer-clean removes *everything* |
| diff --git a/src/shaders/post_processing/gen9/clear_bgrx.g9b b/src/shaders/post_processing/gen9/clear_bgrx.g9b |
| deleted file mode 100644 |
| index 2f4ede0752a7..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_bgrx.g9b |
| +++ /dev/null |
| @@ -1,21 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_bgrx.gxa b/src/shaders/post_processing/gen9/clear_bgrx.gxa |
| deleted file mode 100644 |
| index 0e2e4067db09..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_bgrx.gxa |
| +++ /dev/null |
| @@ -1,87 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Red */ |
| -define(`R', `g1.2<0,1,0>UB') |
| -/* Green */ |
| -define(`G', `g1.1<0,1,0>UB') |
| -/* Blue */ |
| -define(`B', `g1.0<0,1,0>UB') |
| - |
| -define(`BGRX_BTI', `1') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* RGBA/RGBX */ |
| -shl(1) g16.0<1>UD ORIGX 6:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(1) g17.3<1>UB ALPHA {align1}; |
| -mov(1) g17.2<1>UB B {align1}; |
| -mov(1) g17.1<1>UB G {align1}; |
| -mov(1) g17.0<1>UB R {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/clear_pl2_8bit.g9b b/src/shaders/post_processing/gen9/clear_pl2_8bit.g9b |
| deleted file mode 100644 |
| index a66b02a6faa6..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_pl2_8bit.g9b |
| +++ /dev/null |
| @@ -1,18 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00040004 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x0007000f }, |
| - { 0x00200001, 0x22201248, 0x00000020, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x0a0a8002 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_pl2_8bit.gxa b/src/shaders/post_processing/gen9/clear_pl2_8bit.gxa |
| deleted file mode 100644 |
| index ece0eb80b3d4..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_pl2_8bit.gxa |
| +++ /dev/null |
| @@ -1,96 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(2) g16.0<1>UD ORIG 4:w {align1}; |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(4) g17.0<1>UB Y {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* UV */ |
| -shl(1) g16.0<1>UD ORIGX 4:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 3:w {align1}; |
| - |
| -/* 16x8 block */ |
| -mov(1) g16.8<1>UD 0x0007000fUD {align1}; |
| - |
| -mov(2) g17.0<1>UW CBCR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CBCR_BTI, 0, 10, 12) mlen 5 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/clear_pl3_8bit.g9b b/src/shaders/post_processing/gen9/clear_pl3_8bit.g9b |
| deleted file mode 100644 |
| index 7a6d03d5d2a5..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_pl3_8bit.g9b |
| +++ /dev/null |
| @@ -1,20 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00030003 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x00070007 }, |
| - { 0x00400001, 0x22202288, 0x00000020, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x060a8002 }, |
| - { 0x00400001, 0x22202288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x060a8003 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_pl3_8bit.gxa b/src/shaders/post_processing/gen9/clear_pl3_8bit.gxa |
| deleted file mode 100644 |
| index 67662681e8c7..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_pl3_8bit.gxa |
| +++ /dev/null |
| @@ -1,109 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(2) g16.0<1>UD ORIG 4:w {align1}; |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(4) g17.0<1>UB Y {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* U */ |
| -shl(1) g16.0<1>UD ORIGX 3:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 3:w {align1}; |
| - |
| -/* 8x8 block */ |
| -mov(1) g16.8<1>UD 0x00070007UD {align1}; |
| - |
| -mov(4) g17.0<1>UB CB {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| - |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; |
| - |
| -/* V */ |
| -mov(4) g17.0<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| - |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/clear_rgbx.g9b b/src/shaders/post_processing/gen9/clear_rgbx.g9b |
| deleted file mode 100644 |
| index 2f4ede0752a7..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_rgbx.g9b |
| +++ /dev/null |
| @@ -1,21 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_rgbx.gxa b/src/shaders/post_processing/gen9/clear_rgbx.gxa |
| deleted file mode 100644 |
| index 5ca6ea758702..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_rgbx.gxa |
| +++ /dev/null |
| @@ -1,87 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Red */ |
| -define(`R', `g1.2<0,1,0>UB') |
| -/* Green */ |
| -define(`G', `g1.1<0,1,0>UB') |
| -/* Blue */ |
| -define(`B', `g1.0<0,1,0>UB') |
| - |
| -define(`RGBX_BTI', `1') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* RGBA/RGBX */ |
| -shl(1) g16.0<1>UD ORIGX 6:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(1) g17.3<1>UB ALPHA {align1}; |
| -mov(1) g17.2<1>UB B {align1}; |
| -mov(1) g17.1<1>UB G {align1}; |
| -mov(1) g17.0<1>UB R {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/clear_uyvy.g9b b/src/shaders/post_processing/gen9/clear_uyvy.g9b |
| deleted file mode 100644 |
| index 1c6ab920b68f..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_uyvy.g9b |
| +++ /dev/null |
| @@ -1,16 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00200001, 0x42212288, 0x00000022, 0x00000000 }, |
| - { 0x00000001, 0x22202288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22222288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_uyvy.gxa b/src/shaders/post_processing/gen9/clear_uyvy.gxa |
| deleted file mode 100644 |
| index 8dffacc9e578..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_uyvy.gxa |
| +++ /dev/null |
| @@ -1,84 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(1) g16.0<1>UD ORIGX 5:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(2) g17.1<2>UB Y {align1}; |
| -mov(1) g17.0<1>UB CB {align1}; |
| -mov(1) g17.2<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| diff --git a/src/shaders/post_processing/gen9/clear_yuy2.g9b b/src/shaders/post_processing/gen9/clear_yuy2.g9b |
| deleted file mode 100644 |
| index 6c2345d89035..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_yuy2.g9b |
| +++ /dev/null |
| @@ -1,16 +0,0 @@ |
| - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, |
| - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, |
| - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, |
| - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, |
| - { 0x00200001, 0x42202288, 0x00000022, 0x00000000 }, |
| - { 0x00000001, 0x22212288, 0x00000020, 0x00000000 }, |
| - { 0x00000001, 0x22232288, 0x00000021, 0x00000000 }, |
| - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, |
| - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, |
| - { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 }, |
| - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, |
| - { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 }, |
| diff --git a/src/shaders/post_processing/gen9/clear_yuy2.gxa b/src/shaders/post_processing/gen9/clear_yuy2.gxa |
| deleted file mode 100644 |
| index d6840a9abcf7..000000000000 |
| --- a/src/shaders/post_processing/gen9/clear_yuy2.gxa |
| +++ /dev/null |
| @@ -1,84 +0,0 @@ |
| -/* |
| - * Copyright © 2018 Intel Corporation |
| - * |
| - * Permission is hereby granted, free of charge, to any person obtaining a |
| - * copy of this software and associated documentation files (the |
| - * "Software"), to deal in the Software without restriction, including |
| - * without limitation the rights to use, copy, modify, merge, publish, |
| - * distribute, sub license, and/or sell copies of the Software, and to |
| - * permit persons to whom the Software is furnished to do so, subject to |
| - * the following conditions: |
| - * |
| - * The above copyright notice and this permission notice (including the |
| - * next paragraph) shall be included in all copies or substantial portions |
| - * of the Software. |
| - * |
| - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| - * |
| - * Authors: |
| - * Xiang Haihao <haihao.xiang@intel.com> |
| - * |
| - */ |
| - |
| -/* |
| - * Registers |
| - * g0 header |
| - * g1-g3 static parameters (constant) |
| - * g16-g24 payload for write message |
| - */ |
| -define(`ORIG', `g0.4<2,2,1>UW') |
| -define(`ORIGX', `g0.4<0,1,0>UW') |
| -define(`ORIGY', `g0.6<0,1,0>UW') |
| - |
| -define(`ALPHA', `g1.3<0,1,0>UB') |
| -/* Y */ |
| -define(`Y', `g1.2<0,1,0>UB') |
| -/* V */ |
| -define(`CR', `g1.1<0,1,0>UB') |
| -/* U */ |
| -define(`CB', `g1.0<0,1,0>UB') |
| -define(`CBCR', `g1.0<0,1,0>UW') |
| - |
| -define(`Y_BTI', `1') |
| -define(`CB_BTI', `2') |
| -define(`CBCR_BTI', `2') |
| -define(`CR_BTI', `3') |
| - |
| -/* Thread header */ |
| -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; |
| - |
| -/* Y */ |
| -shl(1) g16.0<1>UD ORIGX 5:w {align1}; |
| -shl(1) g16.4<1>UD ORIGY 4:w {align1}; |
| - |
| -/* 16x16 block */ |
| -mov(1) g16.8<1>UD 0x000f000fUD {align1}; |
| - |
| -mov(2) g17.0<2>UB Y {align1}; |
| -mov(1) g17.1<1>UB CB {align1}; |
| -mov(1) g17.3<1>UB CR {align1}; |
| -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; |
| -/* |
| - * write(p0, p1, p2, p3) |
| - * p0: binding table index |
| - * p1: message control, default is 0, |
| - * p2: message type, 10 is media_block_write |
| - * p3: cache type, 12 is data cache data port 1 |
| - */ |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; |
| -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; |
| - |
| -/* EOT */ |
| -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; |
| -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| -- |
| 2.19.0 |
| |
