| # Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command: |
| # t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 4.90196 |
| # -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o Nike_0121_2GB_204Mhz.cfg |
| # -b NIKE_0121_204MHz_emc_reg.txt |
| # Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 4.90 ns (204.00 MHz) |
| # bkv file: NIKE_0121_204MHz_emc_reg.txt |
| SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[0].PllMInputDivider = 0x00000001; |
| SDRAM[0].PllMFeedbackDivider = 0x00000022; |
| SDRAM[0].PllMStableTime = 0x0000012c; |
| SDRAM[0].PllMSetupControl = 0x00000000; |
| SDRAM[0].PllMSelectDiv2 = 0x00000000; |
| SDRAM[0].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[0].PllMKCP = 0x00000000; |
| SDRAM[0].PllMKVCO = 0x00000000; |
| SDRAM[0].EmcBctSpare0 = 0x00000000; |
| SDRAM[0].EmcBctSpare1 = 0x00000000; |
| SDRAM[0].EmcBctSpare2 = 0x00000000; |
| SDRAM[0].EmcBctSpare3 = 0x00000000; |
| SDRAM[0].EmcBctSpare4 = 0x00000000; |
| SDRAM[0].EmcBctSpare5 = 0x00000000; |
| SDRAM[0].EmcBctSpare6 = 0x00000000; |
| SDRAM[0].EmcBctSpare7 = 0x00000000; |
| SDRAM[0].EmcBctSpare8 = 0x00000000; |
| SDRAM[0].EmcBctSpare9 = 0x00000000; |
| SDRAM[0].EmcBctSpare10 = 0x00000000; |
| SDRAM[0].EmcBctSpare11 = 0x00000000; |
| SDRAM[0].EmcClockSource = 0x40000002; |
| SDRAM[0].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[0].EmcAutoCalConfig = 0xa1430000; |
| SDRAM[0].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[0].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[0].EmcAutoCalWait = 0x00000190; |
| SDRAM[0].EmcAdrCfg = 0x00000000; |
| SDRAM[0].EmcPinProgramWait = 0x00000001; |
| SDRAM[0].EmcPinExtraWait = 0x00000000; |
| SDRAM[0].EmcTimingControlWait = 0x00000000; |
| SDRAM[0].EmcRc = 0x00000009; |
| SDRAM[0].EmcRfc = 0x00000035; |
| SDRAM[0].EmcRfcSlr = 0x00000000; |
| SDRAM[0].EmcRas = 0x00000007; |
| SDRAM[0].EmcRp = 0x00000002; |
| SDRAM[0].EmcR2r = 0x00000000; |
| SDRAM[0].EmcW2w = 0x00000000; |
| SDRAM[0].EmcR2w = 0x00000005; |
| SDRAM[0].EmcW2r = 0x0000000a; |
| SDRAM[0].EmcR2p = 0x00000003; |
| SDRAM[0].EmcW2p = 0x0000000b; |
| SDRAM[0].EmcRdRcd = 0x00000002; |
| SDRAM[0].EmcWrRcd = 0x00000002; |
| SDRAM[0].EmcRrd = 0x00000003; |
| SDRAM[0].EmcRext = 0x00000003; |
| SDRAM[0].EmcWext = 0x00000000; |
| SDRAM[0].EmcWdv = 0x00000005; |
| SDRAM[0].EmcWdvMask = 0x00000005; |
| SDRAM[0].EmcQUse = 0x00000006; |
| SDRAM[0].EmcQuseWidth = 0x00000002; |
| SDRAM[0].EmcIbdly = 0x00000000; |
| SDRAM[0].EmcEInput = 0x00000004; |
| SDRAM[0].EmcEInputDuration = 0x00000006; |
| SDRAM[0].EmcPutermExtra = 0x00010000; |
| SDRAM[0].EmcPutermWidth = 0x00000003; |
| SDRAM[0].EmcPutermAdj = 0x00000000; |
| SDRAM[0].EmcCdbCntl1 = 0x00000000; |
| SDRAM[0].EmcCdbCntl2 = 0x00000000; |
| SDRAM[0].EmcCdbCntl3 = 0x00000000; |
| SDRAM[0].EmcQRst = 0x00000003; |
| SDRAM[0].EmcQSafe = 0x0000000d; |
| SDRAM[0].EmcRdv = 0x0000000f; |
| SDRAM[0].EmcRdvMask = 0x00000011; |
| SDRAM[0].EmcQpop = 0x0000000a; |
| SDRAM[0].EmcCtt = 0x00000000; |
| SDRAM[0].EmcCttDuration = 0x00000003; |
| SDRAM[0].EmcRefresh = 0x00000607; |
| SDRAM[0].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[0].EmcPreRefreshReqCnt = 0x00000181; |
| SDRAM[0].EmcPdEx2Wr = 0x00000002; |
| SDRAM[0].EmcPdEx2Rd = 0x00000002; |
| SDRAM[0].EmcPChg2Pden = 0x00000001; |
| SDRAM[0].EmcAct2Pden = 0x00000000; |
| SDRAM[0].EmcAr2Pden = 0x00000032; |
| SDRAM[0].EmcRw2Pden = 0x0000000f; |
| SDRAM[0].EmcTxsr = 0x00000038; |
| SDRAM[0].EmcTxsrDll = 0x00000038; |
| SDRAM[0].EmcTcke = 0x00000004; |
| SDRAM[0].EmcTckesr = 0x00000005; |
| SDRAM[0].EmcTpd = 0x00000004; |
| SDRAM[0].EmcTfaw = 0x00000007; |
| SDRAM[0].EmcTrpab = 0x00000000; |
| SDRAM[0].EmcTClkStable = 0x00000005; |
| SDRAM[0].EmcTClkStop = 0x00000005; |
| SDRAM[0].EmcTRefBw = 0x00000638; |
| SDRAM[0].EmcFbioCfg5 = 0x106aa298; |
| SDRAM[0].EmcFbioCfg6 = 0x00000000; |
| SDRAM[0].EmcFbioSpare = 0x00000000; |
| SDRAM[0].EmcCfgRsv = 0xff00ff00; |
| SDRAM[0].EmcMrs = 0x80001221; |
| SDRAM[0].EmcEmrs = 0x80100003; |
| SDRAM[0].EmcEmrs2 = 0x80200008; |
| SDRAM[0].EmcEmrs3 = 0x80300000; |
| SDRAM[0].EmcMrw1 = 0x00000000; |
| SDRAM[0].EmcMrw2 = 0x00000000; |
| SDRAM[0].EmcMrw3 = 0x00000000; |
| SDRAM[0].EmcMrw4 = 0x00000000; |
| SDRAM[0].EmcMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcMrwResetCommand = 0x00000000; |
| SDRAM[0].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[0].EmcMrsWaitCnt = 0x000c000c; |
| SDRAM[0].EmcMrsWaitCnt2 = 0x000c000c; |
| SDRAM[0].EmcCfg = 0x73240000; |
| SDRAM[0].EmcCfg2 = 0x0000088d; |
| SDRAM[0].EmcCfgPipe = 0x0000d2b3; |
| SDRAM[0].EmcDbg = 0x01000c00; |
| SDRAM[0].EmcCmdQ = 0x10004408; |
| SDRAM[0].EmcMc2EmcQ = 0x06000404; |
| SDRAM[0].EmcDynSelfRefControl = 0x80000d22; |
| SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[0].EmcCfgDigDll = 0x002c00a0; |
| SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[0].EmcDevSelect = 0x00000002; |
| SDRAM[0].EmcSelDpdCtrl = 0x00040008; |
| SDRAM[0].EmcDllXformDqs0 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs1 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs2 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs3 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs4 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs5 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs6 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs7 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs8 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs9 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs10 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs11 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs12 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs13 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs14 = 0x00064000; |
| SDRAM[0].EmcDllXformDqs15 = 0x00064000; |
| SDRAM[0].EmcDllXformQUse0 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse1 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse2 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse3 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse4 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse5 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse6 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse7 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr0 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr1 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr2 = 0x00004000; |
| SDRAM[0].EmcDllXformAddr3 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr4 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr5 = 0x00004000; |
| SDRAM[0].EmcDllXformQUse8 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse9 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse10 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse11 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse12 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse13 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse14 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse15 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; |
| SDRAM[0].EmcDllXformDq0 = 0x00090000; |
| SDRAM[0].EmcDllXformDq1 = 0x00090000; |
| SDRAM[0].EmcDllXformDq2 = 0x00094000; |
| SDRAM[0].EmcDllXformDq3 = 0x00094000; |
| SDRAM[0].EmcDllXformDq4 = 0x00009400; |
| SDRAM[0].EmcDllXformDq5 = 0x00009000; |
| SDRAM[0].EmcDllXformDq6 = 0x00009000; |
| SDRAM[0].EmcDllXformDq7 = 0x00009000; |
| SDRAM[0].WarmBootWait = 0x00000002; |
| SDRAM[0].EmcCttTermCtrl = 0x00000802; |
| SDRAM[0].EmcOdtWrite = 0x00000000; |
| SDRAM[0].EmcOdtRead = 0x00000000; |
| SDRAM[0].EmcZcalInterval = 0x00020000; |
| SDRAM[0].EmcZcalWaitCnt = 0x00000042; |
| SDRAM[0].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[0].EmcMrsResetDll = 0x00000000; |
| SDRAM[0].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[0].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[0].EmcZcalInitWait = 0x00000003; |
| SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; |
| SDRAM[0].EmcZcalWarmBootWait = 0x00000002; |
| SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[0].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[0].EmcMrsExtra = 0x80001221; |
| SDRAM[0].EmcWarmBootMrsExtra = 0x80100003; |
| SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[0].EmcDdr2Wait = 0x00000000; |
| SDRAM[0].EmcClkenOverride = 0x00000000; |
| SDRAM[0].McDisExtraSnapLevels = 0x00000000; |
| SDRAM[0].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[0].PmcVddpSel = 0x00000002; |
| SDRAM[0].PmcVddpSelWait = 0x00000002; |
| SDRAM[0].PmcDdrPwr = 0x00000003; |
| SDRAM[0].PmcDdrCfg = 0x00002002; |
| SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; |
| SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; |
| SDRAM[0].PmcRegShort = 0x00000000; |
| SDRAM[0].PmcNoIoPower = 0x00000000; |
| SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; |
| SDRAM[0].EmcXm2CmdPadCtrl = 0x10000280; |
| SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; |
| SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0130b118; |
| SDRAM[0].EmcXm2DqsPadCtrl3 = 0x51451400; |
| SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; |
| SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; |
| SDRAM[0].EmcXm2DqsPadCtrl6 = 0x51451400; |
| SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; |
| SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc081; |
| SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; |
| SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; |
| SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x0000003f; |
| SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; |
| SDRAM[0].EmcAcpdControl = 0x00000000; |
| SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; |
| SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; |
| SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; |
| SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; |
| SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; |
| SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; |
| SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; |
| SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; |
| SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; |
| SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; |
| SDRAM[0].EmcDsrVttgenDrv = 0x0000003f; |
| SDRAM[0].EmcTxdsrvttgen = 0x00000066; |
| SDRAM[0].EmcBgbiasCtl0 = 0x00000008; |
| SDRAM[0].McEmemAdrCfg = 0x00000000; |
| SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; |
| SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; |
| SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; |
| SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; |
| SDRAM[0].McEmemCfg = 0x00000800; |
| SDRAM[0].McEmemArbCfg = 0x01000003; |
| SDRAM[0].McEmemArbOutstandingReq = 0x80000040; |
| SDRAM[0].McEmemArbTimingRcd = 0x00000001; |
| SDRAM[0].McEmemArbTimingRp = 0x00000001; |
| SDRAM[0].McEmemArbTimingRc = 0x00000005; |
| SDRAM[0].McEmemArbTimingRas = 0x00000002; |
| SDRAM[0].McEmemArbTimingFaw = 0x00000004; |
| SDRAM[0].McEmemArbTimingRrd = 0x00000001; |
| SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002; |
| SDRAM[0].McEmemArbTimingWap2Pre = 0x00000008; |
| SDRAM[0].McEmemArbTimingR2R = 0x00000003; |
| SDRAM[0].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[0].McEmemArbTimingR2W = 0x00000004; |
| SDRAM[0].McEmemArbTimingW2R = 0x00000006; |
| SDRAM[0].McEmemArbDaTurns = 0x06040203; |
| SDRAM[0].McEmemArbDaCovers = 0x000a0405; |
| SDRAM[0].McEmemArbMisc0 = 0x73840a06; |
| SDRAM[0].McEmemArbMisc1 = 0x70000f03; |
| SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[0].McEmemArbOverride = 0x10000000; |
| SDRAM[0].McEmemArbOverride1 = 0x00000000; |
| SDRAM[0].McEmemArbRsv = 0xff00ff00; |
| SDRAM[0].McClkenOverride = 0x00000000; |
| SDRAM[0].McStatControl = 0x00000000; |
| SDRAM[0].McDisplaySnapRing = 0x00000003; |
| SDRAM[0].McVideoProtectBom = 0xfff00000; |
| SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[0].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; |
| SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; |
| SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[0].McSecCarveoutBom = 0xfff00000; |
| SDRAM[0].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[0].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[0].SwizzleRankByteEncode = 0x0000006f; |
| SDRAM[0].BootRomPatchControl = 0x00000000; |
| SDRAM[0].BootRomPatchData = 0x00000000; |
| SDRAM[0].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000001; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x00000062; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff003c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x004e0049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080057; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff0063; |
| #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00ff0036; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff006b; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510050; |
| #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff006d; |
| |
| # Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command: |
| # t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 4.90196 |
| # -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o Nike_0121_2GB_204Mhz.cfg |
| # -b NIKE_0121_204MHz_emc_reg.txt |
| # Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 4.90 ns (204.00 MHz) |
| # bkv file: NIKE_0121_204MHz_emc_reg.txt |
| SDRAM[1].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[1].PllMInputDivider = 0x00000001; |
| SDRAM[1].PllMFeedbackDivider = 0x00000022; |
| SDRAM[1].PllMStableTime = 0x0000012c; |
| SDRAM[1].PllMSetupControl = 0x00000000; |
| SDRAM[1].PllMSelectDiv2 = 0x00000000; |
| SDRAM[1].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[1].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[1].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[1].PllMKCP = 0x00000000; |
| SDRAM[1].PllMKVCO = 0x00000000; |
| SDRAM[1].EmcBctSpare0 = 0x00000000; |
| SDRAM[1].EmcBctSpare1 = 0x00000000; |
| SDRAM[1].EmcBctSpare2 = 0x00000000; |
| SDRAM[1].EmcBctSpare3 = 0x00000000; |
| SDRAM[1].EmcBctSpare4 = 0x00000000; |
| SDRAM[1].EmcBctSpare5 = 0x00000000; |
| SDRAM[1].EmcBctSpare6 = 0x00000000; |
| SDRAM[1].EmcBctSpare7 = 0x00000000; |
| SDRAM[1].EmcBctSpare8 = 0x00000000; |
| SDRAM[1].EmcBctSpare9 = 0x00000000; |
| SDRAM[1].EmcBctSpare10 = 0x00000000; |
| SDRAM[1].EmcBctSpare11 = 0x00000000; |
| SDRAM[1].EmcClockSource = 0x40000002; |
| SDRAM[1].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[1].EmcAutoCalConfig = 0xa1430000; |
| SDRAM[1].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[1].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[1].EmcAutoCalWait = 0x00000190; |
| SDRAM[1].EmcAdrCfg = 0x00000000; |
| SDRAM[1].EmcPinProgramWait = 0x00000001; |
| SDRAM[1].EmcPinExtraWait = 0x00000000; |
| SDRAM[1].EmcTimingControlWait = 0x00000000; |
| SDRAM[1].EmcRc = 0x00000009; |
| SDRAM[1].EmcRfc = 0x00000035; |
| SDRAM[1].EmcRfcSlr = 0x00000000; |
| SDRAM[1].EmcRas = 0x00000007; |
| SDRAM[1].EmcRp = 0x00000002; |
| SDRAM[1].EmcR2r = 0x00000000; |
| SDRAM[1].EmcW2w = 0x00000000; |
| SDRAM[1].EmcR2w = 0x00000005; |
| SDRAM[1].EmcW2r = 0x0000000a; |
| SDRAM[1].EmcR2p = 0x00000003; |
| SDRAM[1].EmcW2p = 0x0000000b; |
| SDRAM[1].EmcRdRcd = 0x00000002; |
| SDRAM[1].EmcWrRcd = 0x00000002; |
| SDRAM[1].EmcRrd = 0x00000003; |
| SDRAM[1].EmcRext = 0x00000003; |
| SDRAM[1].EmcWext = 0x00000000; |
| SDRAM[1].EmcWdv = 0x00000005; |
| SDRAM[1].EmcWdvMask = 0x00000005; |
| SDRAM[1].EmcQUse = 0x00000006; |
| SDRAM[1].EmcQuseWidth = 0x00000002; |
| SDRAM[1].EmcIbdly = 0x00000000; |
| SDRAM[1].EmcEInput = 0x00000004; |
| SDRAM[1].EmcEInputDuration = 0x00000006; |
| SDRAM[1].EmcPutermExtra = 0x00010000; |
| SDRAM[1].EmcPutermWidth = 0x00000003; |
| SDRAM[1].EmcPutermAdj = 0x00000000; |
| SDRAM[1].EmcCdbCntl1 = 0x00000000; |
| SDRAM[1].EmcCdbCntl2 = 0x00000000; |
| SDRAM[1].EmcCdbCntl3 = 0x00000000; |
| SDRAM[1].EmcQRst = 0x00000003; |
| SDRAM[1].EmcQSafe = 0x0000000d; |
| SDRAM[1].EmcRdv = 0x0000000f; |
| SDRAM[1].EmcRdvMask = 0x00000011; |
| SDRAM[1].EmcQpop = 0x0000000a; |
| SDRAM[1].EmcCtt = 0x00000000; |
| SDRAM[1].EmcCttDuration = 0x00000003; |
| SDRAM[1].EmcRefresh = 0x00000607; |
| SDRAM[1].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[1].EmcPreRefreshReqCnt = 0x00000181; |
| SDRAM[1].EmcPdEx2Wr = 0x00000002; |
| SDRAM[1].EmcPdEx2Rd = 0x00000002; |
| SDRAM[1].EmcPChg2Pden = 0x00000001; |
| SDRAM[1].EmcAct2Pden = 0x00000000; |
| SDRAM[1].EmcAr2Pden = 0x00000032; |
| SDRAM[1].EmcRw2Pden = 0x0000000f; |
| SDRAM[1].EmcTxsr = 0x00000038; |
| SDRAM[1].EmcTxsrDll = 0x00000038; |
| SDRAM[1].EmcTcke = 0x00000004; |
| SDRAM[1].EmcTckesr = 0x00000005; |
| SDRAM[1].EmcTpd = 0x00000004; |
| SDRAM[1].EmcTfaw = 0x00000007; |
| SDRAM[1].EmcTrpab = 0x00000000; |
| SDRAM[1].EmcTClkStable = 0x00000005; |
| SDRAM[1].EmcTClkStop = 0x00000005; |
| SDRAM[1].EmcTRefBw = 0x00000638; |
| SDRAM[1].EmcFbioCfg5 = 0x106aa298; |
| SDRAM[1].EmcFbioCfg6 = 0x00000000; |
| SDRAM[1].EmcFbioSpare = 0x00000000; |
| SDRAM[1].EmcCfgRsv = 0xff00ff00; |
| SDRAM[1].EmcMrs = 0x80001221; |
| SDRAM[1].EmcEmrs = 0x80100003; |
| SDRAM[1].EmcEmrs2 = 0x80200008; |
| SDRAM[1].EmcEmrs3 = 0x80300000; |
| SDRAM[1].EmcMrw1 = 0x00000000; |
| SDRAM[1].EmcMrw2 = 0x00000000; |
| SDRAM[1].EmcMrw3 = 0x00000000; |
| SDRAM[1].EmcMrw4 = 0x00000000; |
| SDRAM[1].EmcMrwExtra = 0x00000000; |
| SDRAM[1].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[1].EmcMrwResetCommand = 0x00000000; |
| SDRAM[1].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[1].EmcMrsWaitCnt = 0x000c000c; |
| SDRAM[1].EmcMrsWaitCnt2 = 0x000c000c; |
| SDRAM[1].EmcCfg = 0x73240000; |
| SDRAM[1].EmcCfg2 = 0x0000088d; |
| SDRAM[1].EmcCfgPipe = 0x0000d2b3; |
| SDRAM[1].EmcDbg = 0x01000c00; |
| SDRAM[1].EmcCmdQ = 0x10004408; |
| SDRAM[1].EmcMc2EmcQ = 0x06000404; |
| SDRAM[1].EmcDynSelfRefControl = 0x80000d22; |
| SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[1].EmcCfgDigDll = 0x002c00a0; |
| SDRAM[1].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[1].EmcDevSelect = 0x00000002; |
| SDRAM[1].EmcSelDpdCtrl = 0x00040008; |
| SDRAM[1].EmcDllXformDqs0 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs1 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs2 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs3 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs4 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs5 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs6 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs7 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs8 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs9 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs10 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs11 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs12 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs13 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs14 = 0x00064000; |
| SDRAM[1].EmcDllXformDqs15 = 0x00064000; |
| SDRAM[1].EmcDllXformQUse0 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse1 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse2 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse3 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse4 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse5 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse6 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse7 = 0x00000000; |
| SDRAM[1].EmcDllXformAddr0 = 0x00000000; |
| SDRAM[1].EmcDllXformAddr1 = 0x00000000; |
| SDRAM[1].EmcDllXformAddr2 = 0x00004000; |
| SDRAM[1].EmcDllXformAddr3 = 0x00000000; |
| SDRAM[1].EmcDllXformAddr4 = 0x00000000; |
| SDRAM[1].EmcDllXformAddr5 = 0x00004000; |
| SDRAM[1].EmcDllXformQUse8 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse9 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse10 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse11 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse12 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse13 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse14 = 0x00000000; |
| SDRAM[1].EmcDllXformQUse15 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs8 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs9 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs10 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs11 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs12 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs13 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs14 = 0x00000000; |
| SDRAM[1].EmcDliTrimTxDqs15 = 0x00000000; |
| SDRAM[1].EmcDllXformDq0 = 0x00090000; |
| SDRAM[1].EmcDllXformDq1 = 0x00090000; |
| SDRAM[1].EmcDllXformDq2 = 0x00094000; |
| SDRAM[1].EmcDllXformDq3 = 0x00094000; |
| SDRAM[1].EmcDllXformDq4 = 0x00009400; |
| SDRAM[1].EmcDllXformDq5 = 0x00009000; |
| SDRAM[1].EmcDllXformDq6 = 0x00009000; |
| SDRAM[1].EmcDllXformDq7 = 0x00009000; |
| SDRAM[1].WarmBootWait = 0x00000002; |
| SDRAM[1].EmcCttTermCtrl = 0x00000802; |
| SDRAM[1].EmcOdtWrite = 0x00000000; |
| SDRAM[1].EmcOdtRead = 0x00000000; |
| SDRAM[1].EmcZcalInterval = 0x00020000; |
| SDRAM[1].EmcZcalWaitCnt = 0x00000042; |
| SDRAM[1].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[1].EmcMrsResetDll = 0x00000000; |
| SDRAM[1].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[1].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[1].EmcZcalInitWait = 0x00000003; |
| SDRAM[1].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000000; |
| SDRAM[1].EmcZcalWarmBootWait = 0x00000002; |
| SDRAM[1].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[1].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[1].EmcMrsExtra = 0x80001221; |
| SDRAM[1].EmcWarmBootMrsExtra = 0x80100003; |
| SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[1].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[1].EmcDdr2Wait = 0x00000000; |
| SDRAM[1].EmcClkenOverride = 0x00000000; |
| SDRAM[1].McDisExtraSnapLevels = 0x00000000; |
| SDRAM[1].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[1].PmcVddpSel = 0x00000002; |
| SDRAM[1].PmcVddpSelWait = 0x00000002; |
| SDRAM[1].PmcDdrPwr = 0x00000003; |
| SDRAM[1].PmcDdrCfg = 0x00002002; |
| SDRAM[1].PmcIoDpd3Req = 0x4fff2f97; |
| SDRAM[1].PmcIoDpd3ReqWait = 0x00000000; |
| SDRAM[1].PmcRegShort = 0x00000000; |
| SDRAM[1].PmcNoIoPower = 0x00000000; |
| SDRAM[1].PmcPorDpdCtrlWait = 0x00000000; |
| SDRAM[1].EmcXm2CmdPadCtrl = 0x10000280; |
| SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[1].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[1].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[1].EmcXm2CmdPadCtrl5 = 0x00111111; |
| SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0130b118; |
| SDRAM[1].EmcXm2DqsPadCtrl3 = 0x51451400; |
| SDRAM[1].EmcXm2DqsPadCtrl4 = 0x00514514; |
| SDRAM[1].EmcXm2DqsPadCtrl5 = 0x00514514; |
| SDRAM[1].EmcXm2DqsPadCtrl6 = 0x51451400; |
| SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[1].EmcXm2DqPadCtrl3 = 0x00000000; |
| SDRAM[1].EmcXm2ClkPadCtrl = 0x77ffc081; |
| SDRAM[1].EmcXm2ClkPadCtrl2 = 0x00000303; |
| SDRAM[1].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[1].EmcXm2VttGenPadCtrl = 0x07070004; |
| SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x0000003f; |
| SDRAM[1].EmcXm2VttGenPadCtrl3 = 0x016eeeee; |
| SDRAM[1].EmcAcpdControl = 0x00000000; |
| SDRAM[1].EmcSwizzleRank0ByteCfg = 0x00003120; |
| SDRAM[1].EmcSwizzleRank0Byte0 = 0x25143067; |
| SDRAM[1].EmcSwizzleRank0Byte1 = 0x45367102; |
| SDRAM[1].EmcSwizzleRank0Byte2 = 0x47106253; |
| SDRAM[1].EmcSwizzleRank0Byte3 = 0x04362175; |
| SDRAM[1].EmcSwizzleRank1ByteCfg = 0x00003120; |
| SDRAM[1].EmcSwizzleRank1Byte0 = 0x71546032; |
| SDRAM[1].EmcSwizzleRank1Byte1 = 0x35104276; |
| SDRAM[1].EmcSwizzleRank1Byte2 = 0x27043615; |
| SDRAM[1].EmcSwizzleRank1Byte3 = 0x72306145; |
| SDRAM[1].EmcDsrVttgenDrv = 0x0000003f; |
| SDRAM[1].EmcTxdsrvttgen = 0x00000066; |
| SDRAM[1].EmcBgbiasCtl0 = 0x00000008; |
| SDRAM[1].McEmemAdrCfg = 0x00000000; |
| SDRAM[1].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[1].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[1].McEmemAdrCfgBankMask0 = 0x00001248; |
| SDRAM[1].McEmemAdrCfgBankMask1 = 0x00002490; |
| SDRAM[1].McEmemAdrCfgBankMask2 = 0x00000920; |
| SDRAM[1].McEmemAdrCfgBankSwizzle3 = 0x00000001; |
| SDRAM[1].McEmemCfg = 0x00000800; |
| SDRAM[1].McEmemArbCfg = 0x01000003; |
| SDRAM[1].McEmemArbOutstandingReq = 0x80000040; |
| SDRAM[1].McEmemArbTimingRcd = 0x00000001; |
| SDRAM[1].McEmemArbTimingRp = 0x00000001; |
| SDRAM[1].McEmemArbTimingRc = 0x00000005; |
| SDRAM[1].McEmemArbTimingRas = 0x00000002; |
| SDRAM[1].McEmemArbTimingFaw = 0x00000004; |
| SDRAM[1].McEmemArbTimingRrd = 0x00000001; |
| SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002; |
| SDRAM[1].McEmemArbTimingWap2Pre = 0x00000008; |
| SDRAM[1].McEmemArbTimingR2R = 0x00000003; |
| SDRAM[1].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[1].McEmemArbTimingR2W = 0x00000004; |
| SDRAM[1].McEmemArbTimingW2R = 0x00000006; |
| SDRAM[1].McEmemArbDaTurns = 0x06040203; |
| SDRAM[1].McEmemArbDaCovers = 0x000a0405; |
| SDRAM[1].McEmemArbMisc0 = 0x73840a06; |
| SDRAM[1].McEmemArbMisc1 = 0x70000f03; |
| SDRAM[1].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[1].McEmemArbOverride = 0x10000000; |
| SDRAM[1].McEmemArbOverride1 = 0x00000000; |
| SDRAM[1].McEmemArbRsv = 0xff00ff00; |
| SDRAM[1].McClkenOverride = 0x00000000; |
| SDRAM[1].McStatControl = 0x00000000; |
| SDRAM[1].McDisplaySnapRing = 0x00000003; |
| SDRAM[1].McVideoProtectBom = 0xfff00000; |
| SDRAM[1].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[1].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[1].McVideoProtectVprOverride = 0xe4bac743; |
| SDRAM[1].McVideoProtectVprOverride1 = 0x00000013; |
| SDRAM[1].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[1].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[1].McSecCarveoutBom = 0xfff00000; |
| SDRAM[1].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[1].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[1].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[1].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[1].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[1].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[1].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[1].SwizzleRankByteEncode = 0x0000006f; |
| SDRAM[1].BootRomPatchControl = 0x00000000; |
| SDRAM[1].BootRomPatchData = 0x00000000; |
| SDRAM[1].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[1].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[1].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[1].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000001; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x00000062; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff003c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x004e0049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080057; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff0063; |
| #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00ff0036; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff006b; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510050; |
| #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff006d; |
| # Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command: |
| # t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 4.90196 |
| # -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o Nike_0121_2GB_204Mhz.cfg |
| # -b NIKE_0121_204MHz_emc_reg.txt |
| # Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 4.90 ns (204.00 MHz) |
| # bkv file: NIKE_0121_204MHz_emc_reg.txt |
| SDRAM[2].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[2].PllMInputDivider = 0x00000001; |
| SDRAM[2].PllMFeedbackDivider = 0x00000022; |
| SDRAM[2].PllMStableTime = 0x0000012c; |
| SDRAM[2].PllMSetupControl = 0x00000000; |
| SDRAM[2].PllMSelectDiv2 = 0x00000000; |
| SDRAM[2].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[2].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[2].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[2].PllMKCP = 0x00000000; |
| SDRAM[2].PllMKVCO = 0x00000000; |
| SDRAM[2].EmcBctSpare0 = 0x00000000; |
| SDRAM[2].EmcBctSpare1 = 0x00000000; |
| SDRAM[2].EmcBctSpare2 = 0x00000000; |
| SDRAM[2].EmcBctSpare3 = 0x00000000; |
| SDRAM[2].EmcBctSpare4 = 0x00000000; |
| SDRAM[2].EmcBctSpare5 = 0x00000000; |
| SDRAM[2].EmcBctSpare6 = 0x00000000; |
| SDRAM[2].EmcBctSpare7 = 0x00000000; |
| SDRAM[2].EmcBctSpare8 = 0x00000000; |
| SDRAM[2].EmcBctSpare9 = 0x00000000; |
| SDRAM[2].EmcBctSpare10 = 0x00000000; |
| SDRAM[2].EmcBctSpare11 = 0x00000000; |
| SDRAM[2].EmcClockSource = 0x40000002; |
| SDRAM[2].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[2].EmcAutoCalConfig = 0xa1430000; |
| SDRAM[2].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[2].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[2].EmcAutoCalWait = 0x00000190; |
| SDRAM[2].EmcAdrCfg = 0x00000000; |
| SDRAM[2].EmcPinProgramWait = 0x00000001; |
| SDRAM[2].EmcPinExtraWait = 0x00000000; |
| SDRAM[2].EmcTimingControlWait = 0x00000000; |
| SDRAM[2].EmcRc = 0x00000009; |
| SDRAM[2].EmcRfc = 0x00000035; |
| SDRAM[2].EmcRfcSlr = 0x00000000; |
| SDRAM[2].EmcRas = 0x00000007; |
| SDRAM[2].EmcRp = 0x00000002; |
| SDRAM[2].EmcR2r = 0x00000000; |
| SDRAM[2].EmcW2w = 0x00000000; |
| SDRAM[2].EmcR2w = 0x00000005; |
| SDRAM[2].EmcW2r = 0x0000000a; |
| SDRAM[2].EmcR2p = 0x00000003; |
| SDRAM[2].EmcW2p = 0x0000000b; |
| SDRAM[2].EmcRdRcd = 0x00000002; |
| SDRAM[2].EmcWrRcd = 0x00000002; |
| SDRAM[2].EmcRrd = 0x00000003; |
| SDRAM[2].EmcRext = 0x00000003; |
| SDRAM[2].EmcWext = 0x00000000; |
| SDRAM[2].EmcWdv = 0x00000005; |
| SDRAM[2].EmcWdvMask = 0x00000005; |
| SDRAM[2].EmcQUse = 0x00000006; |
| SDRAM[2].EmcQuseWidth = 0x00000002; |
| SDRAM[2].EmcIbdly = 0x00000000; |
| SDRAM[2].EmcEInput = 0x00000004; |
| SDRAM[2].EmcEInputDuration = 0x00000006; |
| SDRAM[2].EmcPutermExtra = 0x00010000; |
| SDRAM[2].EmcPutermWidth = 0x00000003; |
| SDRAM[2].EmcPutermAdj = 0x00000000; |
| SDRAM[2].EmcCdbCntl1 = 0x00000000; |
| SDRAM[2].EmcCdbCntl2 = 0x00000000; |
| SDRAM[2].EmcCdbCntl3 = 0x00000000; |
| SDRAM[2].EmcQRst = 0x00000003; |
| SDRAM[2].EmcQSafe = 0x0000000d; |
| SDRAM[2].EmcRdv = 0x0000000f; |
| SDRAM[2].EmcRdvMask = 0x00000011; |
| SDRAM[2].EmcQpop = 0x0000000a; |
| SDRAM[2].EmcCtt = 0x00000000; |
| SDRAM[2].EmcCttDuration = 0x00000003; |
| SDRAM[2].EmcRefresh = 0x00000607; |
| SDRAM[2].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[2].EmcPreRefreshReqCnt = 0x00000181; |
| SDRAM[2].EmcPdEx2Wr = 0x00000002; |
| SDRAM[2].EmcPdEx2Rd = 0x00000002; |
| SDRAM[2].EmcPChg2Pden = 0x00000001; |
| SDRAM[2].EmcAct2Pden = 0x00000000; |
| SDRAM[2].EmcAr2Pden = 0x00000032; |
| SDRAM[2].EmcRw2Pden = 0x0000000f; |
| SDRAM[2].EmcTxsr = 0x00000038; |
| SDRAM[2].EmcTxsrDll = 0x00000038; |
| SDRAM[2].EmcTcke = 0x00000004; |
| SDRAM[2].EmcTckesr = 0x00000005; |
| SDRAM[2].EmcTpd = 0x00000004; |
| SDRAM[2].EmcTfaw = 0x00000007; |
| SDRAM[2].EmcTrpab = 0x00000000; |
| SDRAM[2].EmcTClkStable = 0x00000005; |
| SDRAM[2].EmcTClkStop = 0x00000005; |
| SDRAM[2].EmcTRefBw = 0x00000638; |
| SDRAM[2].EmcFbioCfg5 = 0x106aa298; |
| SDRAM[2].EmcFbioCfg6 = 0x00000000; |
| SDRAM[2].EmcFbioSpare = 0x00000000; |
| SDRAM[2].EmcCfgRsv = 0xff00ff00; |
| SDRAM[2].EmcMrs = 0x80001221; |
| SDRAM[2].EmcEmrs = 0x80100003; |
| SDRAM[2].EmcEmrs2 = 0x80200008; |
| SDRAM[2].EmcEmrs3 = 0x80300000; |
| SDRAM[2].EmcMrw1 = 0x00000000; |
| SDRAM[2].EmcMrw2 = 0x00000000; |
| SDRAM[2].EmcMrw3 = 0x00000000; |
| SDRAM[2].EmcMrw4 = 0x00000000; |
| SDRAM[2].EmcMrwExtra = 0x00000000; |
| SDRAM[2].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[2].EmcMrwResetCommand = 0x00000000; |
| SDRAM[2].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[2].EmcMrsWaitCnt = 0x000c000c; |
| SDRAM[2].EmcMrsWaitCnt2 = 0x000c000c; |
| SDRAM[2].EmcCfg = 0x73240000; |
| SDRAM[2].EmcCfg2 = 0x0000088d; |
| SDRAM[2].EmcCfgPipe = 0x0000d2b3; |
| SDRAM[2].EmcDbg = 0x01000c00; |
| SDRAM[2].EmcCmdQ = 0x10004408; |
| SDRAM[2].EmcMc2EmcQ = 0x06000404; |
| SDRAM[2].EmcDynSelfRefControl = 0x80000d22; |
| SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[2].EmcCfgDigDll = 0x002c00a0; |
| SDRAM[2].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[2].EmcDevSelect = 0x00000002; |
| SDRAM[2].EmcSelDpdCtrl = 0x00040008; |
| SDRAM[2].EmcDllXformDqs0 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs1 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs2 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs3 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs4 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs5 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs6 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs7 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs8 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs9 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs10 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs11 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs12 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs13 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs14 = 0x00064000; |
| SDRAM[2].EmcDllXformDqs15 = 0x00064000; |
| SDRAM[2].EmcDllXformQUse0 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse1 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse2 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse3 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse4 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse5 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse6 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse7 = 0x00000000; |
| SDRAM[2].EmcDllXformAddr0 = 0x00000000; |
| SDRAM[2].EmcDllXformAddr1 = 0x00000000; |
| SDRAM[2].EmcDllXformAddr2 = 0x00004000; |
| SDRAM[2].EmcDllXformAddr3 = 0x00000000; |
| SDRAM[2].EmcDllXformAddr4 = 0x00000000; |
| SDRAM[2].EmcDllXformAddr5 = 0x00004000; |
| SDRAM[2].EmcDllXformQUse8 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse9 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse10 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse11 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse12 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse13 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse14 = 0x00000000; |
| SDRAM[2].EmcDllXformQUse15 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs8 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs9 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs10 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs11 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs12 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs13 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs14 = 0x00000000; |
| SDRAM[2].EmcDliTrimTxDqs15 = 0x00000000; |
| SDRAM[2].EmcDllXformDq0 = 0x00090000; |
| SDRAM[2].EmcDllXformDq1 = 0x00090000; |
| SDRAM[2].EmcDllXformDq2 = 0x00094000; |
| SDRAM[2].EmcDllXformDq3 = 0x00094000; |
| SDRAM[2].EmcDllXformDq4 = 0x00009400; |
| SDRAM[2].EmcDllXformDq5 = 0x00009000; |
| SDRAM[2].EmcDllXformDq6 = 0x00009000; |
| SDRAM[2].EmcDllXformDq7 = 0x00009000; |
| SDRAM[2].WarmBootWait = 0x00000002; |
| SDRAM[2].EmcCttTermCtrl = 0x00000802; |
| SDRAM[2].EmcOdtWrite = 0x00000000; |
| SDRAM[2].EmcOdtRead = 0x00000000; |
| SDRAM[2].EmcZcalInterval = 0x00020000; |
| SDRAM[2].EmcZcalWaitCnt = 0x00000042; |
| SDRAM[2].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[2].EmcMrsResetDll = 0x00000000; |
| SDRAM[2].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[2].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[2].EmcZcalInitWait = 0x00000003; |
| SDRAM[2].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000000; |
| SDRAM[2].EmcZcalWarmBootWait = 0x00000002; |
| SDRAM[2].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[2].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[2].EmcMrsExtra = 0x80001221; |
| SDRAM[2].EmcWarmBootMrsExtra = 0x80100003; |
| SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[2].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[2].EmcDdr2Wait = 0x00000000; |
| SDRAM[2].EmcClkenOverride = 0x00000000; |
| SDRAM[2].McDisExtraSnapLevels = 0x00000000; |
| SDRAM[2].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[2].PmcVddpSel = 0x00000002; |
| SDRAM[2].PmcVddpSelWait = 0x00000002; |
| SDRAM[2].PmcDdrPwr = 0x00000003; |
| SDRAM[2].PmcDdrCfg = 0x00002002; |
| SDRAM[2].PmcIoDpd3Req = 0x4fff2f97; |
| SDRAM[2].PmcIoDpd3ReqWait = 0x00000000; |
| SDRAM[2].PmcRegShort = 0x00000000; |
| SDRAM[2].PmcNoIoPower = 0x00000000; |
| SDRAM[2].PmcPorDpdCtrlWait = 0x00000000; |
| SDRAM[2].EmcXm2CmdPadCtrl = 0x10000280; |
| SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[2].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[2].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[2].EmcXm2CmdPadCtrl5 = 0x00111111; |
| SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0130b118; |
| SDRAM[2].EmcXm2DqsPadCtrl3 = 0x51451400; |
| SDRAM[2].EmcXm2DqsPadCtrl4 = 0x00514514; |
| SDRAM[2].EmcXm2DqsPadCtrl5 = 0x00514514; |
| SDRAM[2].EmcXm2DqsPadCtrl6 = 0x51451400; |
| SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[2].EmcXm2DqPadCtrl3 = 0x00000000; |
| SDRAM[2].EmcXm2ClkPadCtrl = 0x77ffc081; |
| SDRAM[2].EmcXm2ClkPadCtrl2 = 0x00000303; |
| SDRAM[2].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[2].EmcXm2VttGenPadCtrl = 0x07070004; |
| SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x0000003f; |
| SDRAM[2].EmcXm2VttGenPadCtrl3 = 0x016eeeee; |
| SDRAM[2].EmcAcpdControl = 0x00000000; |
| SDRAM[2].EmcSwizzleRank0ByteCfg = 0x00003120; |
| SDRAM[2].EmcSwizzleRank0Byte0 = 0x25143067; |
| SDRAM[2].EmcSwizzleRank0Byte1 = 0x45367102; |
| SDRAM[2].EmcSwizzleRank0Byte2 = 0x47106253; |
| SDRAM[2].EmcSwizzleRank0Byte3 = 0x04362175; |
| SDRAM[2].EmcSwizzleRank1ByteCfg = 0x00003120; |
| SDRAM[2].EmcSwizzleRank1Byte0 = 0x71546032; |
| SDRAM[2].EmcSwizzleRank1Byte1 = 0x35104276; |
| SDRAM[2].EmcSwizzleRank1Byte2 = 0x27043615; |
| SDRAM[2].EmcSwizzleRank1Byte3 = 0x72306145; |
| SDRAM[2].EmcDsrVttgenDrv = 0x0000003f; |
| SDRAM[2].EmcTxdsrvttgen = 0x00000066; |
| SDRAM[2].EmcBgbiasCtl0 = 0x00000008; |
| SDRAM[2].McEmemAdrCfg = 0x00000000; |
| SDRAM[2].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[2].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[2].McEmemAdrCfgBankMask0 = 0x00001248; |
| SDRAM[2].McEmemAdrCfgBankMask1 = 0x00002490; |
| SDRAM[2].McEmemAdrCfgBankMask2 = 0x00000920; |
| SDRAM[2].McEmemAdrCfgBankSwizzle3 = 0x00000001; |
| SDRAM[2].McEmemCfg = 0x00000800; |
| SDRAM[2].McEmemArbCfg = 0x01000003; |
| SDRAM[2].McEmemArbOutstandingReq = 0x80000040; |
| SDRAM[2].McEmemArbTimingRcd = 0x00000001; |
| SDRAM[2].McEmemArbTimingRp = 0x00000001; |
| SDRAM[2].McEmemArbTimingRc = 0x00000005; |
| SDRAM[2].McEmemArbTimingRas = 0x00000002; |
| SDRAM[2].McEmemArbTimingFaw = 0x00000004; |
| SDRAM[2].McEmemArbTimingRrd = 0x00000001; |
| SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002; |
| SDRAM[2].McEmemArbTimingWap2Pre = 0x00000008; |
| SDRAM[2].McEmemArbTimingR2R = 0x00000003; |
| SDRAM[2].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[2].McEmemArbTimingR2W = 0x00000004; |
| SDRAM[2].McEmemArbTimingW2R = 0x00000006; |
| SDRAM[2].McEmemArbDaTurns = 0x06040203; |
| SDRAM[2].McEmemArbDaCovers = 0x000a0405; |
| SDRAM[2].McEmemArbMisc0 = 0x73840a06; |
| SDRAM[2].McEmemArbMisc1 = 0x70000f03; |
| SDRAM[2].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[2].McEmemArbOverride = 0x10000000; |
| SDRAM[2].McEmemArbOverride1 = 0x00000000; |
| SDRAM[2].McEmemArbRsv = 0xff00ff00; |
| SDRAM[2].McClkenOverride = 0x00000000; |
| SDRAM[2].McStatControl = 0x00000000; |
| SDRAM[2].McDisplaySnapRing = 0x00000003; |
| SDRAM[2].McVideoProtectBom = 0xfff00000; |
| SDRAM[2].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[2].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[2].McVideoProtectVprOverride = 0xe4bac743; |
| SDRAM[2].McVideoProtectVprOverride1 = 0x00000013; |
| SDRAM[2].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[2].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[2].McSecCarveoutBom = 0xfff00000; |
| SDRAM[2].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[2].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[2].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[2].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[2].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[2].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[2].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[2].SwizzleRankByteEncode = 0x0000006f; |
| SDRAM[2].BootRomPatchControl = 0x00000000; |
| SDRAM[2].BootRomPatchData = 0x00000000; |
| SDRAM[2].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[2].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[2].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[2].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000001; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x00000062; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff003c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x004e0049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080057; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff0063; |
| #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00ff0036; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff006b; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510050; |
| #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff006d; |
| # Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command: |
| # t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 4.90196 |
| # -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o Nike_0121_2GB_204Mhz.cfg |
| # -b NIKE_0121_204MHz_emc_reg.txt |
| # Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 4.90 ns (204.00 MHz) |
| # bkv file: NIKE_0121_204MHz_emc_reg.txt |
| SDRAM[3].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[3].PllMInputDivider = 0x00000001; |
| SDRAM[3].PllMFeedbackDivider = 0x00000022; |
| SDRAM[3].PllMStableTime = 0x0000012c; |
| SDRAM[3].PllMSetupControl = 0x00000000; |
| SDRAM[3].PllMSelectDiv2 = 0x00000000; |
| SDRAM[3].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[3].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[3].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[3].PllMKCP = 0x00000000; |
| SDRAM[3].PllMKVCO = 0x00000000; |
| SDRAM[3].EmcBctSpare0 = 0x00000000; |
| SDRAM[3].EmcBctSpare1 = 0x00000000; |
| SDRAM[3].EmcBctSpare2 = 0x00000000; |
| SDRAM[3].EmcBctSpare3 = 0x00000000; |
| SDRAM[3].EmcBctSpare4 = 0x00000000; |
| SDRAM[3].EmcBctSpare5 = 0x00000000; |
| SDRAM[3].EmcBctSpare6 = 0x00000000; |
| SDRAM[3].EmcBctSpare7 = 0x00000000; |
| SDRAM[3].EmcBctSpare8 = 0x00000000; |
| SDRAM[3].EmcBctSpare9 = 0x00000000; |
| SDRAM[3].EmcBctSpare10 = 0x00000000; |
| SDRAM[3].EmcBctSpare11 = 0x00000000; |
| SDRAM[3].EmcClockSource = 0x40000002; |
| SDRAM[3].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[3].EmcAutoCalConfig = 0xa1430000; |
| SDRAM[3].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[3].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[3].EmcAutoCalWait = 0x00000190; |
| SDRAM[3].EmcAdrCfg = 0x00000000; |
| SDRAM[3].EmcPinProgramWait = 0x00000001; |
| SDRAM[3].EmcPinExtraWait = 0x00000000; |
| SDRAM[3].EmcTimingControlWait = 0x00000000; |
| SDRAM[3].EmcRc = 0x00000009; |
| SDRAM[3].EmcRfc = 0x00000035; |
| SDRAM[3].EmcRfcSlr = 0x00000000; |
| SDRAM[3].EmcRas = 0x00000007; |
| SDRAM[3].EmcRp = 0x00000002; |
| SDRAM[3].EmcR2r = 0x00000000; |
| SDRAM[3].EmcW2w = 0x00000000; |
| SDRAM[3].EmcR2w = 0x00000005; |
| SDRAM[3].EmcW2r = 0x0000000a; |
| SDRAM[3].EmcR2p = 0x00000003; |
| SDRAM[3].EmcW2p = 0x0000000b; |
| SDRAM[3].EmcRdRcd = 0x00000002; |
| SDRAM[3].EmcWrRcd = 0x00000002; |
| SDRAM[3].EmcRrd = 0x00000003; |
| SDRAM[3].EmcRext = 0x00000003; |
| SDRAM[3].EmcWext = 0x00000000; |
| SDRAM[3].EmcWdv = 0x00000005; |
| SDRAM[3].EmcWdvMask = 0x00000005; |
| SDRAM[3].EmcQUse = 0x00000006; |
| SDRAM[3].EmcQuseWidth = 0x00000002; |
| SDRAM[3].EmcIbdly = 0x00000000; |
| SDRAM[3].EmcEInput = 0x00000004; |
| SDRAM[3].EmcEInputDuration = 0x00000006; |
| SDRAM[3].EmcPutermExtra = 0x00010000; |
| SDRAM[3].EmcPutermWidth = 0x00000003; |
| SDRAM[3].EmcPutermAdj = 0x00000000; |
| SDRAM[3].EmcCdbCntl1 = 0x00000000; |
| SDRAM[3].EmcCdbCntl2 = 0x00000000; |
| SDRAM[3].EmcCdbCntl3 = 0x00000000; |
| SDRAM[3].EmcQRst = 0x00000003; |
| SDRAM[3].EmcQSafe = 0x0000000d; |
| SDRAM[3].EmcRdv = 0x0000000f; |
| SDRAM[3].EmcRdvMask = 0x00000011; |
| SDRAM[3].EmcQpop = 0x0000000a; |
| SDRAM[3].EmcCtt = 0x00000000; |
| SDRAM[3].EmcCttDuration = 0x00000003; |
| SDRAM[3].EmcRefresh = 0x00000607; |
| SDRAM[3].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[3].EmcPreRefreshReqCnt = 0x00000181; |
| SDRAM[3].EmcPdEx2Wr = 0x00000002; |
| SDRAM[3].EmcPdEx2Rd = 0x00000002; |
| SDRAM[3].EmcPChg2Pden = 0x00000001; |
| SDRAM[3].EmcAct2Pden = 0x00000000; |
| SDRAM[3].EmcAr2Pden = 0x00000032; |
| SDRAM[3].EmcRw2Pden = 0x0000000f; |
| SDRAM[3].EmcTxsr = 0x00000038; |
| SDRAM[3].EmcTxsrDll = 0x00000038; |
| SDRAM[3].EmcTcke = 0x00000004; |
| SDRAM[3].EmcTckesr = 0x00000005; |
| SDRAM[3].EmcTpd = 0x00000004; |
| SDRAM[3].EmcTfaw = 0x00000007; |
| SDRAM[3].EmcTrpab = 0x00000000; |
| SDRAM[3].EmcTClkStable = 0x00000005; |
| SDRAM[3].EmcTClkStop = 0x00000005; |
| SDRAM[3].EmcTRefBw = 0x00000638; |
| SDRAM[3].EmcFbioCfg5 = 0x106aa298; |
| SDRAM[3].EmcFbioCfg6 = 0x00000000; |
| SDRAM[3].EmcFbioSpare = 0x00000000; |
| SDRAM[3].EmcCfgRsv = 0xff00ff00; |
| SDRAM[3].EmcMrs = 0x80001221; |
| SDRAM[3].EmcEmrs = 0x80100003; |
| SDRAM[3].EmcEmrs2 = 0x80200008; |
| SDRAM[3].EmcEmrs3 = 0x80300000; |
| SDRAM[3].EmcMrw1 = 0x00000000; |
| SDRAM[3].EmcMrw2 = 0x00000000; |
| SDRAM[3].EmcMrw3 = 0x00000000; |
| SDRAM[3].EmcMrw4 = 0x00000000; |
| SDRAM[3].EmcMrwExtra = 0x00000000; |
| SDRAM[3].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[3].EmcMrwResetCommand = 0x00000000; |
| SDRAM[3].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[3].EmcMrsWaitCnt = 0x000c000c; |
| SDRAM[3].EmcMrsWaitCnt2 = 0x000c000c; |
| SDRAM[3].EmcCfg = 0x73240000; |
| SDRAM[3].EmcCfg2 = 0x0000088d; |
| SDRAM[3].EmcCfgPipe = 0x0000d2b3; |
| SDRAM[3].EmcDbg = 0x01000c00; |
| SDRAM[3].EmcCmdQ = 0x10004408; |
| SDRAM[3].EmcMc2EmcQ = 0x06000404; |
| SDRAM[3].EmcDynSelfRefControl = 0x80000d22; |
| SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[3].EmcCfgDigDll = 0x002c00a0; |
| SDRAM[3].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[3].EmcDevSelect = 0x00000002; |
| SDRAM[3].EmcSelDpdCtrl = 0x00040008; |
| SDRAM[3].EmcDllXformDqs0 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs1 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs2 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs3 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs4 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs5 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs6 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs7 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs8 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs9 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs10 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs11 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs12 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs13 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs14 = 0x00064000; |
| SDRAM[3].EmcDllXformDqs15 = 0x00064000; |
| SDRAM[3].EmcDllXformQUse0 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse1 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse2 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse3 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse4 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse5 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse6 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse7 = 0x00000000; |
| SDRAM[3].EmcDllXformAddr0 = 0x00000000; |
| SDRAM[3].EmcDllXformAddr1 = 0x00000000; |
| SDRAM[3].EmcDllXformAddr2 = 0x00004000; |
| SDRAM[3].EmcDllXformAddr3 = 0x00000000; |
| SDRAM[3].EmcDllXformAddr4 = 0x00000000; |
| SDRAM[3].EmcDllXformAddr5 = 0x00004000; |
| SDRAM[3].EmcDllXformQUse8 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse9 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse10 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse11 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse12 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse13 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse14 = 0x00000000; |
| SDRAM[3].EmcDllXformQUse15 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs8 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs9 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs10 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs11 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs12 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs13 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs14 = 0x00000000; |
| SDRAM[3].EmcDliTrimTxDqs15 = 0x00000000; |
| SDRAM[3].EmcDllXformDq0 = 0x00090000; |
| SDRAM[3].EmcDllXformDq1 = 0x00090000; |
| SDRAM[3].EmcDllXformDq2 = 0x00094000; |
| SDRAM[3].EmcDllXformDq3 = 0x00094000; |
| SDRAM[3].EmcDllXformDq4 = 0x00009400; |
| SDRAM[3].EmcDllXformDq5 = 0x00009000; |
| SDRAM[3].EmcDllXformDq6 = 0x00009000; |
| SDRAM[3].EmcDllXformDq7 = 0x00009000; |
| SDRAM[3].WarmBootWait = 0x00000002; |
| SDRAM[3].EmcCttTermCtrl = 0x00000802; |
| SDRAM[3].EmcOdtWrite = 0x00000000; |
| SDRAM[3].EmcOdtRead = 0x00000000; |
| SDRAM[3].EmcZcalInterval = 0x00020000; |
| SDRAM[3].EmcZcalWaitCnt = 0x00000042; |
| SDRAM[3].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[3].EmcMrsResetDll = 0x00000000; |
| SDRAM[3].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[3].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[3].EmcZcalInitWait = 0x00000003; |
| SDRAM[3].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000000; |
| SDRAM[3].EmcZcalWarmBootWait = 0x00000002; |
| SDRAM[3].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[3].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[3].EmcMrsExtra = 0x80001221; |
| SDRAM[3].EmcWarmBootMrsExtra = 0x80100003; |
| SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[3].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[3].EmcDdr2Wait = 0x00000000; |
| SDRAM[3].EmcClkenOverride = 0x00000000; |
| SDRAM[3].McDisExtraSnapLevels = 0x00000000; |
| SDRAM[3].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[3].PmcVddpSel = 0x00000002; |
| SDRAM[3].PmcVddpSelWait = 0x00000002; |
| SDRAM[3].PmcDdrPwr = 0x00000003; |
| SDRAM[3].PmcDdrCfg = 0x00002002; |
| SDRAM[3].PmcIoDpd3Req = 0x4fff2f97; |
| SDRAM[3].PmcIoDpd3ReqWait = 0x00000000; |
| SDRAM[3].PmcRegShort = 0x00000000; |
| SDRAM[3].PmcNoIoPower = 0x00000000; |
| SDRAM[3].PmcPorDpdCtrlWait = 0x00000000; |
| SDRAM[3].EmcXm2CmdPadCtrl = 0x10000280; |
| SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[3].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[3].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[3].EmcXm2CmdPadCtrl5 = 0x00111111; |
| SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0130b118; |
| SDRAM[3].EmcXm2DqsPadCtrl3 = 0x51451400; |
| SDRAM[3].EmcXm2DqsPadCtrl4 = 0x00514514; |
| SDRAM[3].EmcXm2DqsPadCtrl5 = 0x00514514; |
| SDRAM[3].EmcXm2DqsPadCtrl6 = 0x51451400; |
| SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[3].EmcXm2DqPadCtrl3 = 0x00000000; |
| SDRAM[3].EmcXm2ClkPadCtrl = 0x77ffc081; |
| SDRAM[3].EmcXm2ClkPadCtrl2 = 0x00000303; |
| SDRAM[3].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[3].EmcXm2VttGenPadCtrl = 0x07070004; |
| SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x0000003f; |
| SDRAM[3].EmcXm2VttGenPadCtrl3 = 0x016eeeee; |
| SDRAM[3].EmcAcpdControl = 0x00000000; |
| SDRAM[3].EmcSwizzleRank0ByteCfg = 0x00003120; |
| SDRAM[3].EmcSwizzleRank0Byte0 = 0x25143067; |
| SDRAM[3].EmcSwizzleRank0Byte1 = 0x45367102; |
| SDRAM[3].EmcSwizzleRank0Byte2 = 0x47106253; |
| SDRAM[3].EmcSwizzleRank0Byte3 = 0x04362175; |
| SDRAM[3].EmcSwizzleRank1ByteCfg = 0x00003120; |
| SDRAM[3].EmcSwizzleRank1Byte0 = 0x71546032; |
| SDRAM[3].EmcSwizzleRank1Byte1 = 0x35104276; |
| SDRAM[3].EmcSwizzleRank1Byte2 = 0x27043615; |
| SDRAM[3].EmcSwizzleRank1Byte3 = 0x72306145; |
| SDRAM[3].EmcDsrVttgenDrv = 0x0000003f; |
| SDRAM[3].EmcTxdsrvttgen = 0x00000066; |
| SDRAM[3].EmcBgbiasCtl0 = 0x00000008; |
| SDRAM[3].McEmemAdrCfg = 0x00000000; |
| SDRAM[3].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[3].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[3].McEmemAdrCfgBankMask0 = 0x00001248; |
| SDRAM[3].McEmemAdrCfgBankMask1 = 0x00002490; |
| SDRAM[3].McEmemAdrCfgBankMask2 = 0x00000920; |
| SDRAM[3].McEmemAdrCfgBankSwizzle3 = 0x00000001; |
| SDRAM[3].McEmemCfg = 0x00000800; |
| SDRAM[3].McEmemArbCfg = 0x01000003; |
| SDRAM[3].McEmemArbOutstandingReq = 0x80000040; |
| SDRAM[3].McEmemArbTimingRcd = 0x00000001; |
| SDRAM[3].McEmemArbTimingRp = 0x00000001; |
| SDRAM[3].McEmemArbTimingRc = 0x00000005; |
| SDRAM[3].McEmemArbTimingRas = 0x00000002; |
| SDRAM[3].McEmemArbTimingFaw = 0x00000004; |
| SDRAM[3].McEmemArbTimingRrd = 0x00000001; |
| SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002; |
| SDRAM[3].McEmemArbTimingWap2Pre = 0x00000008; |
| SDRAM[3].McEmemArbTimingR2R = 0x00000003; |
| SDRAM[3].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[3].McEmemArbTimingR2W = 0x00000004; |
| SDRAM[3].McEmemArbTimingW2R = 0x00000006; |
| SDRAM[3].McEmemArbDaTurns = 0x06040203; |
| SDRAM[3].McEmemArbDaCovers = 0x000a0405; |
| SDRAM[3].McEmemArbMisc0 = 0x73840a06; |
| SDRAM[3].McEmemArbMisc1 = 0x70000f03; |
| SDRAM[3].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[3].McEmemArbOverride = 0x10000000; |
| SDRAM[3].McEmemArbOverride1 = 0x00000000; |
| SDRAM[3].McEmemArbRsv = 0xff00ff00; |
| SDRAM[3].McClkenOverride = 0x00000000; |
| SDRAM[3].McStatControl = 0x00000000; |
| SDRAM[3].McDisplaySnapRing = 0x00000003; |
| SDRAM[3].McVideoProtectBom = 0xfff00000; |
| SDRAM[3].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[3].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[3].McVideoProtectVprOverride = 0xe4bac743; |
| SDRAM[3].McVideoProtectVprOverride1 = 0x00000013; |
| SDRAM[3].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[3].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[3].McSecCarveoutBom = 0xfff00000; |
| SDRAM[3].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[3].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[3].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[3].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[3].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[3].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[3].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[3].SwizzleRankByteEncode = 0x0000006f; |
| SDRAM[3].BootRomPatchControl = 0x00000000; |
| SDRAM[3].BootRomPatchData = 0x00000000; |
| SDRAM[3].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[3].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[3].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[3].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000001; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x00000062; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff003c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00af; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff004f; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x004e0049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080057; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff0063; |
| #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00ff0036; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff006b; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000050; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510050; |
| #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff006d; |
