| diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt |
| index ce59a505f5a4c21ea288688b4d967e061274bc83..c1ccd8582eb2227155b34751b7002a51199c061f 100644 |
| --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt |
| +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt |
| @@ -58,6 +58,7 @@ Required properties: |
| - compatible : must be one of the following string: |
| "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. |
| "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. |
| + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. |
| "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses |
| generation one m4u HW. |
| "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. |
| @@ -78,6 +79,7 @@ Required properties: |
| Specifies the mtk_m4u_id as defined in |
| dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 |
| dt-binding/memory/mt2712-larb-port.h for mt2712, |
| + dt-binding/memory/mt6779-larb-port.h for mt6779, |
| dt-binding/memory/mt8173-larb-port.h for mt8173, and |
| dt-binding/memory/mt8183-larb-port.h for mt8183. |
| |
| diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt |
| index 0df4382afc206d79bc64a32aa61476d6d0bbd442..fb24fe24641380762011be10e0ff7b56cb34620f 100644 |
| --- a/Documentation/devicetree/bindings/mfd/mt6397.txt |
| +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt |
| @@ -21,6 +21,7 @@ Required properties: |
| compatible: |
| "mediatek,mt6323" for PMIC MT6323 |
| "mediatek,mt6358" for PMIC MT6358 |
| + "mediatek,mt6359" for PMIC MT6359 |
| "mediatek,mt6397" for PMIC MT6397 |
| |
| Optional subnodes: |
| @@ -29,6 +30,7 @@ Optional subnodes: |
| Required properties: Should be one of follows |
| - compatible: "mediatek,mt6323-rtc" |
| - compatible: "mediatek,mt6358-rtc" |
| + - compatible: "mediatek,mt6359-rtc" |
| - compatible: "mediatek,mt6397-rtc" |
| For details, see ../rtc/rtc-mt6397.txt |
| - regulators |
| @@ -37,6 +39,8 @@ Optional subnodes: |
| see ../regulator/mt6323-regulator.txt |
| - compatible: "mediatek,mt6358-regulator" |
| see ../regulator/mt6358-regulator.txt |
| + - compatible: "mediatek,mt6359-regulator" |
| + see ../regulator/mt6359-regulator.txt |
| - compatible: "mediatek,mt6397-regulator" |
| see ../regulator/mt6397-regulator.txt |
| - codec |
| diff --git a/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..c86aaa986291740ef71b38bee03b926a121b5535 |
| --- /dev/null |
| +++ b/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt |
| @@ -0,0 +1,58 @@ |
| +Mediatek MT6359 Regulator |
| + |
| +Required properties: |
| +- compatible: "mediatek,mt6359-regulator" |
| +- mt6359regulator: List of regulators provided by this controller. It is named |
| + according to its regulator type, buck_<name> and ldo_<name>. |
| + The definition for each of these nodes is defined using the standard binding |
| + for regulators at Documentation/devicetree/bindings/regulator/regulator.txt. |
| + |
| +The valid names for regulators are: |
| +BUCK: |
| + buck_vs1, buck_vgpu11, buck_vmodem, buck_vpu, buck_vcore, buck_vs2, |
| + buck_vpa, buck_vproc2, buck_vproc1, buck_vcore_sshub |
| +LDO: |
| + ldo_vaud18, ldo_vsim1, ldo_vibr, ldo_vrf12, ldo_vusb, ldo_vsram_proc2, |
| + ldo_vio18, ldo_vcamio, ldo_vcn18, ldo_vfe28, ldo_vcn13, ldo_vcn33_1_bt, |
| + ldo_vcn13_1_wifi, ldo_vaux18, ldo_vsram_others, ldo_vefuse, ldo_vxo22, |
| + ldo_vrfck, ldo_vbif28, ldo_vio28, ldo_vemc, ldo_vcn33_2_bt, ldo_vcn33_2_wifi, |
| + ldo_va12, ldo_va09, ldo_vrf18, ldo_vsram_md, ldo_vufs, ldo_vm18, ldo_vbbck, |
| + ldo_vsram_proc1, ldo_vsim2, ldo_vsram_others_sshub |
| + |
| +Example: |
| + pmic { |
| + compatible = "mediatek,mt6359"; |
| + |
| + mt6359regulator: mt6359regulator { |
| + compatible = "mediatek,mt6359-regulator"; |
| + |
| + mt6359_vs1_buck_reg: buck_vs1 { |
| + regulator-name = "vs1"; |
| + regulator-min-microvolt = <800000>; |
| + regulator-max-microvolt = <2200000>; |
| + regulator-enable-ramp-delay = <0>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vgpu11_buck_reg: buck_vgpu11 { |
| + regulator-name = "vgpu11"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-always-on; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vaud18_ldo_reg: ldo_vaud18 { |
| + regulator-name = "vaud18"; |
| + regulator-min-microvolt = <1800000>; |
| + regulator-max-microvolt = <1800000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vsim1_ldo_reg: ldo_vsim1 { |
| + regulator-name = "vsim1"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <3100000>; |
| + regulator-enable-ramp-delay = <480>; |
| + }; |
| + }; |
| + }; |
| + |
| diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |
| index ecac2bbeae4592dafa5cad6de97bc0d8092d27c1..8051c17e640ef49f5f1b7880e2aaa771b45200b7 100644 |
| --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |
| +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |
| @@ -22,6 +22,7 @@ Required properties in pwrap device node. |
| "mediatek,mt6765-pwrap" for MT6765 SoCs |
| "mediatek,mt6779-pwrap" for MT6779 SoCs |
| "mediatek,mt6797-pwrap" for MT6797 SoCs |
| + "mediatek,mt6873-pwrap" for MT6873/8192 SoCs |
| "mediatek,mt7622-pwrap" for MT7622 SoCs |
| "mediatek,mt8135-pwrap" for MT8135 SoCs |
| "mediatek,mt8173-pwrap" for MT8173 SoCs |
| diff --git a/README b/README |
| index 669ac7c32292798644b21dbb5a0dc657125f444d..dc0f0ea4da037c7ea336d73d30e6dbfae24f796f 100644 |
| --- a/README |
| +++ b/README |
| @@ -16,3 +16,5 @@ several of them using the Restructured Text markup notation. |
| Please read the Documentation/process/changes.rst file, as it contains the |
| requirements for building and running the kernel, and information about |
| the problems which may result by upgrading your kernel. |
| + |
| + |
| diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile |
| index b45a45a565a1791f9508d6c936008c193507fc4d..cbcb4a36f316dcc04ec537102675a775a6a68071 100644 |
| --- a/arch/arm64/boot/dts/mediatek/Makefile |
| +++ b/arch/arm64/boot/dts/mediatek/Makefile |
| @@ -11,3 +11,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb |
| dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb |
| dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb |
| dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb |
| +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada.dtb |
| +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb |
| diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..943e3904344b0566c2c583c434a7c27cf4d22dcf |
| --- /dev/null |
| +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi |
| @@ -0,0 +1,310 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +/* |
| + * Copyright (c) 2019 MediaTek Inc. |
| + */ |
| + |
| +&pwrap { |
| + pmic: pmic { |
| + compatible = "mediatek,mt6359"; |
| + interrupt-controller; |
| + #interrupt-cells = <2>; |
| + |
| + mt6359regulator: mt6359regulator { |
| + compatible = "mediatek,mt6359-regulator"; |
| + mt6359_vs1_buck_reg: buck_vs1 { |
| + regulator-name = "vs1"; |
| + regulator-min-microvolt = <800000>; |
| + regulator-max-microvolt = <2200000>; |
| + regulator-enable-ramp-delay = <0>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vgpu11_buck_reg: buck_vgpu11 { |
| + regulator-name = "vgpu11"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <5000>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vmodem_buck_reg: buck_vmodem { |
| + regulator-name = "vmodem"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1100000>; |
| + regulator-ramp-delay = <10760>; |
| + regulator-enable-ramp-delay = <200>; |
| + }; |
| + mt6359_vpu_buck_reg: buck_vpu { |
| + regulator-name = "vpu"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <5000>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vcore_buck_reg: buck_vcore { |
| + regulator-name = "vcore"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <5000>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vs2_buck_reg: buck_vs2 { |
| + regulator-name = "vs2"; |
| + regulator-min-microvolt = <800000>; |
| + regulator-max-microvolt = <1600000>; |
| + regulator-enable-ramp-delay = <0>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vpa_buck_reg: buck_vpa { |
| + regulator-name = "vpa"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <3650000>; |
| + regulator-enable-ramp-delay = <300>; |
| + }; |
| + mt6359_vproc2_buck_reg: buck_vproc2 { |
| + regulator-name = "vproc2"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <7500>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vproc1_buck_reg: buck_vproc1 { |
| + regulator-name = "vproc1"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <7500>; |
| + regulator-enable-ramp-delay = <200>; |
| + regulator-allowed-modes = <0 1 2>; |
| + }; |
| + mt6359_vcore_sshub_buck_reg: buck_vcore_sshub { |
| + regulator-name = "vcore_sshub"; |
| + regulator-min-microvolt = <400000>; |
| + regulator-max-microvolt = <1193750>; |
| + }; |
| + mt6359_vaud18_ldo_reg: ldo_vaud18 { |
| + regulator-name = "vaud18"; |
| + regulator-min-microvolt = <1800000>; |
| + regulator-max-microvolt = <1800000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vsim1_ldo_reg: ldo_vsim1 { |
| + regulator-name = "vsim1"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <3100000>; |
| + regulator-enable-ramp-delay = <480>; |
| + }; |
| + mt6359_vibr_ldo_reg: ldo_vibr { |
| + regulator-name = "vibr"; |
| + regulator-min-microvolt = <1200000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vrf12_ldo_reg: ldo_vrf12 { |
| + regulator-name = "vrf12"; |
| + regulator-min-microvolt = <1100000>; |
| + regulator-max-microvolt = <1300000>; |
| + regulator-enable-ramp-delay = <120>; |
| + }; |
| + mt6359_vusb_ldo_reg: ldo_vusb { |
| + regulator-name = "vusb"; |
| + regulator-min-microvolt = <3000000>; |
| + regulator-max-microvolt = <3000000>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 { |
| + regulator-name = "vsram_proc2"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <7500>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vio18_ldo_reg: ldo_vio18 { |
| + regulator-name = "vio18"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <1900000>; |
| + regulator-enable-ramp-delay = <960>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vcamio_ldo_reg: ldo_vcamio { |
| + regulator-name = "vcamio"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <1900000>; |
| + regulator-enable-ramp-delay = <1920>; |
| + }; |
| + mt6359_vcn18_ldo_reg: ldo_vcn18 { |
| + regulator-name = "vcn18"; |
| + regulator-min-microvolt = <1800000>; |
| + regulator-max-microvolt = <1800000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vfe28_ldo_reg: ldo_vfe28 { |
| + regulator-name = "vfe28"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <2800000>; |
| + regulator-enable-ramp-delay = <120>; |
| + }; |
| + mt6359_vcn13_ldo_reg: ldo_vcn13 { |
| + regulator-name = "vcn13"; |
| + regulator-min-microvolt = <900000>; |
| + regulator-max-microvolt = <1300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { |
| + regulator-name = "vcn33_1_bt"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <3500000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { |
| + regulator-name = "vcn33_1_wifi"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <3500000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vaux18_ldo_reg: ldo_vaux18 { |
| + regulator-name = "vaux18"; |
| + regulator-min-microvolt = <1800000>; |
| + regulator-max-microvolt = <1800000>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vsram_others_ldo_reg: ldo_vsram_others { |
| + regulator-name = "vsram_others"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <5000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vefuse_ldo_reg: ldo_vefuse { |
| + regulator-name = "vefuse"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <2000000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vxo22_ldo_reg: ldo_vxo22 { |
| + regulator-name = "vxo22"; |
| + regulator-min-microvolt = <1800000>; |
| + regulator-max-microvolt = <2200000>; |
| + regulator-enable-ramp-delay = <120>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vrfck_ldo_reg: ldo_vrfck { |
| + regulator-name = "vrfck"; |
| + regulator-min-microvolt = <1500000>; |
| + regulator-max-microvolt = <1700000>; |
| + regulator-enable-ramp-delay = <480>; |
| + }; |
| + mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { |
| + regulator-name = "vrfck"; |
| + regulator-min-microvolt = <1240000>; |
| + regulator-max-microvolt = <1600000>; |
| + regulator-enable-ramp-delay = <480>; |
| + }; |
| + mt6359_vbif28_ldo_reg: ldo_vbif28 { |
| + regulator-name = "vbif28"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <2800000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vio28_ldo_reg: ldo_vio28 { |
| + regulator-name = "vio28"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vemc_ldo_reg: ldo_vemc { |
| + regulator-name = "vemc"; |
| + regulator-min-microvolt = <2900000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vemc_1_ldo_reg: ldo_vemc_1 { |
| + regulator-name = "vemc"; |
| + regulator-min-microvolt = <2500000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { |
| + regulator-name = "vcn33_2_bt"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <3500000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { |
| + regulator-name = "vcn33_2_wifi"; |
| + regulator-min-microvolt = <2800000>; |
| + regulator-max-microvolt = <3500000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_va12_ldo_reg: ldo_va12 { |
| + regulator-name = "va12"; |
| + regulator-min-microvolt = <1200000>; |
| + regulator-max-microvolt = <1300000>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_va09_ldo_reg: ldo_va09 { |
| + regulator-name = "va09"; |
| + regulator-min-microvolt = <800000>; |
| + regulator-max-microvolt = <1200000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vrf18_ldo_reg: ldo_vrf18 { |
| + regulator-name = "vrf18"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <1810000>; |
| + regulator-enable-ramp-delay = <120>; |
| + }; |
| + mt6359_vsram_md_ldo_reg: ldo_vsram_md { |
| + regulator-name = "vsram_md"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <1100000>; |
| + regulator-ramp-delay = <10760>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vufs_ldo_reg: ldo_vufs { |
| + regulator-name = "vufs"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <1900000>; |
| + regulator-enable-ramp-delay = <1920>; |
| + }; |
| + mt6359_vm18_ldo_reg: ldo_vm18 { |
| + regulator-name = "vm18"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <1900000>; |
| + regulator-enable-ramp-delay = <1920>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vbbck_ldo_reg: ldo_vbbck { |
| + regulator-name = "vbbck"; |
| + regulator-min-microvolt = <1100000>; |
| + regulator-max-microvolt = <1200000>; |
| + regulator-enable-ramp-delay = <240>; |
| + }; |
| + mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 { |
| + regulator-name = "vsram_proc1"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-ramp-delay = <7500>; |
| + regulator-enable-ramp-delay = <240>; |
| + regulator-always-on; |
| + }; |
| + mt6359_vsim2_ldo_reg: ldo_vsim2 { |
| + regulator-name = "vsim2"; |
| + regulator-min-microvolt = <1700000>; |
| + regulator-max-microvolt = <3100000>; |
| + regulator-enable-ramp-delay = <480>; |
| + }; |
| + mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { |
| + regulator-name = "vsram_others_sshub"; |
| + regulator-min-microvolt = <500000>; |
| + regulator-max-microvolt = <1193750>; |
| + }; |
| + }; |
| + }; |
| +}; |
| diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dts |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..0e071b43d8886846bb8ed34492680d4acec40121 |
| --- /dev/null |
| +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dts |
| @@ -0,0 +1,964 @@ |
| +// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| +/* |
| + * Copyright (C) 2020 MediaTek Inc. |
| + * Author: Seiya Wang <seiya.wang@mediatek.com> |
| + */ |
| +/dts-v1/; |
| +#include <dt-bindings/gpio/gpio.h> |
| +#include "mt8192.dtsi" |
| +#include "mt6359.dtsi" |
| + |
| +/ { |
| + model = "MediaTek Asurada rev1 board"; |
| + compatible = "google,asurada-rev1", "google,asurada", "mediatek,mt6873"; |
| + |
| + aliases { |
| + serial0 = &uart0; |
| + }; |
| + |
| + chosen { |
| + stdout-path = "serial0:921600n8"; |
| + }; |
| + |
| + backlight_lcd0: backlight_lcd0 { |
| + compatible = "pwm-backlight"; |
| + pwms = <&pwm0 0 26000>; |
| + brightness-levels = < |
| + 0 64 128 192 256 320 384 448 |
| + 512 576 640 704 768 832 896 960 |
| + 1023>; |
| + default-brightness-level = <9>; |
| + status = "okay"; |
| + }; |
| + |
| + memory@40000000 { |
| + device_type = "memory"; |
| + reg = <0 0x40000000 0 0x80000000>; |
| + }; |
| + |
| + mt6360_ldo3_reg: regulator@0 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "mmc1_io"; |
| + /* TODO: This should be adjustable. */ |
| + regulator-min-microvolt = <3300000>; |
| + regulator-max-microvolt = <3300000>; |
| + enable-active-high; |
| + regulator-always-on; |
| + }; |
| + |
| + mt6360_ldo5_reg: regulator@0 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "mmc1_power"; |
| + regulator-min-microvolt = <3300000>; |
| + regulator-max-microvolt = <3300000>; |
| + enable-active-high; |
| + regulator-always-on; |
| + }; |
| + |
| + panel: panel { |
| + compatible = "auo,b116xw03"; |
| + power-supply = <&pp3300_panel>; |
| + ddc-i2c-bus = <&i2c3>; |
| + backlight = <&backlight_lcd0>; |
| + |
| + port { |
| + panel_in: endpoint { |
| + remote-endpoint = <&anx7625_out>; |
| + }; |
| + }; |
| + }; |
| + |
| + pp1000_mipibrdg: pp1000-mipibrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp1000_mipibrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp1000_mipibrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + pp1000_dpbrdg: pp1000-dpbrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp1000_dpbrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp1000_dpbrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + pp1800_mipibrdg: pp1800-mipibrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp1800_mipibrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp1800_mipibrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 128 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + pp1800_dpbrdg: pp1800-dpbrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp1800_dpbrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp1800_dpbrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 126 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + /* Probably useless, as we use pp3300_mipibrdg for panel power */ |
| + pp3300_panel: pp3300-panel { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp3300_panel"; |
| + regulator-min-microvolt = <3300000>; |
| + regulator-max-microvolt = <3300000>; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp3300_panel_pins>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 136 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + pp3300_mipibrdg: pp3300-mipibrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp3300_mipibrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp3300_mipibrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 127 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + pp3300_dpbrdg: pp3300-dpbrdg { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "pp3300_dpbrdg"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pp3300_dpbrdg_en>; |
| + |
| + enable-active-high; |
| + regulator-always-on; |
| + |
| + gpio = <&pio 26 GPIO_ACTIVE_HIGH>; |
| + }; |
| + |
| + usb_vbus_5v0: fixedregulator@0 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "vbus"; |
| + regulator-min-microvolt = <5000000>; |
| + regulator-max-microvolt = <5000000>; |
| + regulator-type = "voltage"; |
| + regulator-always-on; |
| + }; |
| + |
| + usb_vbus_3v3: fixedregulator@1 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "usb vbus"; |
| + regulator-min-microvolt = <3300000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-always-on; |
| + }; |
| +}; |
| + |
| +/* for CORE */ |
| +&mt6359_vgpu11_buck_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +/* for APU */ |
| +&mt6359_vproc1_buck_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +/* for EMMC */ |
| +&mt6359_vufs_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vemc_1_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vaud18_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vrf12_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&pmic { |
| + interrupt-parent = <&pio>; |
| + interrupts = <214 IRQ_TYPE_LEVEL_HIGH>; |
| +}; |
| + |
| +&spmi_bus { |
| + grpid = <11>; |
| + mt6315_6: mt6315@6 { |
| + compatible = "mediatek,mt6315_6-regulator"; |
| + reg = <0x6 0 0xb 1>; |
| + |
| + mt6315_6_vbuck1: 6_vbuck1 { |
| + regulator-name = "6_vbuck1"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + |
| + mt6315_6_vbuck3: 6_vbuck3 { |
| + regulator-name = "6_vbuck3"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + }; |
| + |
| + mt6315_7: mt6315@7 { |
| + compatible = "mediatek,mt6315_7-regulator"; |
| + reg = <0x7 0 0xb 1>; |
| + |
| + mt6315_7_vbuck1: 7_vbuck1 { |
| + regulator-name = "7_vbuck1"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + |
| + mt6315_7_vbuck3: 7_vbuck3 { |
| + regulator-name = "7_vbuck3"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + }; |
| + }; |
| +}; |
| + |
| +&uart0 { |
| + status = "okay"; |
| +}; |
| + |
| +&gpu { |
| + supply-names = "mali","mali_sram"; |
| + mali-supply = <&mt6315_7_vbuck1>; |
| + mali_sram-supply = <&mt6359_vsram_others_ldo_reg>; |
| + operating-points-v2 = <&gpu_opp_table>; |
| + power_model@0 { |
| + compatible = "arm,mali-simple-power-model"; |
| + static-coefficient = <2427750>; |
| + dynamic-coefficient = <4687>; |
| + ts = <20000 2000 (-20) 2>; |
| + thermal-zone = "cpu_thermal"; |
| + }; |
| + power_model@1 { |
| + compatible = "arm,mali-tnax-power-model"; |
| + scale = <5>; |
| + }; |
| +}; |
| + |
| +&mmc0 { |
| + status = "okay"; |
| + pinctrl-names = "default", "state_uhs"; |
| + pinctrl-0 = <&mmc0_pins_default>; |
| + pinctrl-1 = <&mmc0_pins_uhs>; |
| + bus-width = <8>; |
| + max-frequency = <200000000>; |
| + cap-mmc-highspeed; |
| + mmc-hs200-1_8v; |
| + mmc-hs400-1_8v; |
| + supports-cqe; |
| + cap-mmc-hw-reset; |
| + hs400-ds-delay = <0x12814>; |
| + no-sdio; |
| + no-sd; |
| + vmmc-supply = <&mt6359_vemc_1_ldo_reg >; |
| + vqmmc-supply = <&mt6359_vio18_ldo_reg>; |
| + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; |
| + non-removable; |
| + pinctrl-names = "default", "state_uhs"; |
| + pinctrl-0 = <&mmc0_pins_default>; |
| + pinctrl-1 = <&mmc0_pins_uhs>; |
| +}; |
| + |
| +&mmc1 { |
| + status = "okay"; |
| + pinctrl-names = "default", "state_uhs"; |
| + pinctrl-0 = <&mmc1_pins_default>; |
| + pinctrl-1 = <&mmc1_pins_uhs>; |
| + bus-width = <4>; |
| + max-frequency = <200000000>; |
| + cap-sd-highspeed; |
| + /*sd-uhs-sdr50; |
| + sd-uhs-sdr104;*/ |
| + cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; |
| + vmmc-supply = <&mt6360_ldo5_reg>; |
| + vqmmc-supply = <&mt6360_ldo3_reg>; |
| + no-mmc; |
| + no-sdio; |
| + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; |
| +}; |
| + |
| +&dpi0 { |
| + pinctrl-names = "default", "dpimode"; |
| + pinctrl-0 = <&dpi_pin_default>; |
| + pinctrl-1 = <&dpi_pin_func>; |
| + status = "disabled"; |
| +}; |
| + |
| +&dsi0 { |
| + status = "okay"; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + |
| + ports { |
| + port { |
| + dsi_out: endpoint { |
| + remote-endpoint = <&anx7625_in>; |
| + }; |
| + }; |
| + }; |
| +}; |
| + |
| +&mipi_tx0 { |
| + status = "okay"; |
| +}; |
| + |
| +&pio{ |
| + dpi_pin_default: dpi_pin_default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO96__FUNC_GPIO96>, |
| + <PINMUX_GPIO97__FUNC_GPIO97>, |
| + <PINMUX_GPIO98__FUNC_GPIO98>, |
| + <PINMUX_GPIO99__FUNC_GPIO99>, |
| + <PINMUX_GPIO100__FUNC_GPIO100>, |
| + <PINMUX_GPIO101__FUNC_GPIO101>, |
| + <PINMUX_GPIO102__FUNC_GPIO102>, |
| + <PINMUX_GPIO103__FUNC_GPIO103>, |
| + <PINMUX_GPIO104__FUNC_GPIO104>, |
| + <PINMUX_GPIO105__FUNC_GPIO105>, |
| + <PINMUX_GPIO106__FUNC_GPIO106>, |
| + <PINMUX_GPIO110__FUNC_GPIO110>, |
| + <PINMUX_GPIO113__FUNC_GPIO113>, |
| + <PINMUX_GPIO111__FUNC_GPIO111>, |
| + <PINMUX_GPIO109__FUNC_GPIO109>, |
| + <PINMUX_GPIO112__FUNC_GPIO112>; |
| + drive-strength = <MTK_DRIVE_6mA>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + dpi_pin_func: dpi_pin_func { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO96__FUNC_DPI_D0>, |
| + <PINMUX_GPIO97__FUNC_DPI_D1>, |
| + <PINMUX_GPIO98__FUNC_DPI_D2>, |
| + <PINMUX_GPIO99__FUNC_DPI_D3>, |
| + <PINMUX_GPIO100__FUNC_DPI_D4>, |
| + <PINMUX_GPIO101__FUNC_DPI_D5>, |
| + <PINMUX_GPIO102__FUNC_DPI_D6>, |
| + <PINMUX_GPIO103__FUNC_DPI_D7>, |
| + <PINMUX_GPIO104__FUNC_DPI_D8>, |
| + <PINMUX_GPIO105__FUNC_DPI_D9>, |
| + <PINMUX_GPIO106__FUNC_DPI_D10>, |
| + <PINMUX_GPIO110__FUNC_DPI_D11>, |
| + <PINMUX_GPIO113__FUNC_DPI_HSYNC>, |
| + <PINMUX_GPIO111__FUNC_DPI_VSYNC>, |
| + <PINMUX_GPIO109__FUNC_DPI_DE>, |
| + <PINMUX_GPIO112__FUNC_DPI_CK>; |
| + drive-strength = <MTK_DRIVE_6mA>; |
| + }; |
| + }; |
| + |
| + mmc0_pins_default: mmc0default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, |
| + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, |
| + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, |
| + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, |
| + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, |
| + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, |
| + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, |
| + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, |
| + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-up-adv = <2>; |
| + }; |
| + |
| + pins_clk { |
| + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-down-adv = <2>; |
| + }; |
| + |
| + pins_rst { |
| + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; |
| + drive-strength = <MTK_DRIVE_14mA>; |
| + mediatek,pull-down-adv = <01>; |
| + }; |
| + }; |
| + |
| + mmc0_pins_uhs: mmc0uhs{ |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, |
| + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, |
| + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, |
| + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, |
| + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, |
| + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, |
| + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, |
| + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, |
| + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-up-adv = <2>; |
| + }; |
| + |
| + pins_clk { |
| + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-down-adv = <2>; |
| + }; |
| + |
| + pins_rst { |
| + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; |
| + drive-strength = <MTK_DRIVE_14mA>; |
| + mediatek,pull-down-adv = <01>; |
| + }; |
| + |
| + pins_ds { |
| + pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; |
| + drive-strength = <MTK_DRIVE_14mA>; |
| + mediatek,pull-down-adv = <2>; |
| + }; |
| + }; |
| + |
| + mmc1_pins_default: mmc1default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, |
| + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, |
| + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, |
| + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, |
| + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-up-adv = <2>; |
| + }; |
| + |
| + pins_clk { |
| + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + mediatek,pull-down-adv = <2>; |
| + }; |
| + |
| + pins_insert { |
| + pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; |
| + input-enable; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + mmc1_pins_uhs: mmc1@0 { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, |
| + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, |
| + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, |
| + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, |
| + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_8mA>; |
| + mediatek,pull-up-adv = <10>; |
| + }; |
| + |
| + pins_clk { |
| + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; |
| + drive-strength = <MTK_DRIVE_8mA>; |
| + mediatek,pull-down-adv = <10>; |
| + input-enable; |
| + }; |
| + }; |
| + |
| + nor_gpio1_pins: nor { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, |
| + <PINMUX_GPIO28__FUNC_SPINOR_IO1>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + bias-pull-up; |
| + }; |
| + |
| + pins2 { |
| + pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + bias-pull-up; |
| + }; |
| + |
| + pins_clk { |
| + pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; |
| + input-enable; |
| + drive-strength = <MTK_DRIVE_4mA>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + pcie_pinmux: pcie_pinmux { |
| + pcie_wake { |
| + pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; |
| + }; |
| + pcie_pereset { |
| + pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; |
| + }; |
| + pcie_clkreq { |
| + pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; |
| + }; |
| + pcie_en_pp3300_wlan { |
| + /* TODO: Model as a regulator */ |
| + pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; |
| + output-high; |
| + }; |
| + /* TODO: Split and implement. */ |
| + wifi_kill { |
| + pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; /* WIFI_KILL_L */ |
| + output-high; |
| + }; |
| + }; |
| + |
| + pwm0_pin_default: pwm0_pin_default { |
| + pins_pwm { |
| + //HACK: Always set backlight on |
| + //pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; |
| + pinmux = <PINMUX_GPIO40__FUNC_GPIO40>; |
| + output-high; |
| + }; |
| + pins_inhibit { |
| + pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; |
| + output-high; |
| + }; |
| + }; |
| + |
| + ec_ap_int_odl: ec_ap_int_odl { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; |
| + input-enable; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + h1_int_od_l: h1_int_od_l { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; |
| + input-enable; |
| + }; |
| + }; |
| + |
| + i2c0_pins: i2c0 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO204__FUNC_SCL0>, |
| + <PINMUX_GPIO205__FUNC_SDA0>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + i2c1_pins: i2c1 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO118__FUNC_SCL1>, |
| + <PINMUX_GPIO119__FUNC_SDA1>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + i2c2_pins: i2c2 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO141__FUNC_SCL2>, |
| + <PINMUX_GPIO142__FUNC_SDA2>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + i2c3_pins: i2c3 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO160__FUNC_SCL3>, |
| + <PINMUX_GPIO161__FUNC_SDA3>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + i2c6_pins: i2c6 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO200__FUNC_SCL6>, |
| + <PINMUX_GPIO201__FUNC_SDA6>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + i2c7_pins: i2c7 { |
| + pins_bus { |
| + pinmux = <PINMUX_GPIO124__FUNC_SCL7>, |
| + <PINMUX_GPIO125__FUNC_SDA7>; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + pp1000_mipibrdg_en: pp1000-mipibrdg-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + pp1000_dpbrdg_en: pp1000-dpbrdg-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO30__FUNC_GPIO30>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + pp1800_mipibrdg_en: pp1800-mipibrd-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + pp1800_dpbrdg_en: pp1800-dpbrdg-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + pp3300_panel_pins: pp3300-panel-pins { |
| + panel_3v3_enable: panel-3v3-enable { |
| + pinmux = <PINMUX_GPIO136__FUNC_GPIO136>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + ppvarp_lcd_en: ppvarp-lcd-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + ppvarn_lcd_en: ppvarn-lcd-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + anx7625_pins: anx7625-pins { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, |
| + <PINMUX_GPIO42__FUNC_GPIO42>; |
| + output-low; |
| + }; |
| + pins2 { |
| + pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; |
| + input-enable; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + anx7625_dp_pins: anx7625-dp-pins { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO8__FUNC_GPIO8>, |
| + <PINMUX_GPIO9__FUNC_GPIO9>; |
| + output-low; |
| + }; |
| + pins2 { |
| + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; |
| + input-enable; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + pp3300_mipibrdg_en: pp3300-mipibrdg-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + pp3300_dpbrdg_en: pp3300-dpbrdg-en { |
| + pins1 { |
| + pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + spi_pins_1: spi1@0 { |
| + pins_spi{ |
| + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, |
| + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, |
| + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; |
| + bias-disable; |
| + }; |
| + pins_spi_mi { |
| + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; |
| + bias-pull-down; |
| + }; |
| + }; |
| + |
| + spi_pins_5: spi5@0 { |
| + pins_spi{ |
| + pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, |
| + <PINMUX_GPIO37__FUNC_GPIO37>, |
| + <PINMUX_GPIO39__FUNC_SPI5_A_MO>, |
| + <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; |
| + bias-disable; |
| + }; |
| + }; |
| + |
| + touchpad_pins: touchpad-pins { |
| + touchpad_int { |
| + pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; |
| + input-enable; |
| + mediatek,pull-up-adv = <3>; |
| + }; |
| + }; |
| + |
| + bt_pins: bt-pins { |
| + uart_pins { |
| + pinmux = <PINMUX_GPIO94__FUNC_URXD1>, |
| + <PINMUX_GPIO95__FUNC_UTXD1>, |
| + <PINMUX_GPIO166__FUNC_UCTS1>, |
| + <PINMUX_GPIO167__FUNC_URTS1>; |
| + }; |
| + bt_kill { |
| + pinmux = <PINMUX_GPIO131__FUNC_GPIO131>; /* BT_KILL_L */ |
| + output-low; |
| + }; |
| + }; |
| +}; |
| + |
| +&pwm0 { |
| + status = "okay"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pwm0_pin_default>; |
| +}; |
| + |
| +&i2c0 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c0_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + /* TODO: Add touchscreen */ |
| +}; |
| + |
| +&i2c1 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c1_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + /* TODO: Add audio components */ |
| +}; |
| + |
| +&i2c2 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c2_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + touchpad@15 { |
| + compatible = "elan,ekth3000"; |
| + reg = <0x15>; |
| + |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&touchpad_pins>; |
| + |
| + interrupt-parent = <&pio>; |
| + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; |
| + |
| + wakeup-source; |
| + }; |
| + |
| +}; |
| + |
| +&i2c3 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c3_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + anx_bridge: anx7625@58 { |
| + compatible = "analogix,anx7625"; |
| + reg = <0x58>; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&anx7625_pins>; |
| + panel_flags = <1>; |
| + enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; |
| + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; |
| + vdd10-supply = <&pp1000_mipibrdg>; |
| + vdd18-supply = <&pp1800_mipibrdg>; |
| + vdd33-supply = <&pp3300_mipibrdg>; |
| + |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + port@0 { |
| + reg = <0>; |
| + |
| + anx7625_in: endpoint { |
| + remote-endpoint = <&dsi_out>; |
| + }; |
| + }; |
| + |
| + port@2 { |
| + reg = <2>; |
| + |
| + anx7625_out: endpoint { |
| + remote-endpoint = <&panel_in>; |
| + }; |
| + }; |
| + }; |
| +}; |
| + |
| +&i2c6 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c6_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + /* TODO: Add SAR sensor. */ |
| +}; |
| + |
| +&i2c7 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&i2c7_pins>; |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| + |
| + /* TODO: Add ANX7625 external DP bridge. */ |
| +}; |
| + |
| +&nor_flash { |
| + status = "okay"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&nor_gpio1_pins>; |
| + bus-width = <8>; |
| + max-frequency = <50000000>; |
| + non-removable; |
| + flash@0 { |
| + compatible = "jedec,spi-nor"; |
| + reg = <0>; |
| + }; |
| +}; |
| + |
| +&pcie { |
| + status = "okay"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pcie_pinmux>; |
| +}; |
| + |
| +&spi1 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&spi_pins_1>; |
| + mediatek,pad-select = <0>; |
| + status = "okay"; |
| + |
| + cros_ec: ec@0 { |
| + compatible = "google,cros-ec-spi"; |
| + reg = <0>; |
| + spi-max-frequency = <3000000>; |
| + interrupt-parent = <&pio>; |
| + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&ec_ap_int_odl>; |
| + |
| + i2c_tunnel: i2c-tunnel { |
| + compatible = "google,cros-ec-i2c-tunnel"; |
| + google,remote-bus = <0>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + }; |
| + |
| + base_detection: cbas { |
| + compatible = "google,cros-cbas"; |
| + }; |
| + |
| + usbc_extcon: extcon@0 { |
| + compatible = "google,extcon-usbc-cros-ec"; |
| + google,usb-port-id = <0>; |
| + #extcon-cells = <0>; |
| + }; |
| + }; |
| +}; |
| + |
| +#include <arm/cros-ec-keyboard.dtsi> |
| +#include <arm/cros-ec-sbs.dtsi> |
| + |
| +&spi5 { |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&spi_pins_5>; |
| + mediatek,pad-select = <0>; |
| + status = "okay"; |
| + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; |
| + |
| + cr50@0 { |
| + compatible = "google,cr50"; |
| + reg = <0>; |
| + spi-max-frequency = <1000000>; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&h1_int_od_l>; |
| + interrupt-parent = <&pio>; |
| + interrupts = <171 IRQ_TYPE_EDGE_RISING>; |
| + }; |
| + |
| +}; |
| + |
| +&ssusb { |
| + vusb33-supply = <&usb_vbus_3v3>; |
| + vbus-supply = <&usb_vbus_5v0>; |
| + dr_mode = "host"; |
| + |
| + maximum-speed = "high-speed"; |
| + |
| + /* TODO: Check all these parameters. */ |
| + /*usb3-lpm-capable;*/ |
| + |
| + /* wakeup-source; */ |
| + /* mediatek,u3p-dis-msk = <0x1>; */ |
| + |
| + /*mediatek,usb3-drd;*/ |
| + |
| + enable-manual-drd; |
| + /*usb-role-switch;*/ |
| + /*extcon = <&extcon_usb>;*/ |
| + |
| + status = "okay"; |
| +}; |
| + |
| +&uart1 { |
| + status = "okay"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&bt_pins>; |
| + |
| + bluetooth { |
| + compatible = "realtek,rtl8822cs-bt"; |
| + |
| + enable-gpios = <&pio 131 GPIO_ACTIVE_HIGH>; |
| + }; |
| +}; |
| diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..b7990daaa4ac06ac2f2d0ca98a8ff593b0129747 |
| --- /dev/null |
| +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts |
| @@ -0,0 +1,327 @@ |
| +// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| +/* |
| + * Copyright (C) 2020 MediaTek Inc. |
| + * Author: Seiya Wang <seiya.wang@mediatek.com> |
| + */ |
| +/dts-v1/; |
| +#include <dt-bindings/gpio/gpio.h> |
| +#include "mt8192.dtsi" |
| +#include "mt6359.dtsi" |
| + |
| +/ { |
| + model = "MediaTek MT8192 evaluation board"; |
| + compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; |
| + |
| + aliases { |
| + serial0 = &uart0; |
| + }; |
| + |
| + backlight_lcd0: backlight_lcd0 { |
| + compatible = "pwm-backlight"; |
| + pwms = <&pwm0 0 26000>; |
| + brightness-levels = < |
| + 0 64 128 192 256 320 384 448 |
| + 512 576 640 704 768 832 896 960 |
| + 1023>; |
| + default-brightness-level = <9>; |
| + status = "okay"; |
| + }; |
| + |
| + chosen { |
| + stdout-path = "serial0:921600n8"; |
| + }; |
| + |
| + memory@40000000 { |
| + device_type = "memory"; |
| + reg = <0 0x40000000 0 0x80000000>; |
| + }; |
| + |
| + extcon_usb: extcon_iddig { |
| + compatible = "linux,extcon-usb-gpio"; |
| + /* id-gpio = <&pio 8 GPIO_ACTIVE_HIGH>; */ |
| + status = "disabled"; |
| + }; |
| + |
| + usb_vbus_5v0: fixedregulator@0 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "vbus"; |
| + regulator-min-microvolt = <5000000>; |
| + regulator-max-microvolt = <5000000>; |
| + regulator-type = "voltage"; |
| + regulator-always-on; |
| + }; |
| + |
| + usb_vbus_3v3: fixedregulator@1 { |
| + compatible = "regulator-fixed"; |
| + regulator-name = "usb vbus"; |
| + regulator-min-microvolt = <3300000>; |
| + regulator-max-microvolt = <3300000>; |
| + regulator-always-on; |
| + }; |
| + |
| + bring-up { |
| + compatible = "mediatek,clk-bring-up"; |
| + clocks = <&topckgen CLK_TOP_I2C_SEL>, |
| + <&infracfg CLK_INFRA_SSPM>, |
| + <&infracfg CLK_INFRA_MCUPM>; |
| + }; |
| +}; |
| + |
| +&dpi0 { |
| + pinctrl-names = "default", "dpimode"; |
| + pinctrl-0 = <&dpi_pin_default>; |
| + pinctrl-1 = <&dpi_pin_func>; |
| + status = "disabled"; |
| +}; |
| + |
| +&dsi0 { |
| + status = "okay"; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + panel: panel@0 { |
| + compatible = "td,td4330"; |
| + reg = <0>; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&panel_pins_default>; |
| + reset-gpios = <&pio 42 0>; |
| + backlight = <&backlight_lcd0>; |
| + status = "okay"; |
| + port { |
| + panel_in: endpoint { |
| + remote-endpoint = <&dsi_out>; |
| + }; |
| + }; |
| + }; |
| + |
| + ports { |
| + port { |
| + dsi_out: endpoint { |
| + remote-endpoint = <&panel_in>; |
| + }; |
| + }; |
| + }; |
| +}; |
| + |
| +&mipi_tx0 { |
| + status = "okay"; |
| +}; |
| + |
| +&pio{ |
| + dpi_pin_default: dpi_pin_default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO96__FUNC_GPIO96>, |
| + <PINMUX_GPIO97__FUNC_GPIO97>, |
| + <PINMUX_GPIO98__FUNC_GPIO98>, |
| + <PINMUX_GPIO99__FUNC_GPIO99>, |
| + <PINMUX_GPIO100__FUNC_GPIO100>, |
| + <PINMUX_GPIO101__FUNC_GPIO101>, |
| + <PINMUX_GPIO102__FUNC_GPIO102>, |
| + <PINMUX_GPIO103__FUNC_GPIO103>, |
| + <PINMUX_GPIO104__FUNC_GPIO104>, |
| + <PINMUX_GPIO105__FUNC_GPIO105>, |
| + <PINMUX_GPIO106__FUNC_GPIO106>, |
| + <PINMUX_GPIO110__FUNC_GPIO110>, |
| + <PINMUX_GPIO113__FUNC_GPIO113>, |
| + <PINMUX_GPIO111__FUNC_GPIO111>, |
| + <PINMUX_GPIO109__FUNC_GPIO109>, |
| + <PINMUX_GPIO112__FUNC_GPIO112>; |
| + drive-strength = <MTK_DRIVE_6mA>; |
| + output-low; |
| + }; |
| + }; |
| + |
| + dpi_pin_func: dpi_pin_func { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO96__FUNC_DPI_D0>, |
| + <PINMUX_GPIO97__FUNC_DPI_D1>, |
| + <PINMUX_GPIO98__FUNC_DPI_D2>, |
| + <PINMUX_GPIO99__FUNC_DPI_D3>, |
| + <PINMUX_GPIO100__FUNC_DPI_D4>, |
| + <PINMUX_GPIO101__FUNC_DPI_D5>, |
| + <PINMUX_GPIO102__FUNC_DPI_D6>, |
| + <PINMUX_GPIO103__FUNC_DPI_D7>, |
| + <PINMUX_GPIO104__FUNC_DPI_D8>, |
| + <PINMUX_GPIO105__FUNC_DPI_D9>, |
| + <PINMUX_GPIO106__FUNC_DPI_D10>, |
| + <PINMUX_GPIO110__FUNC_DPI_D11>, |
| + <PINMUX_GPIO113__FUNC_DPI_HSYNC>, |
| + <PINMUX_GPIO111__FUNC_DPI_VSYNC>, |
| + <PINMUX_GPIO109__FUNC_DPI_DE>, |
| + <PINMUX_GPIO112__FUNC_DPI_CK>; |
| + drive-strength = <MTK_DRIVE_6mA>; |
| + }; |
| + }; |
| + |
| + panel_pins_default: panel_pins_default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO42__FUNC_GPIO42>; |
| + output-low; |
| + bias-pull-up; |
| + }; |
| + }; |
| + |
| + pwm0_pin_default: pwm0_pin_default { |
| + pins_cmd_dat { |
| + pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; |
| + }; |
| + }; |
| +}; |
| + |
| +&pmic { |
| + interrupt-parent = <&pio>; |
| + interrupts = <214 IRQ_TYPE_LEVEL_HIGH>; |
| +}; |
| + |
| +&pwm0 { |
| + status = "okay"; |
| + pinctrl-names = "default"; |
| + pinctrl-0 = <&pwm0_pin_default>; |
| +}; |
| + |
| +&uart0 { |
| + status = "okay"; |
| +}; |
| + |
| +&i2c0 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&i2c1 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&i2c2 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&i2c3 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&i2c4 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&i2c5 { |
| + status = "okay"; |
| + clock-frequency = <100000>; |
| +}; |
| + |
| +&ssusb { |
| + vusb33-supply = <&usb_vbus_3v3>; |
| + vbus-supply = <&usb_vbus_5v0>; |
| + /* valid string: "", "host", "peripheral", "otg" */ |
| + dr_mode = "host"; |
| + |
| + maximum-speed = "high-speed"; |
| + |
| + /*usb3-lpm-capable;*/ |
| + |
| + /* wakeup-source; */ |
| + /* mediatek,u3p-dis-msk = <0x1>; */ |
| + |
| + /*mediatek,usb3-drd;*/ |
| + |
| + enable-manual-drd; |
| + /*usb-role-switch;*/ |
| + /*extcon = <&extcon_usb>;*/ |
| + |
| + status = "okay"; |
| +}; |
| + |
| +&spmi_bus { |
| + grpid = <11>; |
| + mt6315_6: mt6315@6 { |
| + compatible = "mediatek,mt6315_6-regulator"; |
| + reg = <0x6 0 0xb 1>; |
| + |
| + mt6315_6_vbuck1: 6_vbuck1 { |
| + regulator-name = "6_vbuck1"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + |
| + mt6315_6_vbuck3: 6_vbuck3 { |
| + regulator-name = "6_vbuck3"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + }; |
| + |
| + mt6315_7: mt6315@7 { |
| + compatible = "mediatek,mt6315_7-regulator"; |
| + reg = <0x7 0 0xb 1>; |
| + |
| + mt6315_7_vbuck1: 7_vbuck1 { |
| + regulator-name = "7_vbuck1"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + regulator-allowed-modes = <0 1 2 4>; |
| + regulator-always-on; |
| + }; |
| + |
| + mt6315_7_vbuck3: 7_vbuck3 { |
| + regulator-name = "7_vbuck3"; |
| + regulator-min-microvolt = <300000>; |
| + regulator-max-microvolt = <1193750>; |
| + regulator-enable-ramp-delay = <256>; |
| + }; |
| + }; |
| +}; |
| + |
| +&gpu { |
| + supply-names = "mali","mali_sram"; |
| + mali-supply = <&mt6315_7_vbuck1>; |
| + mali_sram-supply = <&mt6359_vsram_others_ldo_reg>; |
| + operating-points-v2 = <&gpu_opp_table>; |
| + power_model@0 { |
| + compatible = "arm,mali-simple-power-model"; |
| + static-coefficient = <2427750>; |
| + dynamic-coefficient = <4687>; |
| + ts = <20000 2000 (-20) 2>; |
| + thermal-zone = "cpu_thermal"; |
| + }; |
| + power_model@1 { |
| + compatible = "arm,mali-tnax-power-model"; |
| + scale = <5>; |
| + }; |
| +}; |
| + |
| +/* for CORE */ |
| +&mt6359_vgpu11_buck_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +/* for APU */ |
| +&mt6359_vproc1_buck_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +/* for EMMC */ |
| +&mt6359_vufs_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vemc_1_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vaud18_ldo_reg { |
| + regulator-always-on; |
| +}; |
| + |
| +&mt6359_vrf12_ldo_reg { |
| + regulator-always-on; |
| +}; |
| diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..b806705296894e779f1e158e9e775ea8bf1f3eb6 |
| --- /dev/null |
| +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi |
| @@ -0,0 +1,1460 @@ |
| +// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| +/* |
| + * Copyright (C) 2020 MediaTek Inc. |
| + * Author: Seiya Wang <seiya.wang@mediatek.com> |
| + */ |
| + |
| +/dts-v1/; |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| +#include <dt-bindings/interrupt-controller/arm-gic.h> |
| +#include <dt-bindings/interrupt-controller/irq.h> |
| +#include <dt-bindings/memory/mt8192-larb-port.h> |
| +#include <dt-bindings/pinctrl/mt6873-pinfunc.h> |
| +#include <dt-bindings/phy/phy.h> |
| +#include <dt-bindings/power/mt8192-power.h> |
| +#include <dt-bindings/reset-controller/mt8192-resets.h> |
| + |
| +/ { |
| + compatible = "mediatek,mt6873"; |
| + interrupt-parent = <&gic>; |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + |
| + aliases { |
| + i2c0 = &i2c0; |
| + i2c1 = &i2c1; |
| + i2c2 = &i2c2; |
| + i2c3 = &i2c3; |
| + i2c4 = &i2c4; |
| + i2c5 = &i2c5; |
| + i2c6 = &i2c6; |
| + i2c7 = &i2c7; |
| + i2c8 = &i2c8; |
| + i2c9 = &i2c9; |
| + ovl0 = &ovl0; |
| + ovl_2l0 = &ovl_2l0; |
| + ovl_2l2 = &ovl_2l2; |
| + rdma0 = &rdma0; |
| + rdma4 = &rdma4; |
| + }; |
| + |
| + /* chosen */ |
| + chosen: chosen { |
| + bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/mmcblk0p43 rootwait earlycon=mtk8250,mmio32,0x11002000 earlyprintk=ttyS0,921600n8 "; |
| + kaslr-seed = <0 0>; |
| + }; |
| + |
| + clocks { |
| + clk26m: oscillator@0 { |
| + compatible = "fixed-clock"; |
| + #clock-cells = <0>; |
| + clock-frequency = <26000000>; |
| + clock-output-names = "clk26m"; |
| + }; |
| + |
| + clk32k: oscillator@1 { |
| + compatible = "fixed-clock"; |
| + #clock-cells = <0>; |
| + clock-frequency = <32768>; |
| + clock-output-names = "clk32k"; |
| + }; |
| + }; |
| + |
| + cpus { |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + |
| + cpu0: cpu@000 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a55"; |
| + reg = <0x0000>; |
| + enable-method = "psci"; |
| + clock-frequency = <1701000000>; |
| + }; |
| + |
| + cpu1: cpu@001 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a55"; |
| + reg = <0x0100>; |
| + enable-method = "psci"; |
| + clock-frequency = <1701000000>; |
| + }; |
| + |
| + cpu2: cpu@002 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a55"; |
| + reg = <0x0200>; |
| + enable-method = "psci"; |
| + clock-frequency = <1701000000>; |
| + }; |
| + |
| + cpu3: cpu@003 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a55"; |
| + reg = <0x0300>; |
| + enable-method = "psci"; |
| + clock-frequency = <1701000000>; |
| + }; |
| + |
| + cpu4: cpu@100 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a76"; |
| + reg = <0x0400>; |
| + enable-method = "psci"; |
| + clock-frequency = <2171000000>; |
| + }; |
| + |
| + cpu5: cpu@101 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a76"; |
| + reg = <0x0500>; |
| + enable-method = "psci"; |
| + clock-frequency = <2171000000>; |
| + }; |
| + |
| + cpu6: cpu@102 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a76"; |
| + reg = <0x0600>; |
| + enable-method = "psci"; |
| + clock-frequency = <2171000000>; |
| + }; |
| + |
| + cpu7: cpu@103 { |
| + device_type = "cpu"; |
| + compatible = "arm,cortex-a76"; |
| + reg = <0x0700>; |
| + enable-method = "psci"; |
| + clock-frequency = <2171000000>; |
| + }; |
| + |
| + cpu-map { |
| + cluster0 { |
| + core0 { |
| + cpu = <&cpu0>; |
| + }; |
| + core1 { |
| + cpu = <&cpu1>; |
| + }; |
| + core2 { |
| + cpu = <&cpu2>; |
| + }; |
| + core3 { |
| + cpu = <&cpu3>; |
| + }; |
| + }; |
| + |
| + cluster1 { |
| + core0 { |
| + cpu = <&cpu4>; |
| + }; |
| + core1 { |
| + cpu = <&cpu5>; |
| + }; |
| + core2 { |
| + cpu = <&cpu6>; |
| + }; |
| + core3 { |
| + cpu = <&cpu7>; |
| + }; |
| + }; |
| + }; |
| + }; |
| + |
| + gic: interrupt-controller { |
| + compatible = "arm,gic-v3"; |
| + #interrupt-cells = <4>; |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + #redistributor-regions = <1>; |
| + interrupt-parent = <&gic>; |
| + interrupt-controller; |
| + reg = <0 0x0c000000 0 0x40000>, // distributor |
| + <0 0x0c040000 0 0x200000>; // redistributor |
| + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| + |
| + ppi-partitions { |
| + ppi_cluster0: interrupt-partition-0 { |
| + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; |
| + }; |
| + ppi_cluster1: interrupt-partition-1 { |
| + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; |
| + }; |
| + }; |
| + }; |
| + |
| + pmu-a55 { |
| + compatible = "arm,cortex-a55-pmu"; |
| + interrupt-parent = <&gic>; |
| + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; |
| + }; |
| + |
| + pmu-a76 { |
| + compatible = "arm,cortex-a76-pmu"; |
| + interrupt-parent = <&gic>; |
| + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; |
| + }; |
| + |
| + psci { |
| + compatible = "arm,psci-1.0"; |
| + method = "smc"; |
| + }; |
| + |
| + reserved_memory: reserved-memory { |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + ranges; |
| + }; |
| + |
| + timer: timer { |
| + compatible = "arm,armv8-timer"; |
| + interrupt-parent = <&gic>; |
| + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clock-frequency = <13000000>; |
| + }; |
| + |
| + soc { |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + compatible = "simple-bus"; |
| + ranges; |
| + |
| + topckgen: topckgen@10000000 { |
| + compatible = "mediatek,mt8192-topckgen", "syscon"; |
| + reg = <0 0x10000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + infracfg: infracfg@10001000 { |
| + compatible = "mediatek,mt8192-infracfg", "syscon"; |
| + reg = <0 0x10001000 0 0x1000>; |
| + #clock-cells = <1>; |
| + #reset-cells = <1>; |
| + }; |
| + |
| + pericfg: pericfg@10003000 { |
| + compatible = "mediatek,mt8192-pericfg", "syscon"; |
| + reg = <0 0x10003000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + pio: pinctrl@10005000 { |
| + compatible = "mediatek,mt6873-pinctrl"; |
| + reg = <0 0x10005000 0 0x1000>, |
| + <0 0x11c20000 0 0x1000>, |
| + <0 0x11d10000 0 0x1000>, |
| + <0 0x11d30000 0 0x1000>, |
| + <0 0x11d40000 0 0x1000>, |
| + <0 0x11e20000 0 0x1000>, |
| + <0 0x11e70000 0 0x1000>, |
| + <0 0x11ea0000 0 0x1000>, |
| + <0 0x11f20000 0 0x1000>, |
| + <0 0x11f30000 0 0x1000>, |
| + <0 0x1000b000 0 0x1000>; |
| + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", |
| + "iocfg_bl", "iocfg_br", "iocfg_lm", |
| + "iocfg_lb", "iocfg_rt", "iocfg_lt", |
| + "iocfg_tl", "eint"; |
| + gpio-controller; |
| + #gpio-cells = <2>; |
| + gpio-ranges = <&pio 0 0 220>; |
| + interrupt-controller; |
| + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; |
| + #interrupt-cells = <2>; |
| + }; |
| + |
| + scpsys: power-controller@10006000 { |
| + compatible = "mediatek,mt8192-scpsys", "syscon"; |
| + reg = <0 0x10006000 0 0x1000>; |
| + #power-domain-cells = <1>; |
| + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, |
| + <&topckgen CLK_TOP_IMG1_SEL>, |
| + <&topckgen CLK_TOP_IMG2_SEL>, |
| + <&topckgen CLK_TOP_IPE_SEL>, |
| + <&topckgen CLK_TOP_VDEC_SEL>, |
| + <&topckgen CLK_TOP_VENC_SEL>, |
| + <&topckgen CLK_TOP_MDP_SEL>, |
| + <&topckgen CLK_TOP_DISP_SEL>, |
| + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| + <&infracfg CLK_INFRA_AUDIO_26M_B>, |
| + <&infracfg CLK_INFRA_AUDIO>, |
| + <&topckgen CLK_TOP_ADSP_SEL>, |
| + <&topckgen CLK_TOP_CAM_SEL>, |
| + <&imgsys CLK_IMG_LARB9>, |
| + <&imgsys CLK_IMG_GALS>, |
| + <&imgsys2 CLK_IMG2_LARB11>, |
| + <&imgsys2 CLK_IMG2_GALS>, |
| + <&ipesys CLK_IPE_LARB19>, |
| + <&ipesys CLK_IPE_LARB20>, |
| + <&ipesys CLK_IPE_SMI_SUBCOM>, |
| + <&ipesys CLK_IPE_GALS>, |
| + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, |
| + <&vdecsys_soc CLK_VDEC_SOC_LAT>, |
| + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, |
| + <&vdecsys CLK_VDEC_VDEC>, |
| + <&vdecsys CLK_VDEC_LAT>, |
| + <&vdecsys CLK_VDEC_LARB1>, |
| + <&vencsys CLK_VENC_SET1_VENC>, |
| + <&mdpsys CLK_MDP_SMI0>, |
| + <&mmsys CLK_MM_SMI_INFRA>, |
| + <&mmsys CLK_MM_SMI_COMMON>, |
| + <&mmsys CLK_MM_SMI_GALS>, |
| + <&mmsys CLK_MM_SMI_IOMMU>, |
| + <&camsys CLK_CAM_LARB13>, |
| + <&camsys CLK_CAM_LARB14>, |
| + <&camsys CLK_CAM_CCU_GALS>, |
| + <&camsys CLK_CAM_CAM2MM_GALS>, |
| + <&camsys_rawa CLK_CAM_RAWA_LARBX>, |
| + <&camsys_rawb CLK_CAM_RAWB_LARBX>, |
| + <&camsys_rawc CLK_CAM_RAWC_LARBX>; |
| + clock-names = "mfg", "isp", "isp2", "ipe", "vdec", "venc", |
| + "mdp", "disp", "audio", "audio1", "audio2", |
| + "adsp", "cam", "isp-0", "isp-1", "isp2-0", |
| + "isp2-1", "ipe-0", "ipe-1", "ipe-2", "ipe-3", |
| + "vdec-0", "vdec-1", "vdec-2", "vdec2-0", "vdec2-1", |
| + "vdec2-2", "venc-0", "mdp-0", "disp-0", "disp-1", |
| + "disp-2", "disp-3", "cam-0", "cam-1", "cam-2", |
| + "cam-3", "cam_rawa-0", "cam_rawb-0", "cam_rawc-0"; |
| + infracfg = <&infracfg>; |
| + }; |
| + |
| + watchdog: watchdog@10007000 { |
| + compatible = "mediatek,mt6873-wdt", |
| + "mediatek,mt6589-wdt"; |
| + reg = <0 0x10007000 0 0x100>; |
| + }; |
| + |
| + apmixedsys: apmixedsys@1000c000 { |
| + compatible = "mediatek,mt8192-apmixedsys", "syscon"; |
| + reg = <0 0x1000c000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + systimer: timer@10017000 { |
| + compatible = "mediatek,mt8192-timer", |
| + "mediatek,mt6765-timer"; |
| + reg = <0 0x10017000 0 0x1000>; |
| + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; |
| + clock-names = "clk13m"; |
| + }; |
| + |
| + pwrap: pwrap@10026000 { |
| + compatible = "mediatek,mt6873-pwrap"; |
| + reg = <0 0x10026000 0 0x1000>; |
| + reg-names = "pwrap"; |
| + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| + <&infracfg CLK_INFRA_PMIC_TMR>; |
| + clock-names = "spi", "wrap"; |
| + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| + }; |
| + |
| + spmi_bus: spmi@10027000 { |
| + compatible = "mediatek,pmif"; |
| + reg = <0 0x10027000 0 0x000e00>, |
| + <0 0x10027f00 0 0x00008c>, |
| + <0 0x10029000 0 0x000100>; |
| + reg-names = "pmif", "pmifmpu", "spmimst"; |
| + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; |
| + interrupt-names = "pmif_irq"; |
| + irq_event_en = <0x0 0x0 0x00300000 0x00000100 0x0>; |
| + clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| + <&infracfg CLK_INFRA_PMIC_TMR>, |
| + <&topckgen CLK_TOP_SPMI_MST_SEL>; |
| + clock-names = "pmif_sys_ck", |
| + "pmif_tmr_ck", |
| + "spmimst_clk_mux"; |
| + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| + swinf_ch_start = <4>; |
| + ap_swinf_no = <2>; |
| + }; |
| + |
| + scp_adsp: scp_adsp@10720000 { |
| + compatible = "mediatek,mt8192-scp_adsp", "syscon"; |
| + reg = <0 0x10720000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + uart0: serial@11002000 { |
| + compatible = "mediatek,mt6873-uart", |
| + "mediatek,mt6577-uart"; |
| + reg = <0 0x11002000 0 0x1000>; |
| + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; |
| + clock-names = "baud", "bus"; |
| + }; |
| + |
| + uart1: serial@11003000 { |
| + compatible = "mediatek,mt6873-uart", |
| + "mediatek,mt6577-uart"; |
| + reg = <0 0x11003000 0 0x1000>; |
| + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; |
| + clock-names = "baud", "bus"; |
| + status = "disabled"; |
| + }; |
| + |
| + imp_iic_wrap_c: imp_iic_wrap_c@11007000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon"; |
| + reg = <0 0x11007000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + audsys: audsys@11210000 { |
| + compatible = "mediatek,mt8192-audsys", "syscon"; |
| + reg = <0 0x11210000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + ufshci@11270000 { |
| + compatible = "mediatek,mt8183-ufshci"; |
| + reg = <0 0x11270000 0 0x2300>; |
| + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; |
| + phys = <&ufsphy>; |
| + clocks = <&infracfg CLK_INFRA_UFS>, |
| + <&infracfg CLK_INFRA_UFS_TICK>, |
| + <&infracfg CLK_INFRA_UFS_AXI>, |
| + <&infracfg CLK_INFRA_UNIPRO_TICK>, |
| + <&infracfg CLK_INFRA_UNIPRO_MBIST>; |
| + clock-names = "ufs", "ufs_tick", "ufs_axi", |
| + "unipro_tick", "unipro_mbist"; |
| + freq-table-hz = <0 0>, <0 0>, <0 0>, |
| + <0 0>, <0 0>; |
| + |
| +#if 0 //power not ready |
| + vcc-supply = <&mt6359_vemc_ldo_reg>; |
| +#endif |
| + /* Reference clock control mode */ |
| + /* SW mode: 0, Half-HW mode: 1, HW mode: 2 */ |
| + mediatek,refclk_ctrl = <1>; |
| + }; |
| + |
| + imp_iic_wrap_e: imp_iic_wrap_e@11cb1000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon"; |
| + reg = <0 0x11cb1000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + imp_iic_wrap_s: imp_iic_wrap_s@11d03000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon"; |
| + reg = <0 0x11d03000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + imp_iic_wrap_ws: imp_iic_wrap_ws@11d23000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon"; |
| + reg = <0 0x11d23000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + imp_iic_wrap_w: imp_iic_wrap_w@11e01000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon"; |
| + reg = <0 0x11e01000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + imp_iic_wrap_n: imp_iic_wrap_n@11f02000 { |
| + compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon"; |
| + reg = <0 0x11f02000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + msdc_top: msdc_top@11f10000 { |
| + compatible = "mediatek,mt8192-msdc_top", "syscon"; |
| + reg = <0 0x11f10000 0 0x1000>; |
| + #clock-cells = <1>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_MSDC>; |
| + }; |
| + |
| + mmc0: mmc@11f60000 { |
| + compatible = "mediatek,mt8192-mmc"; |
| + reg = <0 0x11f60000 0 0x1000>, |
| + <0 0x11f50000 0 0x1000>; |
| + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, |
| + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, |
| + <&msdc_top CLK_MSDC_TOP_SRC_0P>; |
| + clock-names = "source", "hclk", "source_cg"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_MSDC>; |
| + status = "disabled"; |
| + }; |
| + |
| + mmc1: mmc@11f70000 { |
| + compatible = "mediatek,mt8192-mmc"; |
| + reg = <0 0x11f70000 0 0x1000>, |
| + <0 0x11c70000 0 0x1000>; |
| + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, |
| + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, |
| + <&msdc_top CLK_MSDC_TOP_SRC_1P>; |
| + clock-names = "source", "hclk", "source_cg"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_MSDC>; |
| + status = "disabled"; |
| + }; |
| + |
| + ufsphy: phy@11fa0000 { |
| + compatible = "mediatek,mt8183-ufsphy"; |
| + reg = <0 0x11fa0000 0 0xc000>; |
| + #phy-cells = <0>; |
| + clocks = <&infracfg CLK_INFRA_UNIPRO_SYS>, |
| + <&infracfg CLK_INFRA_UFS_MP_SAP_B>; |
| + clock-names = "unipro", "mp"; |
| + }; |
| + |
| + gpu: mali@13000000 { |
| + compatible = "mediatek,mali", "arm,mali-valhall"; |
| + reg = <0 0x13000000 0 0x4000>; |
| + interrupts = |
| + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; |
| + interrupt-names = |
| + "GPU", |
| + "MMU", |
| + "JOB", |
| + "EVENT", |
| + "PWR"; |
| + |
| + /* |
| + * Note: the properties below are not part of the |
| + * upstream binding. |
| + */ |
| + clocks = |
| + <&apmixedsys CLK_APMIXED_MFGPLL>, |
| + <&topckgen CLK_TOP_MFG_PLL_SEL>, |
| + <&topckgen CLK_TOP_MFG_REF_SEL>, |
| + <&mfgcfg CLK_MFG_BG3D>; |
| + clock-names = |
| + "clk_main_parent", |
| + "clk_mux", |
| + "clk_sub_parent", |
| + "subsys_mfg_cg"; |
| + |
| + power-domains = |
| + <&scpsys MT8192_POWER_DOMAIN_MFG2>, |
| + <&scpsys MT8192_POWER_DOMAIN_MFG3>, |
| + <&scpsys MT8192_POWER_DOMAIN_MFG4>, |
| + <&scpsys MT8192_POWER_DOMAIN_MFG5>, |
| + <&scpsys MT8192_POWER_DOMAIN_MFG6>; |
| + power-domain-names = "core0", |
| + "core1", |
| + "core2", |
| + "core3", |
| + "core4"; |
| + }; |
| + |
| + gpu_opp_table: opp_table0 { |
| + /* |
| + * Note: "operating-points-v2-mali" compatible and the |
| + * opp-core-mask properties are not part of upstream |
| + * binding. |
| + */ |
| + |
| + compatible = "operating-points-v2", "operating-points-v2-mali"; |
| + opp-shared; |
| + |
| + opp-358000000 { |
| + opp-hz = /bits/ 64 <358000000>; |
| + opp-hz-real = /bits/ 64 <358000000>, |
| + /bits/ 64 <358000000>; |
| + opp-microvolt = <606250>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-399000000 { |
| + opp-hz = /bits/ 64 <399000000>; |
| + opp-hz-real = /bits/ 64 <399000000>, |
| + /bits/ 64 <399000000>; |
| + opp-microvolt = <618750>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-440000000 { |
| + opp-hz = /bits/ 64 <440000000>; |
| + opp-hz-real = /bits/ 64 <440000000>, |
| + /bits/ 64 <440000000>; |
| + opp-microvolt = <631250>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-482000000 { |
| + opp-hz = /bits/ 64 <482000000>; |
| + opp-hz-real = /bits/ 64 <482000000>, |
| + /bits/ 64 <482000000>; |
| + opp-microvolt = <643750>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-523000000 { |
| + opp-hz = /bits/ 64 <523000000>; |
| + opp-hz-real = /bits/ 64 <523000000>, |
| + /bits/ 64 <523000000>; |
| + opp-microvolt = <656250>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-564000000 { |
| + opp-hz = /bits/ 64 <564000000>; |
| + opp-hz-real = /bits/ 64 <564000000>, |
| + /bits/ 64 <564000000>; |
| + opp-microvolt = <668750>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-605000000 { |
| + opp-hz = /bits/ 64 <605000000>; |
| + opp-hz-real = /bits/ 64 <605000000>, |
| + /bits/ 64 <605000000>; |
| + opp-microvolt = <681250>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-647000000 { |
| + opp-hz = /bits/ 64 <647000000>; |
| + opp-hz-real = /bits/ 64 <647000000>, |
| + /bits/ 64 <647000000>; |
| + opp-microvolt = <693750>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-688000000 { |
| + opp-hz = /bits/ 64 <688000000>; |
| + opp-hz-real = /bits/ 64 <688000000>, |
| + /bits/ 64 <688000000>; |
| + opp-microvolt = <706250>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-724000000 { |
| + opp-hz = /bits/ 64 <724000000>; |
| + opp-hz-real = /bits/ 64 <724000000>, |
| + /bits/ 64 <724000000>; |
| + opp-microvolt = <725000>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-760000000 { |
| + opp-hz = /bits/ 64 <760000000>; |
| + opp-hz-real = /bits/ 64 <760000000>, |
| + /bits/ 64 <760000000>; |
| + opp-microvolt = <743750>, |
| + <750000>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-795000000 { |
| + opp-hz = /bits/ 64 <795000000>; |
| + opp-hz-real = /bits/ 64 <795000000>, |
| + /bits/ 64 <795000000>; |
| + opp-microvolt = <762500>, |
| + <762500>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-831000000 { |
| + opp-hz = /bits/ 64 <831000000>; |
| + opp-hz-real = /bits/ 64 <831000000>, |
| + /bits/ 64 <831000000>; |
| + opp-microvolt = <781250>, |
| + <781250>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-855000000 { |
| + opp-hz = /bits/ 64 <855000000>; |
| + opp-hz-real = /bits/ 64 <855000000>, |
| + /bits/ 64 <855000000>; |
| + opp-microvolt = <793750>, |
| + <793750>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-902000000 { |
| + opp-hz = /bits/ 64 <902000000>; |
| + opp-hz-real = /bits/ 64 <902000000>, |
| + /bits/ 64 <902000000>; |
| + opp-microvolt = <818750>, |
| + <818750>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + |
| + opp-950000000 { |
| + opp-hz = /bits/ 64 <950000000>; |
| + opp-hz-real = /bits/ 64 <950000000>, |
| + /bits/ 64 <950000000>; |
| + opp-microvolt = <843750>, |
| + <843750>; |
| + opp-core-mask = /bits/ 64 <0x1f>; |
| + }; |
| + }; |
| + |
| + |
| + mfgcfg: mfgcfg@13fbf000 { |
| + compatible = "mediatek,mt8192-mfgcfg", "syscon"; |
| + reg = <0 0x13fbf000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + mmsys: mmsys@14000000 { |
| + compatible = "mediatek,mt8192-mmsys", "syscon"; |
| + reg = <0 0x14000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + assigned-clocks = <&topckgen CLK_TOP_DISP_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; |
| + }; |
| + |
| + mutex: mutex@14001000 { |
| + compatible = "mediatek,mt8192-disp-mutex"; |
| + reg = <0 0x14001000 0 0x1000>; |
| + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&mmsys CLK_MM_DISP_CONFIG>, |
| + <&mmsys CLK_MM_26MHZ>, |
| + <&mmsys CLK_MM_DISP_MUTEX0>; |
| + }; |
| + |
| + smi_common: smi@14002000 { |
| + compatible = "mediatek,mt8192-smi-common"; |
| + reg = <0 0x14002000 0 0x1000>; |
| + clocks = <&mmsys CLK_MM_SMI_COMMON>, |
| + <&mmsys CLK_MM_SMI_INFRA>, |
| + <&mmsys CLK_MM_SMI_GALS>, |
| + <&mmsys CLK_MM_SMI_GALS>; |
| + clock-names = "apb", "smi", "gals0", "gals1"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + }; |
| + |
| + larb0: larb@14003000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x14003000 0 0x1000>; |
| + mediatek,larb-id = <0>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + }; |
| + |
| + larb1: larb@14004000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x14004000 0 0x1000>; |
| + mediatek,larb-id = <1>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + }; |
| + |
| + ovl0: ovl@14005000 { |
| + compatible = "mediatek,mt8192-disp-ovl"; |
| + reg = <0 0x14005000 0 0x1000>; |
| + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&mmsys CLK_MM_DISP_OVL0>; |
| + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, |
| + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; |
| + }; |
| + |
| + ovl_2l0: ovl@14006000 { |
| + compatible = "mediatek,mt8192-disp-ovl-2l"; |
| + reg = <0 0x14006000 0 0x1000>; |
| + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; |
| + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, |
| + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; |
| + }; |
| + |
| + rdma0: rdma@14007000 { |
| + compatible = "mediatek,mt8192-disp-rdma"; |
| + reg = <0 0x14007000 0 0x1000>; |
| + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&mmsys CLK_MM_DISP_RDMA0>; |
| + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; |
| + mediatek,larb = <&larb0>; |
| + mediatek,rdma_fifo_size = <5>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; |
| + }; |
| + |
| + color0: color@14009000 { |
| + compatible = "mediatek,mt8192-disp-color", |
| + "mediatek,mt8173-disp-color"; |
| + reg = <0 0x14009000 0 0x1000>; |
| + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_COLOR0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; |
| + }; |
| + |
| + ccorr0: ccorr@1400a000 { |
| + compatible = "mediatek,mt8192-disp-ccorr"; |
| + reg = <0 0x1400a000 0 0x1000>; |
| + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_CCORR0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; |
| + }; |
| + |
| + aal0: aal@1400b000 { |
| + compatible = "mediatek,mt8192-disp-aal"; |
| + reg = <0 0x1400b000 0 0x1000>; |
| + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_AAL0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; |
| + }; |
| + |
| + gamma0: gamma@1400c000 { |
| + compatible = "mediatek,mt8192-disp-gamma"; |
| + reg = <0 0x1400c000 0 0x1000>; |
| + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; |
| + }; |
| + |
| + postmask0: postmask@1400d000 { |
| + compatible = "mediatek,mt8192-disp-postmask"; |
| + reg = <0 0x1400d000 0 0x1000>; |
| + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; |
| + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; |
| + }; |
| + |
| + dither0: dither@1400e000 { |
| + compatible = "mediatek,mt8192-disp-dither"; |
| + reg = <0 0x1400e000 0 0x1000>; |
| + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_DITHER0>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; |
| + }; |
| + |
| + ovl_2l2: ovl@14014000 { |
| + compatible = "mediatek,mt8192-disp-ovl-2l"; |
| + reg = <0 0x14014000 0 0x1000>; |
| + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; |
| + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, |
| + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; |
| + }; |
| + |
| + rdma4: rdma@14015000 { |
| + compatible = "mediatek,mt8192-disp-rdma"; |
| + reg = <0 0x14015000 0 0x1000>; |
| + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + clocks = <&mmsys CLK_MM_DISP_RDMA4>; |
| + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; |
| + mediatek,rdma_fifo_size = <2>; |
| + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; |
| + }; |
| + |
| + iommu0: m4u@1401d000 { |
| + compatible = "mediatek,mt8192-m4u"; |
| + reg = <0 0x1401d000 0 0x1000>; |
| + mediatek,larbs = <&larb0 &larb1 &larb2 |
| + &larb4 &larb5 &larb7 |
| + &larb9 &larb11 &larb13 |
| + &larb14 &larb16 &larb17 |
| + &larb18 &larb19 &larb20>; |
| + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&mmsys CLK_MM_SMI_IOMMU>; |
| + clock-names = "bclk"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; |
| + #iommu-cells = <1>; |
| + }; |
| + |
| + imgsys: imgsys@15020000 { |
| + compatible = "mediatek,mt8192-imgsys", "syscon"; |
| + reg = <0 0x15020000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb9: larb@1502e000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1502e000 0 0x1000>; |
| + mediatek,larb-id = <9>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&imgsys CLK_IMG_LARB9>, |
| + <&imgsys CLK_IMG_LARB9>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_ISP>; |
| + }; |
| + |
| + imgsys2: imgsys2@15820000 { |
| + compatible = "mediatek,mt8192-imgsys2", "syscon"; |
| + reg = <0 0x15820000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb11: larb@1582e000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1582e000 0 0x1000>; |
| + mediatek,larb-id = <11>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&imgsys2 CLK_IMG2_LARB11>, |
| + <&imgsys2 CLK_IMG2_LARB11>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_ISP2>; |
| + }; |
| + |
| + vdecsys_soc: vdecsys_soc@1600f000 { |
| + compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; |
| + reg = <0 0x1600f000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb4: larb@1602e000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1602e000 0 0x1000>; |
| + mediatek,larb-id = <4>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, |
| + <&vdecsys CLK_VDEC_SOC_LARB1>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_VDEC2>; |
| + }; |
| + |
| + vdecsys: vdecsys@1602f000 { |
| + compatible = "mediatek,mt8192-vdecsys", "syscon"; |
| + reg = <0 0x1602f000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb5: larb@1600d000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1600d000 0 0x1000>; |
| + mediatek,larb-id = <5>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, |
| + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_VDEC>; |
| + }; |
| + |
| + vencsys: vencsys@17000000 { |
| + compatible = "mediatek,mt8192-vencsys", "syscon"; |
| + reg = <0 0x17000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb7: larb@17010000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x17010000 0 0x1000>; |
| + mediatek,larb-id = <7>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&vencsys CLK_VENC_SET0_LARB>, |
| + <&vencsys CLK_VENC_SET1_VENC>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_VENC>; |
| + }; |
| + |
| + iommu_vpu: m4u@19010000 { |
| + compatible = "mediatek,mt8192-m4u-vpu"; |
| + reg = <0 0x19010000 0 0x1000>; |
| + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&apu_conn CLK_APU_CONN_IOMMU_0>; |
| + clock-names = "bclk"; |
| + /* TODO */ |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_IPE>; |
| + #iommu-cells = <1>; |
| + }; |
| + |
| + apu_conn: apu_conn@19020000 { |
| + compatible = "mediatek,mt8192-apu_conn", "syscon"; |
| + reg = <0 0x19020000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + apu_vcore: apu_vcore@19029000 { |
| + compatible = "mediatek,mt8192-apu_vcore", "syscon"; |
| + reg = <0 0x19029000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + apu0: apu0@19030000 { |
| + compatible = "mediatek,mt8192-apu0", "syscon"; |
| + reg = <0 0x19030000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + apu1: apu1@19031000 { |
| + compatible = "mediatek,mt8192-apu1", "syscon"; |
| + reg = <0 0x19031000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + apu_mdla0: apu_mdla0@19034000 { |
| + compatible = "mediatek,mt8192-apu_mdla0", "syscon"; |
| + reg = <0 0x19034000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + camsys: camsys@1a000000 { |
| + compatible = "mediatek,mt8192-camsys", "syscon"; |
| + reg = <0 0x1a000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb13: larb@1a001000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1a001000 0 0x1000>; |
| + mediatek,larb-id = <13>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&camsys CLK_CAM_CAM>, |
| + <&camsys CLK_CAM_LARB13>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_CAM>; |
| + }; |
| + |
| + larb14: larb@1a002000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1a002000 0 0x1000>; |
| + mediatek,larb-id = <14>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&camsys CLK_CAM_CAM>, |
| + <&camsys CLK_CAM_LARB14>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_CAM>; |
| + }; |
| + |
| + larb16: larb@1a00f000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1a00f000 0 0x1000>; |
| + mediatek,larb-id = <16>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, |
| + <&camsys_rawa CLK_CAM_RAWA_LARBX>; |
| + clock-names = "apb", "smi"; |
| + mediatek,smi-id = <16>; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_CAM_RAWA>; |
| + }; |
| + |
| + larb17: larb@1a010000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1a010000 0 0x1000>; |
| + mediatek,larb-id = <17>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, |
| + <&camsys_rawb CLK_CAM_RAWB_LARBX>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_CAM_RAWB>; |
| + }; |
| + |
| + larb18: larb@1a011000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1a011000 0 0x1000>; |
| + mediatek,larb-id = <18>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, |
| + <&camsys_rawc CLK_CAM_RAWC_CAM>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_CAM_RAWC>; |
| + }; |
| + |
| + camsys_rawa: camsys_rawa@1a04f000 { |
| + compatible = "mediatek,mt8192-camsys_rawa", "syscon"; |
| + reg = <0 0x1a04f000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + camsys_rawb: camsys_rawb@1a06f000 { |
| + compatible = "mediatek,mt8192-camsys_rawb", "syscon"; |
| + reg = <0 0x1a06f000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + camsys_rawc: camsys_rawc@1a08f000 { |
| + compatible = "mediatek,mt8192-camsys_rawc", "syscon"; |
| + reg = <0 0x1a08f000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + ipesys: ipesys@1b000000 { |
| + compatible = "mediatek,mt8192-ipesys", "syscon"; |
| + reg = <0 0x1b000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb20: larb@1b00f000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1b00f000 0 0x1000>; |
| + mediatek,larb-id = <20>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| + <&ipesys CLK_IPE_LARB20>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_IPE>; |
| + }; |
| + |
| + larb19: larb@1b10f000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1b10f000 0 0x1000>; |
| + mediatek,larb-id = <19>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| + <&ipesys CLK_IPE_LARB19>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_IPE>; |
| + }; |
| + |
| + mdpsys: mdpsys@1f000000 { |
| + compatible = "mediatek,mt8192-mdpsys", "syscon"; |
| + reg = <0 0x1f000000 0 0x1000>; |
| + #clock-cells = <1>; |
| + }; |
| + |
| + larb2: larb@1f002000 { |
| + compatible = "mediatek,mt8192-smi-larb"; |
| + reg = <0 0x1f002000 0 0x1000>; |
| + mediatek,larb-id = <2>; |
| + mediatek,smi = <&smi_common>; |
| + clocks = <&mdpsys CLK_MDP_SMI0>, |
| + <&mdpsys CLK_MDP_SMI0>; |
| + clock-names = "apb", "smi"; |
| + power-domains = <&scpsys MT8192_POWER_DOMAIN_MDP>; |
| + }; |
| + |
| + |
| + i2c0: i2c0@11f00000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11f00000 0 0x1000>, |
| + <0 0x10217080 0 0x80>; |
| + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c1: i2c1@11d20000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d20000 0 0x1000>, |
| + <0 0x10217100 0 0x80>; |
| + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c2: i2c2@11d21000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d21000 0 0x1000>, |
| + <0 0x10217180 0 0x180>; |
| + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c3: i2c3@11cb0000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11cb0000 0 0x1000>, |
| + <0 0x10217300 0 0x80>; |
| + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c4: i2c4@11d22000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d22000 0 0x1000>, |
| + <0 0x10217380 0 0x180>; |
| + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c5: i2c5@11e00000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11e00000 0 0x1000>, |
| + <0 0x10217500 0 0x80>; |
| + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c6: i2c6@11f01000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11f01000 0 0x1000>, |
| + <0 0x10217580 0 0x80>; |
| + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c7: i2c7@11d00000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d00000 0 0x1000>, |
| + <0 0x10217600 0 0x180>; |
| + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c8: i2c8@11d01000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d01000 0 0x1000>, |
| + <0 0x10217780 0 0x180>; |
| + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + i2c9: i2c9@11d02000 { |
| + compatible = "mediatek,mt8192-i2c"; |
| + reg = <0 0x11d02000 0 0x1000>, |
| + <0 0x10217900 0 0x180>; |
| + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "main", "dma"; |
| + clock-div = <1>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + |
| + pwm0: pwm@1100e000 { |
| + compatible = "mediatek,mt8183-disp-pwm"; |
| + reg = <0 0x1100e000 0 0x1000>; |
| + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; |
| + #pwm-cells = <2>; |
| + clocks = <&infracfg CLK_INFRA_DISP_PWM>, |
| + <&topckgen CLK_TOP_DISP_PWM_SEL>; |
| + clock-names = "main", "mm"; |
| + }; |
| + |
| + mipi_tx0: mipi-dphy@11e50000 { |
| + compatible = "mediatek,mt8183-mipi-tx"; |
| + reg = <0 0x11e50000 0 0x1000>; |
| + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; |
| + clock-names = "ref_clk"; |
| + #clock-cells = <0>; |
| + #phy-cells = <0>; |
| + clock-output-names = "mipi_tx0_pll"; |
| + /*nvmem-cells = <&mipi_tx_calibration>;*/ |
| + /*nvmem-cell-names = "calibration-data";*/ |
| + }; |
| + |
| + dsi0: dsi@14010000 { |
| + compatible = "mediatek,mt8183-dsi"; |
| + reg = <0 0x14010000 0 0x1000>; |
| + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; |
| + mediatek,syscon-dsi = <&mmsys 0x140>; |
| + clocks = <&mmsys CLK_MM_DSI0>, |
| + <&mmsys CLK_MM_DSI_DSI0>, |
| + <&mipi_tx0>; |
| + clock-names = "engine", "digital", "hs"; |
| + phys = <&mipi_tx0>; |
| + phy-names = "dphy"; |
| + }; |
| + |
| + dpi0: dpi@14016000 { |
| + compatible = "mediatek,mt8183-dpi"; |
| + reg = <0 0x14016000 0 0x1000>; |
| + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&mmsys CLK_MM_DISP_DPI0>, |
| + <&mmsys CLK_MM_DPI_DPI0>, |
| + <&apmixedsys CLK_APMIXED_TVDPLL>; |
| + clock-names = "pixel", "engine", "pll"; |
| + }; |
| + |
| + ssusb: usb@11201000 { |
| + compatible = "mediatek,mt8192-mtu3", "mediatek,mtu3"; |
| + reg = <0 0x11201000 0 0x3000>, |
| + <0 0x11203e00 0 0x0100>; |
| + reg-names = "mac", "ippc"; |
| + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>; |
| + phys = <&u2port0 PHY_TYPE_USB2>, |
| + <&u3port0 PHY_TYPE_USB3>; |
| + clocks = <&infracfg CLK_INFRA_SSUSB>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>; |
| + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; |
| + mediatek,syscon-wakeup = <&pericfg 0x420 3>; |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + ranges; |
| + |
| + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, |
| + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; |
| + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, |
| + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; |
| + |
| + usb_host0: xhci@11200000 { |
| + compatible = "mediatek,mt6873-xhci", |
| + "mediatek,mtk-xhci"; |
| + reg = <0 0x11200000 0 0x1000>; |
| + reg-names = "mac"; |
| + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, |
| + <&pio 211 IRQ_TYPE_LEVEL_LOW>; |
| + clocks = <&infracfg CLK_INFRA_SSUSB>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| + <&infracfg CLK_INFRA_SSUSB_XHCI>; |
| + clock-names = "sys_ck", |
| + "xhci_ck", "ref_ck", |
| + "mcu_ck", "dma_ck"; |
| + }; |
| + }; |
| + |
| + u3phy0: usb-phy@11e40000 { |
| + compatible = "mediatek,generic-tphy-v2"; |
| + #address-cells = <2>; |
| + #size-cells = <2>; |
| + ranges; |
| + status = "okay"; |
| + |
| + u2port0: usb-phy@11e40000 { |
| + reg = <0 0x11e40000 0 0x700>; |
| + clocks = <&clk26m>; |
| + clock-names = "ref"; |
| + #phy-cells = <1>; |
| + status = "okay"; |
| + }; |
| + |
| + u3port0: usb-phy@11e40700 { |
| + reg = <0 0x11e40700 0 0x900>; |
| + clocks = <&clk26m>; |
| + clock-names = "ref"; |
| + #phy-cells = <1>; |
| + status = "okay"; |
| + }; |
| + }; |
| + |
| + spi1: spi1@11010000 { |
| + compatible = "mediatek,mt6765-spi"; |
| + reg = <0 0x11010000 0 0x100>; |
| + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| + <&topckgen CLK_TOP_SPI_SEL>, |
| + <&infracfg CLK_INFRA_SPI1>; |
| + clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| + status = "disabled"; |
| + }; |
| + |
| + spi5: spi5@11019000 { |
| + compatible = "mediatek,mt6765-spi"; |
| + reg = <0 0x11019000 0 0x100>; |
| + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; |
| + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| + <&topckgen CLK_TOP_SPI_SEL>, |
| + <&infracfg CLK_INFRA_SPI5>; |
| + clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| + status = "disabled"; |
| + }; |
| + |
| + pcie: pcie@11230000 { |
| + compatible = "mediatek,mt8192-pcie"; |
| + device_type = "pci"; |
| + reg = <0 0x11230000 0 0x2000>; |
| + reg-names = "port0"; |
| + #address-cells = <3>; |
| + #size-cells = <2>; |
| + clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>, |
| + <&infracfg CLK_INFRA_PCIE_TL_96M>, |
| + <&infracfg CLK_INFRA_PCIE_TL_32K>, |
| + <&infracfg CLK_INFRA_PCIE_PERI_26M>, |
| + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>, |
| + <&infracfg CLK_INFRA_PCIE_PL_P_250M>; |
| + clock-names = "sys_ck0", "sys_ck1", "sys_ck2", |
| + "sys_ck3", "axi_ck0", "pipe_ck0"; |
| + resets = <&infracfg |
| + MT8192_INFRACFG_AO_PEXTP_PHY_SW_RST>; |
| + reset-names = "phy_rst"; |
| + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; |
| + bus-range = <0x00 0xff>; |
| + ranges = <0x82000000 0 0x12000000 |
| + 0x0 0x12000000 0 0x1000000>; |
| + status = "okay"; |
| + |
| + pcie0: pcie@0,0 { |
| + device_type = "pci"; |
| + reg = <0x0000 0 0 0 0>; |
| + #address-cells = <3>; |
| + #size-cells = <2>; |
| + ranges; |
| + num-lanes = <1>; |
| + #interrupt-cells = <1>; |
| + interrupt-map-mask = <0 0 0 7>; |
| + interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| + <0 0 0 2 &pcie_intc0 1>, |
| + <0 0 0 3 &pcie_intc0 2>, |
| + <0 0 0 4 &pcie_intc0 3>; |
| + pcie_intc0: interrupt-controller { |
| + interrupt-controller; |
| + #address-cells = <0>; |
| + #interrupt-cells = <1>; |
| + }; |
| + }; |
| + }; |
| + |
| + nor_flash: spi@11234000 { |
| + compatible = "mediatek,mt8173-nor"; |
| + reg = <0 0x11234000 0 0xe0>; |
| + clocks = <&clk26m>, <&clk26m>; |
| + clock-names = "spi", "sf"; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + }; |
| + }; |
| +}; |
| diff --git a/chromeos/config/arm64/chromiumos-arm64.flavour.config b/chromeos/config/arm64/chromiumos-arm64.flavour.config |
| index e82405fdadcde92b0a4e7e05340cf818adcdeaa0..89846f241df0c0753a7953e16144d96395b4833c 100644 |
| --- a/chromeos/config/arm64/chromiumos-arm64.flavour.config |
| +++ b/chromeos/config/arm64/chromiumos-arm64.flavour.config |
| @@ -32,6 +32,34 @@ CONFIG_COMMON_CLK_MT8183_MFGCFG=y |
| CONFIG_COMMON_CLK_MT8183_MMSYS=y |
| CONFIG_COMMON_CLK_MT8183_VDECSYS=y |
| CONFIG_COMMON_CLK_MT8183_VENCSYS=y |
| +CONFIG_COMMON_CLK_MT8192_APU0=y |
| +CONFIG_COMMON_CLK_MT8192_APU1=y |
| +CONFIG_COMMON_CLK_MT8192_APU_CONN=y |
| +CONFIG_COMMON_CLK_MT8192_APU_MDLA0=y |
| +CONFIG_COMMON_CLK_MT8192_APU_VCORE=y |
| +CONFIG_COMMON_CLK_MT8192_AUDSYS=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWB=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWC=y |
| +CONFIG_COMMON_CLK_MT8192_IMGSYS=y |
| +CONFIG_COMMON_CLK_MT8192_IMGSYS2=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_C=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_E=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_N=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_S=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_W=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_WS=y |
| +CONFIG_COMMON_CLK_MT8192_IPESYS=y |
| +CONFIG_COMMON_CLK_MT8192_MDPSYS=y |
| +CONFIG_COMMON_CLK_MT8192_MFGCFG=y |
| +CONFIG_COMMON_CLK_MT8192_MMSYS=y |
| +CONFIG_COMMON_CLK_MT8192_MSDC=y |
| +CONFIG_COMMON_CLK_MT8192_MSDC_TOP=y |
| +CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y |
| +CONFIG_COMMON_CLK_MT8192_VDECSYS=y |
| +CONFIG_COMMON_CLK_MT8192_VDECSYS_SOC=y |
| +CONFIG_COMMON_CLK_MT8192_VENCSYS=y |
| CONFIG_COMMON_CLK_PALMAS=y |
| CONFIG_COMMON_CLK_QCOM=y |
| CONFIG_COMMON_CLK_RK808=y |
| @@ -48,6 +76,7 @@ CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y |
| CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y |
| CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y |
| CONFIG_DRM_PANEL_VISIONOX_RM69299=y |
| +CONFIG_DRM_PANEL_TRULY_TD4330_VDO=y |
| CONFIG_DRM_PARADE_PS8640=y |
| CONFIG_DRM_TI_SN65DSI86=y |
| CONFIG_DRM_VIRTIO_GPU=y |
| @@ -101,6 +130,7 @@ CONFIG_MWIFIEX_SDIO=m |
| CONFIG_PCI=y |
| CONFIG_PCIEASPM_POWERSAVE=y |
| CONFIG_PCIEPORTBUS=y |
| +CONFIG_PCIE_MEDIATEK=y |
| CONFIG_PHY_MTK_TPHY=y |
| CONFIG_PHY_QCOM_QMP=y |
| CONFIG_PHY_QCOM_QUSB2=y |
| @@ -147,6 +177,8 @@ CONFIG_QRTR_SMD=y |
| CONFIG_QRTR_TUN=y |
| CONFIG_REGULATOR_MAX8973=y |
| CONFIG_REGULATOR_MT6311=y |
| +CONFIG_REGULATOR_MT6315=y |
| +CONFIG_REGULATOR_MT6359=y |
| CONFIG_REGULATOR_MT6397=y |
| CONFIG_REGULATOR_PALMAS=y |
| CONFIG_REGULATOR_QCOM_RPMH=y |
| @@ -221,6 +253,7 @@ CONFIG_SPI_QCOM_GENI=y |
| CONFIG_SPI_QCOM_QSPI=y |
| CONFIG_SPI_ROCKCHIP=y |
| CONFIG_SPMI=y |
| +CONFIG_SPMI_MTK_PMIF=y |
| CONFIG_STMMAC_ETH=m |
| CONFIG_TOUCHSCREEN_MELFAS_MIP4=y |
| CONFIG_TYPEC=m |
| diff --git a/chromeos/config/arm64/chromiumos-mediatek.flavour.config b/chromeos/config/arm64/chromiumos-mediatek.flavour.config |
| index c34fc68897644de80b40cce162a42fcfd736a6da..8197b809c109671554f85f7a70415c44a871fefb 100644 |
| --- a/chromeos/config/arm64/chromiumos-mediatek.flavour.config |
| +++ b/chromeos/config/arm64/chromiumos-mediatek.flavour.config |
| @@ -23,6 +23,34 @@ CONFIG_COMMON_CLK_MT8183_MFGCFG=y |
| CONFIG_COMMON_CLK_MT8183_MMSYS=y |
| CONFIG_COMMON_CLK_MT8183_VDECSYS=y |
| CONFIG_COMMON_CLK_MT8183_VENCSYS=y |
| +CONFIG_COMMON_CLK_MT8192_APU0=y |
| +CONFIG_COMMON_CLK_MT8192_APU1=y |
| +CONFIG_COMMON_CLK_MT8192_APU_CONN=y |
| +CONFIG_COMMON_CLK_MT8192_APU_MDLA0=y |
| +CONFIG_COMMON_CLK_MT8192_APU_VCORE=y |
| +CONFIG_COMMON_CLK_MT8192_AUDSYS=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWB=y |
| +CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWC=y |
| +CONFIG_COMMON_CLK_MT8192_IMGSYS=y |
| +CONFIG_COMMON_CLK_MT8192_IMGSYS2=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_C=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_E=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_N=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_S=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_W=y |
| +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_WS=y |
| +CONFIG_COMMON_CLK_MT8192_IPESYS=y |
| +CONFIG_COMMON_CLK_MT8192_MDPSYS=y |
| +CONFIG_COMMON_CLK_MT8192_MFGCFG=y |
| +CONFIG_COMMON_CLK_MT8192_MMSYS=y |
| +CONFIG_COMMON_CLK_MT8192_MSDC=y |
| +CONFIG_COMMON_CLK_MT8192_MSDC_TOP=y |
| +CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y |
| +CONFIG_COMMON_CLK_MT8192_VDECSYS=y |
| +CONFIG_COMMON_CLK_MT8192_VDECSYS_SOC=y |
| +CONFIG_COMMON_CLK_MT8192_VENCSYS=y |
| CONFIG_CROS_EC_RPMSG=m |
| CONFIG_DEVFREQ_GOV_PASSIVE=y |
| CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y |
| @@ -32,6 +60,7 @@ CONFIG_DRM_MEDIATEK=y |
| CONFIG_DRM_MEDIATEK_HDMI=y |
| CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y |
| CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y |
| +CONFIG_DRM_PANEL_TRULY_TD4330_VDO=y |
| CONFIG_DRM_PARADE_PS8640=y |
| CONFIG_EEPROM_AT24=y |
| # CONFIG_EFI is not set |
| @@ -44,6 +73,7 @@ CONFIG_I2C_MT65XX=y |
| CONFIG_MALI_VALHALL=y |
| CONFIG_MALI_VALHALL_DMA_FENCE=y |
| CONFIG_MALI_VALHALL_EXPERT=y |
| +CONFIG_MALI_VALHALL_PLATFORM_NAME="mt8192" |
| CONFIG_MEDIATEK_MT6577_AUXADC=y |
| CONFIG_MEDIATEK_WATCHDOG=y |
| CONFIG_MEDIA_CONTROLLER=y |
| @@ -56,6 +86,7 @@ CONFIG_MTK_PMIC_WRAP=y |
| CONFIG_MTK_SCP=m |
| CONFIG_MTK_SVS=y |
| CONFIG_PCI=y |
| +CONFIG_PCIE_MEDIATEK=y |
| CONFIG_PHY_MTK_TPHY=y |
| # CONFIG_PINCTRL_MT2712 is not set |
| # CONFIG_PINCTRL_MT7622 is not set |
| @@ -63,6 +94,8 @@ CONFIG_PM_DEVFREQ=y |
| CONFIG_POWER_AVS=y |
| CONFIG_PWM_MTK_DISP=y |
| CONFIG_RAS=y |
| +CONFIG_REGULATOR_MT6315=y |
| +CONFIG_REGULATOR_MT6359=y |
| CONFIG_REGULATOR_MT6397=y |
| CONFIG_REMOTEPROC=y |
| CONFIG_RTC_DRV_MT6397=y |
| @@ -88,6 +121,8 @@ CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=y |
| CONFIG_SPI_GPIO=y |
| CONFIG_SPI_MT65XX=y |
| CONFIG_SPI_MTK_QUADSPI=y |
| +CONFIG_SPMI=y |
| +CONFIG_SPMI_MTK_PMIF=y |
| CONFIG_STAGING_MEDIA=y |
| CONFIG_TCG_CR50_I2C=y |
| CONFIG_TMPFS=y |
| diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c |
| index 6fa92e83a99fbe0fc19716025442457967dd0491..e833b2b9ada4a597419b795b2a03a94e729e0c96 100644 |
| --- a/drivers/clk/clk.c |
| +++ b/drivers/clk/clk.c |
| @@ -1275,7 +1275,7 @@ static int clk_disable_unused(void) |
| { |
| struct clk_core *core; |
| |
| - if (clk_ignore_unused) { |
| + if (clk_ignore_unused || 1) { |
| pr_warn("clk: Not disabling unused clocks\n"); |
| return 0; |
| } |
| diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig |
| index 40b45420d4844a1067bace0c58567fcd4fd7affc..1d422238b6046a93f816524464ac5150b427d5f2 100644 |
| --- a/drivers/clk/mediatek/Kconfig |
| +++ b/drivers/clk/mediatek/Kconfig |
| @@ -355,6 +355,182 @@ config COMMON_CLK_MT8183_VENCSYS |
| help |
| This driver supports MediaTek MT8183 vencsys clocks. |
| |
| +config COMMON_CLK_MT8192 |
| + bool "Clock driver for MediaTek MT8192" |
| + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST |
| + select COMMON_CLK_MEDIATEK |
| + default ARCH_MEDIATEK && ARM64 |
| + help |
| + This driver supports MediaTek MT8192 basic clocks. |
| + |
| +config COMMON_CLK_MT8192_APU0 |
| + bool "Clock driver for MediaTek MT8192 apu0" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 apu0 clocks. |
| + |
| +config COMMON_CLK_MT8192_APU1 |
| + bool "Clock driver for MediaTek MT8192 apu1" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 apu1 clocks. |
| + |
| +config COMMON_CLK_MT8192_APU_VCORE |
| + bool "Clock driver for MediaTek MT8192 apu_vcore" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 apu_vcore clocks. |
| + |
| +config COMMON_CLK_MT8192_APU_CONN |
| + bool "Clock driver for MediaTek MT8192 apu_conn" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 apu_conn clocks. |
| + |
| +config COMMON_CLK_MT8192_APU_MDLA0 |
| + bool "Clock driver for MediaTek MT8192 apu_mdla0" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 apu_mdla0 clocks. |
| + |
| +config COMMON_CLK_MT8192_AUDSYS |
| + bool "Clock driver for MediaTek MT8192 audsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 audsys clocks. |
| + |
| +config COMMON_CLK_MT8192_CAMSYS |
| + bool "Clock driver for MediaTek MT8192 camsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 camsys clocks. |
| + |
| +config COMMON_CLK_MT8192_CAMSYS_RAWA |
| + bool "Clock driver for MediaTek MT8192 camsys_rawa" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 camsys_rawa clocks. |
| + |
| +config COMMON_CLK_MT8192_CAMSYS_RAWB |
| + bool "Clock driver for MediaTek MT8192 camsys_rawb" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 camsys_rawb clocks. |
| + |
| +config COMMON_CLK_MT8192_CAMSYS_RAWC |
| + bool "Clock driver for MediaTek MT8192 camsys_rawc" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 camsys_rawc clocks. |
| + |
| +config COMMON_CLK_MT8192_IMGSYS |
| + bool "Clock driver for MediaTek MT8192 imgsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imgsys clocks. |
| + |
| +config COMMON_CLK_MT8192_IMGSYS2 |
| + bool "Clock driver for MediaTek MT8192 imgsys2" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imgsys2 clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_C |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_c" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_c clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_E |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_e" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_e clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_N |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_n" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_n clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_S |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_s" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_s clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_W |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_w" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_w clocks. |
| + |
| +config COMMON_CLK_MT8192_IMP_IIC_WRAP_WS |
| + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_ws" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 imp_iic_wrap_ws clocks. |
| + |
| +config COMMON_CLK_MT8192_IPESYS |
| + bool "Clock driver for MediaTek MT8192 ipesys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 ipesys clocks. |
| + |
| +config COMMON_CLK_MT8192_MDPSYS |
| + bool "Clock driver for MediaTek MT8192 mdpsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 mdpsys clocks. |
| + |
| +config COMMON_CLK_MT8192_MFGCFG |
| + bool "Clock driver for MediaTek MT8192 mfgcfg" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 mfgcfg clocks. |
| + |
| +config COMMON_CLK_MT8192_MMSYS |
| + bool "Clock driver for MediaTek MT8192 mmsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 mmsys clocks. |
| + |
| +config COMMON_CLK_MT8192_MSDC_TOP |
| + bool "Clock driver for MediaTek MT8192 msdc_top" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 msdc_top clocks. |
| + |
| +config COMMON_CLK_MT8192_MSDC |
| + bool "Clock driver for MediaTek MT8192 msdc" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 msdc clocks. |
| + |
| +config COMMON_CLK_MT8192_SCP_ADSP |
| + bool "Clock driver for MediaTek MT8192 scp_adsp" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 scp_adsp clocks. |
| + |
| +config COMMON_CLK_MT8192_VDECSYS |
| + bool "Clock driver for MediaTek MT8192 vdecsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 vdecsys clocks. |
| + |
| +config COMMON_CLK_MT8192_VDECSYS_SOC |
| + bool "Clock driver for MediaTek MT8192 vdecsys_soc" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 vdecsys_soc clocks. |
| + |
| +config COMMON_CLK_MT8192_VENCSYS |
| + bool "Clock driver for MediaTek MT8192 vencsys" |
| + depends on COMMON_CLK_MT8192 |
| + help |
| + This driver supports MediaTek MT8192 vencsys clocks. |
| + |
| config COMMON_CLK_MT8516 |
| bool "Clock driver for MediaTek MT8516" |
| depends on ARCH_MEDIATEK || COMPILE_TEST |
| diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile |
| index bb05369420755f04695c3181716f4863da793672..26733c3fa0d108cc58714f0fd82869b04b710183 100644 |
| --- a/drivers/clk/mediatek/Makefile |
| +++ b/drivers/clk/mediatek/Makefile |
| @@ -54,5 +54,34 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o |
| obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o |
| obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o |
| obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o clkdbg.o clkdbg-mt8192.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_APU0) += clk-mt8192-apu0.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_APU1) += clk-mt8192-apu1.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_APU_VCORE) += clk-mt8192-apu_vcore.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_APU_CONN) += clk-mt8192-apu_conn.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_APU_MDLA0) += clk-mt8192-apu_mdla0.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA) += clk-mt8192-cam_rawa.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWB) += clk-mt8192-cam_rawb.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWC) += clk-mt8192-cam_rawc.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS2) += clk-mt8192-img2.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_C) += clk-mt8192-imp_iic_wrap_c.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_E) += clk-mt8192-imp_iic_wrap_e.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_N) += clk-mt8192-imp_iic_wrap_n.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_S) += clk-mt8192-imp_iic_wrap_s.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_W) += clk-mt8192-imp_iic_wrap_w.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_WS) += clk-mt8192-imp_iic_wrap_ws.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_IPESYS) += clk-mt8192-ipe.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_MDPSYS) += clk-mt8192-mdp.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_MSDC_TOP) += clk-mt8192-msdc_top.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS_SOC) += clk-mt8192-vdec_soc.o |
| +obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o |
| obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o |
| obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o |
| diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c |
| index 720c696b506d59b5cd0ed34d3b8f29488ff382b0..c6a1ce2495fc404a1c6f38e922e51c524f76725a 100644 |
| --- a/drivers/clk/mediatek/clk-mt8183-mm.c |
| +++ b/drivers/clk/mediatek/clk-mt8183-mm.c |
| @@ -31,7 +31,7 @@ static const struct mtk_gate_regs mm1_cg_regs = { |
| GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \ |
| &mtk_clk_gate_ops_setclr) |
| |
| -static const struct mtk_gate mm_clks[] = { |
| +static const struct mtk_gate mt8183_mm_clks[] = { |
| /* MM0 */ |
| GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), |
| GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), |
| @@ -82,29 +82,47 @@ static const struct mtk_gate mm_clks[] = { |
| GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13), |
| }; |
| |
| +struct clk_mt8183_mm_driver_data { |
| + const struct mtk_gate *gates_clk; |
| + int gates_num; |
| +}; |
| + |
| +static const struct clk_mt8183_mm_driver_data mt8183_mmsys_driver_data = { |
| + .gates_clk = mt8183_mm_clks, |
| + .gates_num = ARRAY_SIZE(mt8183_mm_clks), |
| +}; |
| + |
| static int clk_mt8183_mm_probe(struct platform_device *pdev) |
| { |
| + struct device *dev = &pdev->dev; |
| + struct device_node *node = dev->parent->of_node; |
| + const struct clk_mt8183_mm_driver_data *data; |
| struct clk_onecell_data *clk_data; |
| - struct device_node *node = pdev->dev.of_node; |
| + int ret; |
| |
| clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); |
| + if (!clk_data) |
| + return -ENOMEM; |
| |
| - mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), |
| - clk_data); |
| + data = &mt8183_mmsys_driver_data; |
| |
| - return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| + ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, |
| + clk_data); |
| + if (ret) |
| + return ret; |
| + |
| + ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| + if (ret) |
| + return ret; |
| + |
| + return 0; |
| } |
| |
| -static const struct of_device_id of_match_clk_mt8183_mm[] = { |
| - { .compatible = "mediatek,mt8183-mmsys", }, |
| - {} |
| -}; |
| |
| static struct platform_driver clk_mt8183_mm_drv = { |
| .probe = clk_mt8183_mm_probe, |
| .driver = { |
| .name = "clk-mt8183-mm", |
| - .of_match_table = of_match_clk_mt8183_mm, |
| }, |
| }; |
| |
| diff --git a/drivers/clk/mediatek/clk-mt8192-apu0.c b/drivers/clk/mediatek/clk-mt8192-apu0.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..154dd6b480391deb057445ced3d6d93f6e0257bc |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-apu0.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs apu0_cg_regs = { |
| + .set_ofs = 0x104, |
| + .clr_ofs = 0x108, |
| + .sta_ofs = 0x100, |
| +}; |
| + |
| +#define GATE_APU0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apu0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate apu0_clks[] = { |
| + GATE_APU0(CLK_APU0_APU, "apu0_apu", "dsp1_sel", 0), |
| + GATE_APU0(CLK_APU0_AXI_M, "apu0_axi_m", "dsp1_sel", 1), |
| + GATE_APU0(CLK_APU0_JTAG, "apu0_jtag", "dsp1_sel", 2), |
| +}; |
| + |
| +static int clk_mt8192_apu0_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APU0_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, apu0_clks, ARRAY_SIZE(apu0_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_apu0[] = { |
| + { .compatible = "mediatek,mt8192-apu0", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_apu0_drv = { |
| + .probe = clk_mt8192_apu0_probe, |
| + .driver = { |
| + .name = "clk-mt8192-apu0", |
| + .of_match_table = of_match_clk_mt8192_apu0, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_apu0_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-apu1.c b/drivers/clk/mediatek/clk-mt8192-apu1.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..7dbd03025290acd204bc3ce027da6a33554ac078 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-apu1.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs apu1_cg_regs = { |
| + .set_ofs = 0x104, |
| + .clr_ofs = 0x108, |
| + .sta_ofs = 0x100, |
| +}; |
| + |
| +#define GATE_APU1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apu1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate apu1_clks[] = { |
| + GATE_APU1(CLK_APU1_APU, "apu1_apu", "dsp2_sel", 0), |
| + GATE_APU1(CLK_APU1_AXI_M, "apu1_axi_m", "dsp2_sel", 1), |
| + GATE_APU1(CLK_APU1_JTAG, "apu1_jtag", "dsp2_sel", 2), |
| +}; |
| + |
| +static int clk_mt8192_apu1_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APU1_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, apu1_clks, ARRAY_SIZE(apu1_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_apu1[] = { |
| + { .compatible = "mediatek,mt8192-apu1", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_apu1_drv = { |
| + .probe = clk_mt8192_apu1_probe, |
| + .driver = { |
| + .name = "clk-mt8192-apu1", |
| + .of_match_table = of_match_clk_mt8192_apu1, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_apu1_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-apu_conn.c b/drivers/clk/mediatek/clk-mt8192-apu_conn.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..e1e2279a4503f7b5dcfb685dee7fea773ed0954d |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-apu_conn.c |
| @@ -0,0 +1,71 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs apu_conn_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_APU_CONN(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apu_conn_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate apu_conn_clks[] = { |
| + GATE_APU_CONN(CLK_APU_CONN_APU, "apu_conn_apu", "dsp_sel", 0), |
| + GATE_APU_CONN(CLK_APU_CONN_AHB, "apu_conn_ahb", "dsp_sel", 1), |
| + GATE_APU_CONN(CLK_APU_CONN_AXI, "apu_conn_axi", "dsp_sel", 2), |
| + GATE_APU_CONN(CLK_APU_CONN_ISP, "apu_conn_isp", "dsp_sel", 3), |
| + GATE_APU_CONN(CLK_APU_CONN_CAM_ADL, "apu_conn_cam_adl", "dsp_sel", 4), |
| + GATE_APU_CONN(CLK_APU_CONN_IMG_ADL, "apu_conn_img_adl", "dsp_sel", 5), |
| + GATE_APU_CONN(CLK_APU_CONN_EMI_26M, "apu_conn_emi_26m", "dsp_sel", 6), |
| + GATE_APU_CONN(CLK_APU_CONN_VPU_UDI, "apu_conn_vpu_udi", "dsp_sel", 7), |
| + GATE_APU_CONN(CLK_APU_CONN_EDMA_0, "apu_conn_edma_0", "dsp_sel", 8), |
| + GATE_APU_CONN(CLK_APU_CONN_EDMA_1, "apu_conn_edma_1", "dsp_sel", 9), |
| + GATE_APU_CONN(CLK_APU_CONN_EDMAL_0, "apu_conn_edmal_0", "dsp_sel", 10), |
| + GATE_APU_CONN(CLK_APU_CONN_EDMAL_1, "apu_conn_edmal_1", "dsp_sel", 11), |
| + GATE_APU_CONN(CLK_APU_CONN_MNOC, "apu_conn_mnoc", "dsp_sel", 12), |
| + GATE_APU_CONN(CLK_APU_CONN_TCM, "apu_conn_tcm", "dsp_sel", 13), |
| + GATE_APU_CONN(CLK_APU_CONN_MD32, "apu_conn_md32", "dsp_sel", 14), |
| + GATE_APU_CONN(CLK_APU_CONN_IOMMU_0, "apu_conn_iommu_0", "dsp_sel", 15), |
| + GATE_APU_CONN(CLK_APU_CONN_IOMMU_1, "apu_conn_iommu_1", "dsp_sel", 16), |
| + GATE_APU_CONN(CLK_APU_CONN_MD32_32K, "apu_conn_md32_32k", "dsp_sel", 17), |
| +}; |
| + |
| +static int clk_mt8192_apu_conn_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APU_CONN_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, apu_conn_clks, ARRAY_SIZE(apu_conn_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_apu_conn[] = { |
| + { .compatible = "mediatek,mt8192-apu_conn", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_apu_conn_drv = { |
| + .probe = clk_mt8192_apu_conn_probe, |
| + .driver = { |
| + .name = "clk-mt8192-apu_conn", |
| + .of_match_table = of_match_clk_mt8192_apu_conn, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_apu_conn_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-apu_mdla0.c b/drivers/clk/mediatek/clk-mt8192-apu_mdla0.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..b50f76b9f734a3a91e9af70aea6ec8db02c2c45b |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-apu_mdla0.c |
| @@ -0,0 +1,68 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs apu_mdla0_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_APU_MDLA0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apu_mdla0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate apu_mdla0_clks[] = { |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG0, "apu_mdla0_cg0", "dsp5_sel", 0), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG1, "apu_mdla0_cg1", "dsp5_sel", 1), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG2, "apu_mdla0_cg2", "dsp5_sel", 2), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG3, "apu_mdla0_cg3", "dsp5_sel", 3), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG4, "apu_mdla0_cg4", "dsp5_sel", 4), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG5, "apu_mdla0_cg5", "dsp5_sel", 5), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG6, "apu_mdla0_cg6", "dsp5_sel", 6), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG7, "apu_mdla0_cg7", "dsp5_sel", 7), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG8, "apu_mdla0_cg8", "dsp5_sel", 8), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG9, "apu_mdla0_cg9", "dsp5_sel", 9), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG10, "apu_mdla0_cg10", "dsp5_sel", 10), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG11, "apu_mdla0_cg11", "dsp5_sel", 11), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_CG12, "apu_mdla0_cg12", "dsp5_sel", 12), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_APB, "apu_mdla0_apb", "dsp5_sel", 13), |
| + GATE_APU_MDLA0(CLK_APU_MDLA0_AXI_M, "apu_mdla0_axi_m", "dsp5_sel", 14), |
| +}; |
| + |
| +static int clk_mt8192_apu_mdla0_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APU_MDLA0_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, apu_mdla0_clks, ARRAY_SIZE(apu_mdla0_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_apu_mdla0[] = { |
| + { .compatible = "mediatek,mt8192-apu_mdla0", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_apu_mdla0_drv = { |
| + .probe = clk_mt8192_apu_mdla0_probe, |
| + .driver = { |
| + .name = "clk-mt8192-apu_mdla0", |
| + .of_match_table = of_match_clk_mt8192_apu_mdla0, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_apu_mdla0_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-apu_vcore.c b/drivers/clk/mediatek/clk-mt8192-apu_vcore.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..124fbabf08b44c8180717b60d91908683d14b9a6 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-apu_vcore.c |
| @@ -0,0 +1,57 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs apu_vcore_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_APU_VCORE(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apu_vcore_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate apu_vcore_clks[] = { |
| + GATE_APU_VCORE(CLK_APU_VCORE_AHB, "apu_vcore_ahb", "ipu_if_sel", 0), |
| + GATE_APU_VCORE(CLK_APU_VCORE_AXI, "apu_vcore_axi", "ipu_if_sel", 1), |
| + GATE_APU_VCORE(CLK_APU_VCORE_ADL, "apu_vcore_adl", "ipu_if_sel", 2), |
| + GATE_APU_VCORE(CLK_APU_VCORE_QOS, "apu_vcore_qos", "ipu_if_sel", 3), |
| +}; |
| + |
| +static int clk_mt8192_apu_vcore_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APU_VCORE_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, apu_vcore_clks, ARRAY_SIZE(apu_vcore_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_apu_vcore[] = { |
| + { .compatible = "mediatek,mt8192-apu_vcore", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_apu_vcore_drv = { |
| + .probe = clk_mt8192_apu_vcore_probe, |
| + .driver = { |
| + .name = "clk-mt8192-apu_vcore", |
| + .of_match_table = of_match_clk_mt8192_apu_vcore, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_apu_vcore_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..d45e9e8a6f3271be8a8f84095dbb8a3e8528bd55 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-aud.c |
| @@ -0,0 +1,108 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs aud0_cg_regs = { |
| + .set_ofs = 0x0, |
| + .clr_ofs = 0x0, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +static const struct mtk_gate_regs aud1_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x4, |
| + .sta_ofs = 0x4, |
| +}; |
| + |
| +static const struct mtk_gate_regs aud2_cg_regs = { |
| + .set_ofs = 0x8, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x8, |
| +}; |
| + |
| +#define GATE_AUD0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr) |
| + |
| +#define GATE_AUD1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr) |
| + |
| +#define GATE_AUD2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr) |
| + |
| +static const struct mtk_gate aud_clks[] = { |
| + /* AUD0 */ |
| + GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2), |
| + GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8), |
| + GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9), |
| + GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18), |
| + GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19), |
| + GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20), |
| + GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24), |
| + GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25), |
| + GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26), |
| + GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27), |
| + GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28), |
| + /* AUD1 */ |
| + GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4), |
| + GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5), |
| + GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6), |
| + GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7), |
| + GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12), |
| + GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13), |
| + GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14), |
| + GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15), |
| + GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16), |
| + GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17), |
| + GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20), |
| + GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21), |
| + GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28), |
| + GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29), |
| + GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30), |
| + GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31), |
| + /* AUD2 */ |
| + GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0), |
| + GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1), |
| + GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2), |
| + GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3), |
| + GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), |
| +}; |
| + |
| +static int clk_mt8192_aud_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_aud[] = { |
| + { .compatible = "mediatek,mt8192-audsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_aud_drv = { |
| + .probe = clk_mt8192_aud_probe, |
| + .driver = { |
| + .name = "clk-mt8192-aud", |
| + .of_match_table = of_match_clk_mt8192_aud, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_aud_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..309625bf1b949f88650c771efbf31f57316db06b |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-cam.c |
| @@ -0,0 +1,69 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs cam_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_CAM(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate cam_clks[] = { |
| + GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0), |
| + GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1), |
| + GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 2), |
| + GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6), |
| + GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7), |
| + GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8), |
| + GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9), |
| + GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10), |
| + GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11), |
| + GATE_CAM(CLK_CAM_CAMSV3, "cam_camsv3", "cam_sel", 12), |
| + GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "cam_sel", 13), |
| + GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "cam_sel", 14), |
| + GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "cam_sel", 15), |
| + GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 17), |
| + GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "cam_sel", 18), |
| + GATE_CAM(CLK_CAM_CAM2MM_GALS, "cam2mm_gals", "cam_sel", 19), |
| +}; |
| + |
| +static int clk_mt8192_cam_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_cam[] = { |
| + { .compatible = "mediatek,mt8192-camsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_cam_drv = { |
| + .probe = clk_mt8192_cam_probe, |
| + .driver = { |
| + .name = "clk-mt8192-cam", |
| + .of_match_table = of_match_clk_mt8192_cam, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_cam_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-cam_rawa.c b/drivers/clk/mediatek/clk-mt8192-cam_rawa.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..cb1911aed817fd1c3a4f3b72c6c3dff9807d46d6 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-cam_rawa.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs cam_rawa_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_CAM_RAWA(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &cam_rawa_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate cam_rawa_clks[] = { |
| + GATE_CAM_RAWA(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0), |
| + GATE_CAM_RAWA(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1), |
| + GATE_CAM_RAWA(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2), |
| +}; |
| + |
| +static int clk_mt8192_cam_rawa_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_CAM_RAWA_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, cam_rawa_clks, ARRAY_SIZE(cam_rawa_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_cam_rawa[] = { |
| + { .compatible = "mediatek,mt8192-camsys_rawa", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_cam_rawa_drv = { |
| + .probe = clk_mt8192_cam_rawa_probe, |
| + .driver = { |
| + .name = "clk-mt8192-cam_rawa", |
| + .of_match_table = of_match_clk_mt8192_cam_rawa, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_cam_rawa_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-cam_rawb.c b/drivers/clk/mediatek/clk-mt8192-cam_rawb.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..7fcc33f1af68cb4281c6ab492278f9e7a4fa64c5 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-cam_rawb.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs cam_rawb_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_CAM_RAWB(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &cam_rawb_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate cam_rawb_clks[] = { |
| + GATE_CAM_RAWB(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0), |
| + GATE_CAM_RAWB(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1), |
| + GATE_CAM_RAWB(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2), |
| +}; |
| + |
| +static int clk_mt8192_cam_rawb_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_CAM_RAWB_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, cam_rawb_clks, ARRAY_SIZE(cam_rawb_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_cam_rawb[] = { |
| + { .compatible = "mediatek,mt8192-camsys_rawb", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_cam_rawb_drv = { |
| + .probe = clk_mt8192_cam_rawb_probe, |
| + .driver = { |
| + .name = "clk-mt8192-cam_rawb", |
| + .of_match_table = of_match_clk_mt8192_cam_rawb, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_cam_rawb_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-cam_rawc.c b/drivers/clk/mediatek/clk-mt8192-cam_rawc.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..bc2aa548a40eef3dcf3b1983fb8d15d0df8f104d |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-cam_rawc.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs cam_rawc_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_CAM_RAWC(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &cam_rawc_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate cam_rawc_clks[] = { |
| + GATE_CAM_RAWC(CLK_CAM_RAWC_LARBX, "cam_rawc_larbx", "cam_sel", 0), |
| + GATE_CAM_RAWC(CLK_CAM_RAWC_CAM, "cam_rawc_cam", "cam_sel", 1), |
| + GATE_CAM_RAWC(CLK_CAM_RAWC_CAMTG, "cam_rawc_camtg", "cam_sel", 2), |
| +}; |
| + |
| +static int clk_mt8192_cam_rawc_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_CAM_RAWC_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, cam_rawc_clks, ARRAY_SIZE(cam_rawc_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_cam_rawc[] = { |
| + { .compatible = "mediatek,mt8192-camsys_rawc", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_cam_rawc_drv = { |
| + .probe = clk_mt8192_cam_rawc_probe, |
| + .driver = { |
| + .name = "clk-mt8192-cam_rawc", |
| + .of_match_table = of_match_clk_mt8192_cam_rawc, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_cam_rawc_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..9fa0f47322f4be461f90575789759b59d4b44f31 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-img.c |
| @@ -0,0 +1,57 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs img_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_IMG(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate img_clks[] = { |
| + GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0), |
| + GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1), |
| + GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2), |
| + GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12), |
| +}; |
| + |
| +static int clk_mt8192_img_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_img[] = { |
| + { .compatible = "mediatek,mt8192-imgsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_img_drv = { |
| + .probe = clk_mt8192_img_probe, |
| + .driver = { |
| + .name = "clk-mt8192-img", |
| + .of_match_table = of_match_clk_mt8192_img, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_img_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-img2.c b/drivers/clk/mediatek/clk-mt8192-img2.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..42925cce365c9251d24b6cc05ce9500af60a4946 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-img2.c |
| @@ -0,0 +1,59 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs img2_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_IMG2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &img2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate img2_clks[] = { |
| + GATE_IMG2(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0), |
| + GATE_IMG2(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1), |
| + GATE_IMG2(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6), |
| + GATE_IMG2(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7), |
| + GATE_IMG2(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8), |
| + GATE_IMG2(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12), |
| +}; |
| + |
| +static int clk_mt8192_img2_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMG2_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, img2_clks, ARRAY_SIZE(img2_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_img2[] = { |
| + { .compatible = "mediatek,mt8192-imgsys2", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_img2_drv = { |
| + .probe = clk_mt8192_img2_probe, |
| + .driver = { |
| + .name = "clk-mt8192-img2", |
| + .of_match_table = of_match_clk_mt8192_img2, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_img2_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..9ff38a297149352cf350ef4d5ccb4cc6a43bd4e9 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c |
| @@ -0,0 +1,57 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_c_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_C(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_c_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_c_clks[] = { |
| + GATE_IMP_IIC_WRAP_C(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0), |
| + GATE_IMP_IIC_WRAP_C(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1), |
| + GATE_IMP_IIC_WRAP_C(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2), |
| + GATE_IMP_IIC_WRAP_C(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_c_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_C_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_c_clks, ARRAY_SIZE(imp_iic_wrap_c_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_c[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_c", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_c_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_c_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_c", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_c, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_c_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..5a6a9bcc9eb36b0d7d9c6823741e81f94aff83c8 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c |
| @@ -0,0 +1,54 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_e_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_E(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_e_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_e_clks[] = { |
| + GATE_IMP_IIC_WRAP_E(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_e_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_E_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_e_clks, ARRAY_SIZE(imp_iic_wrap_e_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_e[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_e", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_e_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_e_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_e", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_e, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_e_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..573538b9a4dd06c71adf6cf4ccded975a2b06a55 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c |
| @@ -0,0 +1,55 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_n_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_N(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_n_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_n_clks[] = { |
| + GATE_IMP_IIC_WRAP_N(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0), |
| + GATE_IMP_IIC_WRAP_N(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_n_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_N_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_n_clks, ARRAY_SIZE(imp_iic_wrap_n_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_n[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_n", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_n_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_n_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_n", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_n, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_n_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..972b0c3e350e9c3864257a449ec8eb45fe297549 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_s_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_S(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_s_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_s_clks[] = { |
| + GATE_IMP_IIC_WRAP_S(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0), |
| + GATE_IMP_IIC_WRAP_S(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1), |
| + GATE_IMP_IIC_WRAP_S(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_s_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_S_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_s_clks, ARRAY_SIZE(imp_iic_wrap_s_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_s[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_s", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_s_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_s_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_s", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_s, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_s_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..c00ac8e890062332ef1d35a0f7137012740cad97 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c |
| @@ -0,0 +1,54 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_w_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_W(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_w_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_w_clks[] = { |
| + GATE_IMP_IIC_WRAP_W(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_w_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_W_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_w_clks, ARRAY_SIZE(imp_iic_wrap_w_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_w[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_w", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_w_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_w_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_w", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_w, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_w_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..e4dace1feeae165810657a8d0c7f2c28cc5b2bb5 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c |
| @@ -0,0 +1,56 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs imp_iic_wrap_ws_cg_regs = { |
| + .set_ofs = 0xe08, |
| + .clr_ofs = 0xe04, |
| + .sta_ofs = 0xe00, |
| +}; |
| + |
| +#define GATE_IMP_IIC_WRAP_WS(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &imp_iic_wrap_ws_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate imp_iic_wrap_ws_clks[] = { |
| + GATE_IMP_IIC_WRAP_WS(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0), |
| + GATE_IMP_IIC_WRAP_WS(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1), |
| + GATE_IMP_IIC_WRAP_WS(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2), |
| +}; |
| + |
| +static int clk_mt8192_imp_iic_wrap_ws_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_WS_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, imp_iic_wrap_ws_clks, ARRAY_SIZE(imp_iic_wrap_ws_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_ws[] = { |
| + { .compatible = "mediatek,mt8192-imp_iic_wrap_ws", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_imp_iic_wrap_ws_drv = { |
| + .probe = clk_mt8192_imp_iic_wrap_ws_probe, |
| + .driver = { |
| + .name = "clk-mt8192-imp_iic_wrap_ws", |
| + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_ws, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_imp_iic_wrap_ws_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..15109a8b53e373c01c4a298932892c32fa606676 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c |
| @@ -0,0 +1,61 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs ipe_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_IPE(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate ipe_clks[] = { |
| + GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0), |
| + GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1), |
| + GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2), |
| + GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3), |
| + GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4), |
| + GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5), |
| + GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6), |
| + GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8), |
| +}; |
| + |
| +static int clk_mt8192_ipe_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_ipe[] = { |
| + { .compatible = "mediatek,mt8192-ipesys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_ipe_drv = { |
| + .probe = clk_mt8192_ipe_probe, |
| + .driver = { |
| + .name = "clk-mt8192-ipe", |
| + .of_match_table = of_match_clk_mt8192_ipe, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_ipe_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/clk-mt8192-mdp.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..2d937fba037029fcdeae7accc93ec50a899dae6e |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c |
| @@ -0,0 +1,87 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs mdp0_cg_regs = { |
| + .set_ofs = 0x104, |
| + .clr_ofs = 0x108, |
| + .sta_ofs = 0x100, |
| +}; |
| + |
| +static const struct mtk_gate_regs mdp1_cg_regs = { |
| + .set_ofs = 0x124, |
| + .clr_ofs = 0x128, |
| + .sta_ofs = 0x120, |
| +}; |
| + |
| +#define GATE_MDP0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_MDP1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate mdp_clks[] = { |
| + /* MDP0 */ |
| + GATE_MDP0(CLK_MDP_RDMA0, "mdp_mdp_rdma0", "mdp_sel", 0), |
| + GATE_MDP0(CLK_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp_sel", 1), |
| + GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp_sel", 2), |
| + GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "mdp_sel", 3), |
| + GATE_MDP0(CLK_MDP_RDMA1, "mdp_mdp_rdma1", "mdp_sel", 4), |
| + GATE_MDP0(CLK_MDP_TDSHP1, "mdp_mdp_tdshp1", "mdp_sel", 5), |
| + GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp_sel", 6), |
| + GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp_sel", 7), |
| + GATE_MDP0(CLK_MDP_WROT0, "mdp_mdp_wrot0", "mdp_sel", 8), |
| + GATE_MDP0(CLK_MDP_RSZ0, "mdp_mdp_rsz0", "mdp_sel", 9), |
| + GATE_MDP0(CLK_MDP_HDR0, "mdp_mdp_hdr0", "mdp_sel", 10), |
| + GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp_sel", 11), |
| + GATE_MDP0(CLK_MDP_WROT1, "mdp_mdp_wrot1", "mdp_sel", 12), |
| + GATE_MDP0(CLK_MDP_RSZ1, "mdp_mdp_rsz1", "mdp_sel", 13), |
| + GATE_MDP0(CLK_MDP_HDR1, "mdp_mdp_hdr1", "mdp_sel", 14), |
| + GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp_sel", 15), |
| + GATE_MDP0(CLK_MDP_AAL0, "mdp_mdp_aal0", "mdp_sel", 16), |
| + GATE_MDP0(CLK_MDP_AAL1, "mdp_mdp_aal1", "mdp_sel", 17), |
| + GATE_MDP0(CLK_MDP_COLOR0, "mdp_mdp_color0", "mdp_sel", 18), |
| + GATE_MDP0(CLK_MDP_COLOR1, "mdp_mdp_color1", "mdp_sel", 19), |
| + /* MDP1 */ |
| + GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_relay0_async0", "mdp_sel", 0), |
| + GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_relay1_async1", "mdp_sel", 8), |
| +}; |
| + |
| +static int clk_mt8192_mdp_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_MDP_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, mdp_clks, ARRAY_SIZE(mdp_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_mdp[] = { |
| + { .compatible = "mediatek,mt8192-mdpsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_mdp_drv = { |
| + .probe = clk_mt8192_mdp_probe, |
| + .driver = { |
| + .name = "clk-mt8192-mdp", |
| + .of_match_table = of_match_clk_mt8192_mdp, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_mdp_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..1d8c17db5617e9bab4f8a37083d98c84dbf1476a |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c |
| @@ -0,0 +1,54 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs mfg_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_MFG(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate mfg_clks[] = { |
| + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0), |
| +}; |
| + |
| +static int clk_mt8192_mfg_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_mfg[] = { |
| + { .compatible = "mediatek,mt8192-mfgcfg", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_mfg_drv = { |
| + .probe = clk_mt8192_mfg_probe, |
| + .driver = { |
| + .name = "clk-mt8192-mfg", |
| + .of_match_table = of_match_clk_mt8192_mfg, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_mfg_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..18171c0a7c17962135620b746a9f66555ff9fc12 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-mm.c |
| @@ -0,0 +1,130 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs mm0_cg_regs = { |
| + .set_ofs = 0x104, |
| + .clr_ofs = 0x108, |
| + .sta_ofs = 0x100, |
| +}; |
| + |
| +static const struct mtk_gate_regs mm1_cg_regs = { |
| + .set_ofs = 0x114, |
| + .clr_ofs = 0x118, |
| + .sta_ofs = 0x110, |
| +}; |
| + |
| +static const struct mtk_gate_regs mm2_cg_regs = { |
| + .set_ofs = 0x1a4, |
| + .clr_ofs = 0x1a8, |
| + .sta_ofs = 0x1a0, |
| +}; |
| + |
| +#define GATE_MM0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_MM1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_MM2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate mt8192_mm_clks[] = { |
| + /* MM0 */ |
| + GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0), |
| + GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1), |
| + GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2), |
| + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3), |
| + GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4), |
| + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5), |
| + GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6), |
| + GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7), |
| + GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8), |
| + GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9), |
| + GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10), |
| + GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11), |
| + GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12), |
| + GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13), |
| + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14), |
| + GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15), |
| + GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16), |
| + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17), |
| + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18), |
| + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19), |
| + GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20), |
| + GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21), |
| + GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22), |
| + GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23), |
| + GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24), |
| + GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25), |
| + GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26), |
| + GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27), |
| + GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28), |
| + GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29), |
| + GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30), |
| + /* MM1 */ |
| + GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0), |
| + /* MM2 */ |
| + GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0), |
| + GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8), |
| + GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24), |
| + GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25), |
| +}; |
| + |
| +struct clk_mt8192_mm_driver_data { |
| + const struct mtk_gate *gates_clk; |
| + int gates_num; |
| +}; |
| + |
| +static const struct clk_mt8192_mm_driver_data mt8192_mmsys_driver_data = { |
| + .gates_clk = mt8192_mm_clks, |
| + .gates_num = ARRAY_SIZE(mt8192_mm_clks), |
| +}; |
| + |
| +static int clk_mt8192_mm_probe(struct platform_device *pdev) |
| +{ |
| + struct device *dev = &pdev->dev; |
| + struct device_node *node = dev->parent->of_node; |
| + const struct clk_mt8192_mm_driver_data *data; |
| + struct clk_onecell_data *clk_data; |
| + int ret; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); |
| + if (!clk_data) |
| + return -ENOMEM; |
| + |
| + data = &mt8192_mmsys_driver_data; |
| + |
| + ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, |
| + clk_data); |
| + if (ret) |
| + return ret; |
| + |
| + ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| + if (ret) |
| + return ret; |
| + |
| + return 0; |
| +} |
| + |
| + |
| +static struct platform_driver clk_mt8192_mm_drv = { |
| + .probe = clk_mt8192_mm_probe, |
| + .driver = { |
| + .name = "clk-mt8192-mm", |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_mm_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..f0b30a109d1b71b127184752548276195ff0ca9f |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c |
| @@ -0,0 +1,54 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs msdc_cg_regs = { |
| + .set_ofs = 0xb4, |
| + .clr_ofs = 0xb4, |
| + .sta_ofs = 0xb4, |
| +}; |
| + |
| +#define GATE_MSDC(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr_inv) |
| + |
| +static const struct mtk_gate msdc_clks[] = { |
| + GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22), |
| +}; |
| + |
| +static int clk_mt8192_msdc_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_MSDC_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, msdc_clks, ARRAY_SIZE(msdc_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_msdc[] = { |
| + { .compatible = "mediatek,mt8192-msdc", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_msdc_drv = { |
| + .probe = clk_mt8192_msdc_probe, |
| + .driver = { |
| + .name = "clk-mt8192-msdc", |
| + .of_match_table = of_match_clk_mt8192_msdc, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_msdc_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-msdc_top.c b/drivers/clk/mediatek/clk-mt8192-msdc_top.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..ce3e0e6ac9498f0edb75a02ea42c42ac40ad9fb3 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-msdc_top.c |
| @@ -0,0 +1,68 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs msdc_top_cg_regs = { |
| + .set_ofs = 0x0, |
| + .clr_ofs = 0x0, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr_inv) |
| + |
| +static const struct mtk_gate msdc_top_clks[] = { |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13), |
| + GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), |
| +}; |
| + |
| +static int clk_mt8192_msdc_top_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_MSDC_TOP_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, msdc_top_clks, ARRAY_SIZE(msdc_top_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_msdc_top[] = { |
| + { .compatible = "mediatek,mt8192-msdc_top", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_msdc_top_drv = { |
| + .probe = clk_mt8192_msdc_top_probe, |
| + .driver = { |
| + .name = "clk-mt8192-msdc_top", |
| + .of_match_table = of_match_clk_mt8192_msdc_top, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_msdc_top_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..b01bbf579662234341563aed2d8606568a29aa4b |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c |
| @@ -0,0 +1,54 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs scp_adsp_cg_regs = { |
| + .set_ofs = 0x180, |
| + .clr_ofs = 0x180, |
| + .sta_ofs = 0x180, |
| +}; |
| + |
| +#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr) |
| + |
| +static const struct mtk_gate scp_adsp_clks[] = { |
| + GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0), |
| +}; |
| + |
| +static int clk_mt8192_scp_adsp_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_SCP_ADSP_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, scp_adsp_clks, ARRAY_SIZE(scp_adsp_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_scp_adsp[] = { |
| + { .compatible = "mediatek,mt8192-scp_adsp", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_scp_adsp_drv = { |
| + .probe = clk_mt8192_scp_adsp_probe, |
| + .driver = { |
| + .name = "clk-mt8192-scp_adsp", |
| + .of_match_table = of_match_clk_mt8192_scp_adsp, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_scp_adsp_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..37f8a838d8eb1fe0f5bc670ffaa9efb788e0837c |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c |
| @@ -0,0 +1,81 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs vdec0_cg_regs = { |
| + .set_ofs = 0x0, |
| + .clr_ofs = 0x4, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +static const struct mtk_gate_regs vdec1_cg_regs = { |
| + .set_ofs = 0x200, |
| + .clr_ofs = 0x204, |
| + .sta_ofs = 0x200, |
| +}; |
| + |
| +static const struct mtk_gate_regs vdec2_cg_regs = { |
| + .set_ofs = 0x8, |
| + .clr_ofs = 0xc, |
| + .sta_ofs = 0x8, |
| +}; |
| + |
| +#define GATE_VDEC0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +#define GATE_VDEC1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +#define GATE_VDEC2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +static const struct mtk_gate vdec_clks[] = { |
| + /* VDEC0 */ |
| + GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0), |
| + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), |
| + /* VDEC1 */ |
| + GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0), |
| + GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4), |
| + /* VDEC2 */ |
| + GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0), |
| +}; |
| + |
| +static int clk_mt8192_vdec_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_vdec[] = { |
| + { .compatible = "mediatek,mt8192-vdecsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_vdec_drv = { |
| + .probe = clk_mt8192_vdec_probe, |
| + .driver = { |
| + .name = "clk-mt8192-vdec", |
| + .of_match_table = of_match_clk_mt8192_vdec, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_vdec_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-vdec_soc.c b/drivers/clk/mediatek/clk-mt8192-vdec_soc.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..2744d2cf9866101bebf96cc5934e5808814d40a5 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-vdec_soc.c |
| @@ -0,0 +1,81 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs vdec_soc0_cg_regs = { |
| + .set_ofs = 0x0, |
| + .clr_ofs = 0x4, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +static const struct mtk_gate_regs vdec_soc1_cg_regs = { |
| + .set_ofs = 0x200, |
| + .clr_ofs = 0x204, |
| + .sta_ofs = 0x200, |
| +}; |
| + |
| +static const struct mtk_gate_regs vdec_soc2_cg_regs = { |
| + .set_ofs = 0x8, |
| + .clr_ofs = 0xc, |
| + .sta_ofs = 0x8, |
| +}; |
| + |
| +#define GATE_VDEC_SOC0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec_soc0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +#define GATE_VDEC_SOC1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec_soc1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +#define GATE_VDEC_SOC2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &vdec_soc2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +static const struct mtk_gate vdec_soc_clks[] = { |
| + /* VDEC_SOC0 */ |
| + GATE_VDEC_SOC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0), |
| + GATE_VDEC_SOC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4), |
| + /* VDEC_SOC1 */ |
| + GATE_VDEC_SOC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0), |
| + GATE_VDEC_SOC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4), |
| + /* VDEC_SOC2 */ |
| + GATE_VDEC_SOC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0), |
| +}; |
| + |
| +static int clk_mt8192_vdec_soc_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_VDEC_SOC_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, vdec_soc_clks, ARRAY_SIZE(vdec_soc_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_vdec_soc[] = { |
| + { .compatible = "mediatek,mt8192-vdecsys_soc", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_vdec_soc_drv = { |
| + .probe = clk_mt8192_vdec_soc_probe, |
| + .driver = { |
| + .name = "clk-mt8192-vdec_soc", |
| + .of_match_table = of_match_clk_mt8192_vdec_soc, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_vdec_soc_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..8675d6a1e24dc80d3b7650551a46b50802e424b5 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192-venc.c |
| @@ -0,0 +1,57 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/platform_device.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +static const struct mtk_gate_regs venc_cg_regs = { |
| + .set_ofs = 0x4, |
| + .clr_ofs = 0x8, |
| + .sta_ofs = 0x0, |
| +}; |
| + |
| +#define GATE_VENC(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr_inv) |
| + |
| +static const struct mtk_gate venc_clks[] = { |
| + GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "venc_sel", 0), |
| + GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "venc_sel", 4), |
| + GATE_VENC(CLK_VENC_SET2_JPGENC, "venc_set2_jpgenc", "venc_sel", 8), |
| + GATE_VENC(CLK_VENC_SET5_GALS, "venc_set5_gals", "venc_sel", 28), |
| +}; |
| + |
| +static int clk_mt8192_venc_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192_venc[] = { |
| + { .compatible = "mediatek,mt8192-vencsys", }, |
| + {} |
| +}; |
| + |
| +static struct platform_driver clk_mt8192_venc_drv = { |
| + .probe = clk_mt8192_venc_probe, |
| + .driver = { |
| + .name = "clk-mt8192-venc", |
| + .of_match_table = of_match_clk_mt8192_venc, |
| + }, |
| +}; |
| + |
| +builtin_platform_driver(clk_mt8192_venc_drv); |
| diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..aaa4231eaa1d2ac935a0700880521a20af9acaf0 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clk-mt8192.c |
| @@ -0,0 +1,1357 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk.h> |
| +#include <linux/delay.h> |
| +#include <linux/mfd/syscon.h> |
| +#include <linux/of.h> |
| +#include <linux/of_address.h> |
| +#include <linux/of_device.h> |
| +#include <linux/platform_device.h> |
| +#include <linux/slab.h> |
| + |
| +#include "clk-mtk.h" |
| +#include "clk-mux.h" |
| +#include "clk-gate.h" |
| + |
| +#include <dt-bindings/clock/mt8192-clk.h> |
| + |
| +/* Infra global controller reset set register */ |
| +#define INFRA_RST0_SET_OFFSET 0x120 |
| + |
| +static DEFINE_SPINLOCK(mt8192_clk_lock); |
| + |
| +static const struct mtk_fixed_clk top_fixed_clks[] = { |
| + FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), |
| +}; |
| + |
| +static const struct mtk_fixed_factor top_early_divs[] = { |
| + FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), |
| +}; |
| + |
| +static const struct mtk_fixed_factor top_divs[] = { |
| + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), |
| + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), |
| + FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2), |
| + FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4), |
| + FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8), |
| + FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16), |
| + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), |
| + FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), |
| + FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), |
| + FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8), |
| + FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), |
| + FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2), |
| + FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4), |
| + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), |
| + FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), |
| + FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), |
| + FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8), |
| + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), |
| + FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), |
| + FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2), |
| + FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4), |
| + FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8), |
| + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), |
| + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), |
| + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), |
| + FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), |
| + FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), |
| + FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2), |
| + FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4), |
| + FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8), |
| + FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16), |
| + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), |
| + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), |
| + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), |
| + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), |
| + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), |
| + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), |
| + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), |
| + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), |
| + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), |
| + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), |
| + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), |
| + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), |
| + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), |
| + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), |
| + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), |
| + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), |
| + FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), |
| + FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), |
| + FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), |
| + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), |
| + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), |
| + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), |
| + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), |
| + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), |
| + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), |
| + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), |
| + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), |
| + FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), |
| + FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), |
| + FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), |
| + FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), |
| + FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), |
| + FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), |
| + FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), |
| + FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), |
| + FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2), |
| + FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4), |
| + FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8), |
| + FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16), |
| + FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32), |
| +}; |
| + |
| +static const char * const axi_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d4", |
| + "mainpll_d7_d2", |
| + "mainpll_d4_d2", |
| + "mainpll_d5_d2", |
| + "mainpll_d6_d2", |
| + "osc_d4" |
| +}; |
| + |
| +static const char * const spm_parents[] = { |
| + "clk26m", |
| + "osc_d10", |
| + "mainpll_d7_d4", |
| + "clk32k" |
| +}; |
| + |
| +static const char * const scp_parents[] = { |
| + "clk26m", |
| + "univpll_d5", |
| + "mainpll_d6_d2", |
| + "mainpll_d6", |
| + "univpll_d6", |
| + "mainpll_d4_d2", |
| + "mainpll_d5_d2", |
| + "univpll_d4_d2" |
| +}; |
| + |
| +static const char * const bus_aximem_parents[] = { |
| + "clk26m", |
| + "mainpll_d7_d2", |
| + "mainpll_d4_d2", |
| + "mainpll_d5_d2", |
| + "mainpll_d6" |
| +}; |
| + |
| +static const char * const disp_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d2", |
| + "mainpll_d5_d2", |
| + "mmpll_d6_d2", |
| + "univpll_d5_d2", |
| + "univpll_d4_d2", |
| + "mmpll_d7", |
| + "univpll_d6", |
| + "mainpll_d4", |
| + "mmpll_d5_d2" |
| +}; |
| + |
| +static const char * const mdp_parents[] = { |
| + "clk26m", |
| + "mainpll_d5_d2", |
| + "mmpll_d6_d2", |
| + "mainpll_d4_d2", |
| + "mmpll_d4_d2", |
| + "mainpll_d6", |
| + "univpll_d6", |
| + "mainpll_d4", |
| + "tvdpll_ck", |
| + "univpll_d4", |
| + "mmpll_d5_d2" |
| +}; |
| + |
| +static const char * const img1_parents[] = { |
| + "clk26m", |
| + "univpll_d4", |
| + "tvdpll_ck", |
| + "mainpll_d4", |
| + "univpll_d5", |
| + "mmpll_d6", |
| + "univpll_d6", |
| + "mainpll_d6", |
| + "mmpll_d4_d2", |
| + "mainpll_d4_d2", |
| + "mmpll_d6_d2", |
| + "mmpll_d5_d2" |
| +}; |
| + |
| +static const char * const img2_parents[] = { |
| + "clk26m", |
| + "univpll_d4", |
| + "tvdpll_ck", |
| + "mainpll_d4", |
| + "univpll_d5", |
| + "mmpll_d6", |
| + "univpll_d6", |
| + "mainpll_d6", |
| + "mmpll_d4_d2", |
| + "mainpll_d4_d2", |
| + "mmpll_d6_d2", |
| + "mmpll_d5_d2" |
| +}; |
| + |
| +static const char * const ipe_parents[] = { |
| + "clk26m", |
| + "mainpll_d4", |
| + "mmpll_d6", |
| + "univpll_d6", |
| + "mainpll_d6", |
| + "univpll_d4_d2", |
| + "mainpll_d4_d2", |
| + "mmpll_d6_d2", |
| + "mmpll_d5_d2" |
| +}; |
| + |
| +static const char * const dpe_parents[] = { |
| + "clk26m", |
| + "mainpll_d4", |
| + "mmpll_d6", |
| + "univpll_d6", |
| + "mainpll_d6", |
| + "univpll_d4_d2", |
| + "univpll_d5_d2", |
| + "mmpll_d6_d2" |
| +}; |
| + |
| +static const char * const cam_parents[] = { |
| + "clk26m", |
| + "mainpll_d4", |
| + "mmpll_d6", |
| + "univpll_d4", |
| + "univpll_d5", |
| + "univpll_d6", |
| + "mmpll_d7", |
| + "univpll_d4_d2", |
| + "mainpll_d4_d2", |
| + "univpll_d6_d2" |
| +}; |
| + |
| +static const char * const ccu_parents[] = { |
| + "clk26m", |
| + "mainpll_d4", |
| + "mmpll_d6", |
| + "mainpll_d6", |
| + "mmpll_d7", |
| + "univpll_d4_d2", |
| + "mmpll_d6_d2", |
| + "mmpll_d5_d2", |
| + "univpll_d5", |
| + "univpll_d6_d2" |
| +}; |
| + |
| +static const char * const dsp_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2", |
| + "univpll_d5", |
| + "univpll_d4", |
| + "mmpll_d4", |
| + "mainpll_d3", |
| + "univpll_d3" |
| +}; |
| + |
| +static const char * const dsp1_parents[] = { |
| + "clk26m", |
| + "npupll_ck", |
| + "mainpll_d4_d2", |
| + "univpll_d5", |
| + "univpll_d4", |
| + "mainpll_d3", |
| + "univpll_d3", |
| + "apupll_ck" |
| +}; |
| + |
| +static const char * const dsp1_npupll_parents[] = { |
| + "dsp1_sel", |
| + "npupll_ck" |
| +}; |
| + |
| +static const char * const dsp2_parents[] = { |
| + "clk26m", |
| + "npupll_ck", |
| + "mainpll_d4_d2", |
| + "univpll_d5", |
| + "univpll_d4", |
| + "mainpll_d3", |
| + "univpll_d3", |
| + "apupll_ck" |
| +}; |
| + |
| +static const char * const dsp2_npupll_parents[] = { |
| + "dsp2_sel", |
| + "npupll_ck" |
| +}; |
| + |
| +static const char * const dsp5_parents[] = { |
| + "clk26m", |
| + "apupll_ck", |
| + "univpll_d4_d2", |
| + "mainpll_d4", |
| + "univpll_d4", |
| + "mmpll_d4", |
| + "mainpll_d3", |
| + "univpll_d3" |
| +}; |
| + |
| +static const char * const dsp5_apupll_parents[] = { |
| + "dsp5_sel", |
| + "apupll_ck" |
| +}; |
| + |
| +static const char * const dsp7_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d2", |
| + "mainpll_d6", |
| + "mmpll_d6", |
| + "univpll_d5", |
| + "mmpll_d5", |
| + "univpll_d4", |
| + "mmpll_d4" |
| +}; |
| + |
| +static const char * const ipu_if_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d2", |
| + "mainpll_d4_d2", |
| + "univpll_d4_d2", |
| + "univpll_d5", |
| + "mainpll_d4", |
| + "tvdpll_ck", |
| + "univpll_d4" |
| +}; |
| + |
| +static const char * const mfg_ref_parents[] = { |
| + "clk26m", |
| + "clk26m", |
| + "univpll_d6", |
| + "mainpll_d5_d2" |
| +}; |
| + |
| +static const char * const mfg_pll_parents[] = { |
| + "mfg_ref_sel", |
| + "mfgpll" |
| +}; |
| + |
| +static const char * const camtg_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const camtg2_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const camtg3_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const camtg4_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const camtg5_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const camtg6_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d8", |
| + "univpll_d6_d8", |
| + "univpll_192m_d4", |
| + "univpll_d6_d16", |
| + "csw_f26m_d2", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32" |
| +}; |
| + |
| +static const char * const uart_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d8" |
| +}; |
| + |
| +static const char * const spi_parents[] = { |
| + "clk26m", |
| + "mainpll_d5_d4", |
| + "mainpll_d6_d4", |
| + "msdcpll_d4" |
| +}; |
| + |
| +static const char * const msdc50_0_h_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d2", |
| + "mainpll_d6_d2" |
| +}; |
| + |
| +static const char * const msdc50_0_parents[] = { |
| + "clk26m", |
| + "msdcpll_ck", |
| + "msdcpll_d2", |
| + "univpll_d4_d4", |
| + "mainpll_d6_d2", |
| + "univpll_d4_d2" |
| +}; |
| + |
| +static const char * const msdc30_1_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d2", |
| + "mainpll_d6_d2", |
| + "mainpll_d7_d2", |
| + "msdcpll_d2" |
| +}; |
| + |
| +static const char * const msdc30_2_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d2", |
| + "mainpll_d6_d2", |
| + "mainpll_d7_d2", |
| + "msdcpll_d2" |
| +}; |
| + |
| +static const char * const audio_parents[] = { |
| + "clk26m", |
| + "mainpll_d5_d8", |
| + "mainpll_d7_d8", |
| + "mainpll_d4_d16" |
| +}; |
| + |
| +static const char * const aud_intbus_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d4", |
| + "mainpll_d7_d4" |
| +}; |
| + |
| +static const char * const pwrap_ulposc_parents[] = { |
| + "osc_d10", |
| + "clk26m", |
| + "osc_d4", |
| + "osc_d8", |
| + "osc_d16" |
| +}; |
| + |
| +static const char * const atb_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d2", |
| + "mainpll_d5_d2" |
| +}; |
| + |
| +static const char * const sspm_parents[] = { |
| + "clk26m", |
| + "mainpll_d5_d2", |
| + "univpll_d5_d2", |
| + "mainpll_d4_d2", |
| + "univpll_d4_d2", |
| + "mainpll_d6" |
| +}; |
| + |
| +static const char * const dpi_parents[] = { |
| + "clk26m", |
| + "tvdpll_d2", |
| + "tvdpll_d4", |
| + "tvdpll_d8", |
| + "tvdpll_d16" |
| +}; |
| + |
| +static const char * const scam_parents[] = { |
| + "clk26m", |
| + "mainpll_d5_d4" |
| +}; |
| + |
| +static const char * const disp_pwm_parents[] = { |
| + "clk26m", |
| + "univpll_d6_d4", |
| + "osc_d2", |
| + "osc_d4", |
| + "osc_d16" |
| +}; |
| + |
| +static const char * const usb_top_parents[] = { |
| + "clk26m", |
| + "univpll_d5_d4", |
| + "univpll_d6_d4", |
| + "univpll_d5_d2" |
| +}; |
| + |
| +static const char * const ssusb_xhci_parents[] = { |
| + "clk26m", |
| + "univpll_d5_d4", |
| + "univpll_d6_d4", |
| + "univpll_d5_d2" |
| +}; |
| + |
| +static const char * const i2c_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d8", |
| + "univpll_d5_d4" |
| +}; |
| + |
| +static const char * const seninf_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d4", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2", |
| + "univpll_d7", |
| + "univpll_d6", |
| + "mmpll_d6", |
| + "univpll_d5" |
| +}; |
| + |
| +static const char * const seninf1_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d4", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2", |
| + "univpll_d7", |
| + "univpll_d6", |
| + "mmpll_d6", |
| + "univpll_d5" |
| +}; |
| + |
| +static const char * const seninf2_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d4", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2", |
| + "univpll_d7", |
| + "univpll_d6", |
| + "mmpll_d6", |
| + "univpll_d5" |
| +}; |
| + |
| +static const char * const seninf3_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d4", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2", |
| + "univpll_d7", |
| + "univpll_d6", |
| + "mmpll_d6", |
| + "univpll_d5" |
| +}; |
| + |
| +static const char * const tl_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d2", |
| + "mainpll_d6_d4" |
| +}; |
| + |
| +static const char * const dxcc_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d2", |
| + "mainpll_d4_d4", |
| + "mainpll_d4_d8" |
| +}; |
| + |
| +static const char * const aud_engen1_parents[] = { |
| + "clk26m", |
| + "apll1_d2", |
| + "apll1_d4", |
| + "apll1_d8" |
| +}; |
| + |
| +static const char * const aud_engen2_parents[] = { |
| + "clk26m", |
| + "apll2_d2", |
| + "apll2_d4", |
| + "apll2_d8" |
| +}; |
| + |
| +static const char * const aes_ufsfde_parents[] = { |
| + "clk26m", |
| + "mainpll_d4", |
| + "mainpll_d4_d2", |
| + "mainpll_d6", |
| + "mainpll_d4_d4", |
| + "univpll_d4_d2", |
| + "univpll_d6" |
| +}; |
| + |
| +static const char * const ufs_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d4", |
| + "mainpll_d4_d8", |
| + "univpll_d4_d4", |
| + "mainpll_d6_d2", |
| + "mainpll_d5_d2", |
| + "msdcpll_d2" |
| +}; |
| + |
| +static const char * const aud_1_parents[] = { |
| + "clk26m", |
| + "apll1_ck" |
| +}; |
| + |
| +static const char * const aud_2_parents[] = { |
| + "clk26m", |
| + "apll2_ck" |
| +}; |
| + |
| +static const char * const adsp_parents[] = { |
| + "clk26m", |
| + "mainpll_d6", |
| + "mainpll_d5_d2", |
| + "univpll_d4_d4", |
| + "univpll_d4", |
| + "univpll_d6", |
| + "ulposc", |
| + "adsppll_ck" |
| +}; |
| + |
| +static const char * const dpmaif_main_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d4", |
| + "mainpll_d6", |
| + "mainpll_d4_d2", |
| + "univpll_d4_d2" |
| +}; |
| + |
| +static const char * const venc_parents[] = { |
| + "clk26m", |
| + "mmpll_d7", |
| + "mainpll_d6", |
| + "univpll_d4_d2", |
| + "mainpll_d4_d2", |
| + "univpll_d6", |
| + "mmpll_d6", |
| + "mainpll_d5_d2", |
| + "mainpll_d6_d2", |
| + "mmpll_d9", |
| + "univpll_d4_d4", |
| + "mainpll_d4", |
| + "univpll_d4", |
| + "univpll_d5", |
| + "univpll_d5_d2", |
| + "mainpll_d5" |
| +}; |
| + |
| +static const char * const vdec_parents[] = { |
| + "clk26m", |
| + "univpll_192m_d2", |
| + "univpll_d5_d4", |
| + "mainpll_d5", |
| + "mainpll_d5_d2", |
| + "mmpll_d6_d2", |
| + "univpll_d5_d2", |
| + "mainpll_d4_d2", |
| + "univpll_d4_d2", |
| + "univpll_d7", |
| + "mmpll_d7", |
| + "mmpll_d6", |
| + "univpll_d5", |
| + "mainpll_d4", |
| + "univpll_d4", |
| + "univpll_d6" |
| +}; |
| + |
| +static const char * const camtm_parents[] = { |
| + "clk26m", |
| + "univpll_d7", |
| + "univpll_d6_d2", |
| + "univpll_d4_d2" |
| +}; |
| + |
| +static const char * const pwm_parents[] = { |
| + "clk26m", |
| + "univpll_d4_d8" |
| +}; |
| + |
| +static const char * const audio_h_parents[] = { |
| + "clk26m", |
| + "univpll_d7", |
| + "apll1_ck", |
| + "apll2_ck" |
| +}; |
| + |
| +static const char * const spmi_mst_parents[] = { |
| + "clk26m", |
| + "csw_f26m_d2", |
| + "osc_d8", |
| + "osc_d10", |
| + "osc_d16", |
| + "osc_d20", |
| + "clk32k" |
| +}; |
| + |
| +static const char * const aes_msdcfde_parents[] = { |
| + "clk26m", |
| + "mainpll_d4_d2", |
| + "mainpll_d6", |
| + "mainpll_d4_d4", |
| + "univpll_d4_d2", |
| + "univpll_d6" |
| +}; |
| + |
| +static const char * const mcupm_parents[] = { |
| + "clk26m", |
| + "mainpll_d6_d4", |
| + "mainpll_d6_d2" |
| +}; |
| + |
| +static const char * const sflash_parents[] = { |
| + "clk26m", |
| + "mainpll_d7_d8", |
| + "univpll_d6_d8", |
| + "univpll_d5_d8" |
| +}; |
| + |
| +static const char * const apll_i2s0_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s1_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s2_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s3_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s4_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s5_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s6_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s7_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s8_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +static const char * const apll_i2s9_m_parents[] = { |
| + "aud_1_sel", |
| + "aud_2_sel" |
| +}; |
| + |
| +/* |
| + * CRITICAL CLOCK: |
| + * axi_sel is the main bus clock of whole SOC. |
| + * spm_sel is the clock of the always-on co-processor. |
| + * bus_aximem_sel is clock of the bus that access emi. |
| + */ |
| +static const struct mtk_mux top_mtk_muxes[] = { |
| + /* CLK_CFG_0 */ |
| + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, CLK_IS_CRITICAL), |
| + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, CLK_IS_CRITICAL), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), |
| + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, CLK_IS_CRITICAL), |
| + /* CLK_CFG_1 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), |
| + /* CLK_CFG_2 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), |
| + /* CLK_CFG_3 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x004, 12), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel", dsp1_parents, 0x040, 0x044, 0x048, 8, 3, 15, 0x004, 13), |
| + MUX_CLR_SET_UPD(CLK_TOP_DSP1_NPUPLL_SEL, "dsp1_npupll_sel", dsp1_npupll_parents, 0x040, 0x044, 0x048, 11, 1, -1, -1), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel", dsp2_parents, 0x040, 0x044, 0x048, 16, 3, 23, 0x004, 14), |
| + MUX_CLR_SET_UPD(CLK_TOP_DSP2_NPUPLL_SEL, "dsp2_npupll_sel", dsp2_npupll_parents, 0x040, 0x044, 0x048, 19, 1, -1, -1), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel", dsp5_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x004, 15), |
| + MUX_CLR_SET_UPD(CLK_TOP_DSP5_APUPLL_SEL, "dsp5_apupll_sel", dsp5_apupll_parents, 0x040, 0x044, 0x048, 27, 1, -1, -1), |
| + /* CLK_CFG_4 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel", ipu_if_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x004, 17), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), |
| + MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), |
| + /* CLK_CFG_5 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), |
| + /* CLK_CFG_6 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), |
| + /* CLK_CFG_7 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), |
| + /* CLK_CFG_8 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents, 0x090, 0x094, 0x098, 24, 3, 31, 0x008, 4), |
| + /* CLK_CFG_9 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), |
| + /* CLK_CFG_10 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), |
| + /* CLK_CFG_11 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), |
| + /* CLK_CFG_12 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), |
| + /* CLK_CFG_13 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), |
| + /* CLK_CFG_14 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), |
| + /* CLK_CFG_15 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), |
| + /* CLK_CFG_16 */ |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel", mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2), |
| + MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), |
| +}; |
| + |
| +static struct mtk_composite top_muxes[] = { |
| + /* CLK_AUDDIV_0 */ |
| + MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1), |
| + MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1), |
| + MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1), |
| + MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1), |
| + MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1), |
| + MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1), |
| + MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1), |
| + MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1), |
| + MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1), |
| + MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1), |
| +}; |
| + |
| +static const struct mtk_composite top_adj_divs[] = { |
| + DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), |
| + DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), |
| + DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), |
| + DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), |
| + DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), |
| + DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), |
| + DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), |
| + DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), |
| + DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), |
| + DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), |
| + DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), |
| +}; |
| + |
| +static const struct mtk_gate_regs apmixed_cg_regs = { |
| + .set_ofs = 0x14, |
| + .clr_ofs = 0x14, |
| + .sta_ofs = 0x14, |
| +}; |
| + |
| +#define GATE_APMIXED(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr_inv) |
| + |
| +static const struct mtk_gate apmixed_clks[] = { |
| + GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), |
| +}; |
| + |
| +static const struct mtk_gate_regs infra0_cg_regs = { |
| + .set_ofs = 0x80, |
| + .clr_ofs = 0x84, |
| + .sta_ofs = 0x90, |
| +}; |
| + |
| +static const struct mtk_gate_regs infra1_cg_regs = { |
| + .set_ofs = 0x88, |
| + .clr_ofs = 0x8c, |
| + .sta_ofs = 0x94, |
| +}; |
| + |
| +static const struct mtk_gate_regs infra2_cg_regs = { |
| + .set_ofs = 0xa4, |
| + .clr_ofs = 0xa8, |
| + .sta_ofs = 0xac, |
| +}; |
| + |
| +static const struct mtk_gate_regs infra3_cg_regs = { |
| + .set_ofs = 0xc0, |
| + .clr_ofs = 0xc4, |
| + .sta_ofs = 0xc8, |
| +}; |
| + |
| +static const struct mtk_gate_regs infra4_cg_regs = { |
| + .set_ofs = 0xd0, |
| + .clr_ofs = 0xd4, |
| + .sta_ofs = 0xd8, |
| +}; |
| + |
| +static const struct mtk_gate_regs infra5_cg_regs = { |
| + .set_ofs = 0xe0, |
| + .clr_ofs = 0xe4, |
| + .sta_ofs = 0xe8, |
| +}; |
| + |
| +#define GATE_INFRA0(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_INFRA1(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_INFRA2(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_INFRA3(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_INFRA4(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +#define GATE_INFRA5(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &infra5_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_setclr) |
| + |
| +static const struct mtk_gate infra_clks[] = { |
| + /* INFRA0 */ |
| + GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), |
| + GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), |
| + GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), |
| + GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), |
| + GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), |
| + GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), |
| + GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), |
| + GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7), |
| + GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), |
| + GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), |
| + GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), |
| + GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), |
| + GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), |
| + GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), |
| + GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), |
| + GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), |
| + GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), |
| + GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), |
| + GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), |
| + GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), |
| + GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), |
| + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), |
| + GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), |
| + GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), |
| + GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), |
| + GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), |
| + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), |
| + GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), |
| + /* INFRA1 */ |
| + GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), |
| + GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), |
| + GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), |
| + GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), |
| + GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), |
| + GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), |
| + GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), |
| + GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), |
| + GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), |
| + GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), |
| + GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), |
| + GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), |
| + GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), |
| + GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), |
| + GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), |
| + GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "axi_sel", 18), |
| + GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), |
| + GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), |
| + GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), |
| + GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), |
| + GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), |
| + GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), |
| + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), |
| + GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), |
| + GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), |
| + GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), |
| + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), |
| + /* INFRA2 */ |
| + GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), |
| + GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), |
| + GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), |
| + GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), |
| + GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), |
| + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), |
| + GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), |
| + GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), |
| + GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), |
| + GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), |
| + GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), |
| + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), |
| + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), |
| + GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), |
| + GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15), |
| + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), |
| + GATE_INFRA2(CLK_INFRA_SSPM_BUS_H, "infra_sspm_bus_h", "axi_sel", 17), |
| + GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), |
| + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), |
| + GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), |
| + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), |
| + GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), |
| + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), |
| + GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), |
| + GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), |
| + GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), |
| + GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), |
| + GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), |
| + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), |
| + GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), |
| + GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), |
| + /* INFRA3 */ |
| + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), |
| + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), |
| + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), |
| + GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "clk26m", 3), |
| + GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "clk32k", 4), |
| + GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), |
| + GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), |
| + GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), |
| + GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), |
| + GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), |
| + GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), |
| + GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), |
| + GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), |
| + GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), |
| + GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), |
| + GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), |
| + GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), |
| + GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), |
| + GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), |
| + GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), |
| + GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), |
| + GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), |
| + GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), |
| + GATE_INFRA3(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25), |
| + GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), |
| + GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), |
| + GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), |
| + GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), |
| + GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), |
| + GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), |
| + /* INFRA4 */ |
| + GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), |
| + /* INFRA5 */ |
| + GATE_INFRA5(CLK_INFRA_133M, "infra_133m", "axi_sel", 0), |
| + GATE_INFRA5(CLK_INFRA_66M, "infra_66m", "axi_sel", 1), |
| + GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), |
| + GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), |
| + GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), |
| + GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), |
| + GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), |
| + GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), |
| + GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), |
| +}; |
| + |
| +static const struct mtk_gate_regs peri_cg_regs = { |
| + .set_ofs = 0x20c, |
| + .clr_ofs = 0x20c, |
| + .sta_ofs = 0x20c, |
| +}; |
| + |
| +#define GATE_PERI(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr_inv) |
| + |
| +static const struct mtk_gate peri_clks[] = { |
| + GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), |
| +}; |
| + |
| +static const struct mtk_gate_regs top_cg_regs = { |
| + .set_ofs = 0x150, |
| + .clr_ofs = 0x150, |
| + .sta_ofs = 0x150, |
| +}; |
| + |
| +#define GATE_TOP(_id, _name, _parent, _shift) \ |
| + GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ |
| + &mtk_clk_gate_ops_no_setclr_inv) |
| + |
| +static const struct mtk_gate top_clks[] = { |
| + GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), |
| + GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), |
| +}; |
| + |
| +#define MT8192_PLL_FMAX (3800UL * MHZ) |
| +#define MT8192_PLL_FMIN (1500UL * MHZ) |
| +#define MT8192_INTEGER_BITS 8 |
| + |
| +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ |
| + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ |
| + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ |
| + _pcw_reg, _pcw_shift, _pcw_chg_reg, \ |
| + _en_reg, _base_en_bit) { \ |
| + .id = _id, \ |
| + .name = _name, \ |
| + .reg = _reg, \ |
| + .pwr_reg = _pwr_reg, \ |
| + .en_mask = _en_mask, \ |
| + .flags = _flags, \ |
| + .rst_bar_mask = _rst_bar_mask, \ |
| + .fmax = MT8192_PLL_FMAX, \ |
| + .fmin = MT8192_PLL_FMIN, \ |
| + .pcwbits = _pcwbits, \ |
| + .pcwibits = MT8192_INTEGER_BITS, \ |
| + .pd_reg = _pd_reg, \ |
| + .pd_shift = _pd_shift, \ |
| + .tuner_reg = _tuner_reg, \ |
| + .tuner_en_reg = _tuner_en_reg, \ |
| + .tuner_en_bit = _tuner_en_bit, \ |
| + .pcw_reg = _pcw_reg, \ |
| + .pcw_shift = _pcw_shift, \ |
| + .pcw_chg_reg = _pcw_chg_reg, \ |
| + .en_reg = _en_reg, \ |
| + .base_en_bit = _base_en_bit, \ |
| + } |
| + |
| +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ |
| + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ |
| + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ |
| + _pcw_reg, _pcw_shift) \ |
| + PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ |
| + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ |
| + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ |
| + _pcw_reg, _pcw_shift, 0, 0, 0) |
| + |
| +static const struct mtk_pll_data plls[] = { |
| + PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000001, |
| + HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), |
| + PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000001, |
| + HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), |
| + PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, |
| + 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), |
| + PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000001, |
| + 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), |
| + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000001, |
| + HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), |
| + PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000001, |
| + HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), |
| + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000001, |
| + 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), |
| + PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000001, |
| + 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), |
| + PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000001, |
| + 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), |
| + PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000001, |
| + 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), |
| + PLL_B(CLK_APMIXED_APUPLL, "apupll", 0x03a0, 0x03ac, 0xff000001, |
| + HAVE_RST_BAR, BIT(23), 22, 0x03a4, 24, 0, 0, 0, 0x03a4, 0), |
| + PLL_B(CLK_APMIXED_NPUPLL, "npupll", 0x03b4, 0x03c0, 0x00000001, |
| + 0, 0, 22, 0x03b8, 24, 0, 0, 0, 0x03b8, 0), |
| +}; |
| + |
| +static struct clk_onecell_data *top_clk_data; |
| + |
| +static void clk_mt8192_top_init_early(struct device_node *node) |
| +{ |
| + int i; |
| + |
| + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); |
| + |
| + for (i = 0; i < CLK_TOP_NR_CLK; i++) |
| + top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); |
| + |
| + mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), |
| + top_clk_data); |
| + |
| + of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); |
| +} |
| + |
| +CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", |
| + clk_mt8192_top_init_early); |
| + |
| +static int clk_mt8192_top_probe(struct platform_device *pdev) |
| +{ |
| + struct device_node *node = pdev->dev.of_node; |
| + void __iomem *base; |
| + |
| + base = devm_platform_ioremap_resource(pdev, 0); |
| + if (IS_ERR(base)) |
| + return PTR_ERR(base); |
| + |
| + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), |
| + top_clk_data); |
| + mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), |
| + top_clk_data); |
| + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); |
| + mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, |
| + &mt8192_clk_lock, top_clk_data); |
| + |
| + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, |
| + &mt8192_clk_lock, top_clk_data); |
| + mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, |
| + &mt8192_clk_lock, top_clk_data); |
| + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), |
| + top_clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); |
| +} |
| + |
| +static int clk_mt8192_infra_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), |
| + clk_data); |
| + |
| + mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static int clk_mt8192_peri_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); |
| + |
| + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static int clk_mt8192_apmixed_probe(struct platform_device *pdev) |
| +{ |
| + struct clk_onecell_data *clk_data; |
| + struct device_node *node = pdev->dev.of_node; |
| + |
| + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); |
| + |
| + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); |
| + mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), |
| + clk_data); |
| + |
| + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| +} |
| + |
| +static const struct of_device_id of_match_clk_mt8192[] = { |
| + { |
| + .compatible = "mediatek,mt8192-apmixedsys", |
| + .data = clk_mt8192_apmixed_probe, |
| + }, { |
| + .compatible = "mediatek,mt8192-topckgen", |
| + .data = clk_mt8192_top_probe, |
| + }, { |
| + .compatible = "mediatek,mt8192-infracfg", |
| + .data = clk_mt8192_infra_probe, |
| + }, { |
| + .compatible = "mediatek,mt8192-pericfg", |
| + .data = clk_mt8192_peri_probe, |
| + }, { |
| + /* sentinel */ |
| + } |
| +}; |
| + |
| +static int clk_mt8192_probe(struct platform_device *pdev) |
| +{ |
| + int (*clk_probe)(struct platform_device *pdev); |
| + int r; |
| + |
| + clk_probe = of_device_get_match_data(&pdev->dev); |
| + if (!clk_probe) |
| + return -EINVAL; |
| + |
| + r = clk_probe(pdev); |
| + if (r) |
| + dev_err(&pdev->dev, |
| + "could not register clock provider: %s: %d\n", |
| + pdev->name, r); |
| + |
| + return r; |
| +} |
| + |
| +static struct platform_driver clk_mt8192_drv = { |
| + .probe = clk_mt8192_probe, |
| + .driver = { |
| + .name = "clk-mt8192", |
| + .of_match_table = of_match_clk_mt8192, |
| + }, |
| +}; |
| + |
| +static int __init clk_mt8192_init(void) |
| +{ |
| + return platform_driver_register(&clk_mt8192_drv); |
| +} |
| + |
| +arch_initcall(clk_mt8192_init); |
| + |
| + |
| diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h |
| index c3d6756b0c7e758f503ec8c107d04ae91458b817..8bb0b3d4ee2a2ea1c9174be9d0c7bad98cc5cfea 100644 |
| --- a/drivers/clk/mediatek/clk-mtk.h |
| +++ b/drivers/clk/mediatek/clk-mtk.h |
| @@ -233,6 +233,8 @@ struct mtk_pll_data { |
| uint32_t pcw_chg_reg; |
| const struct mtk_pll_div_table *div_table; |
| const char *parent_name; |
| + uint32_t en_reg; |
| + uint8_t base_en_bit; |
| }; |
| |
| void mtk_clk_register_plls(struct device_node *node, |
| diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h |
| index f5625f4d9e6c67d33e1aed02332d0cd4d2520e18..afbc7df7fd8dfe8fdb0fdb543bb63ab6c1da9d64 100644 |
| --- a/drivers/clk/mediatek/clk-mux.h |
| +++ b/drivers/clk/mediatek/clk-mux.h |
| @@ -77,6 +77,21 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; |
| _width, _gate, _upd_ofs, _upd, \ |
| CLK_SET_RATE_PARENT) |
| |
| +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ |
| + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| + _upd_ofs, _upd, _flags) \ |
| + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ |
| + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| + 0, _upd_ofs, _upd, _flags, \ |
| + mtk_mux_clr_set_upd_ops) |
| + |
| +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ |
| + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ |
| + _upd_ofs, _upd) \ |
| + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ |
| + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ |
| + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT) |
| + |
| struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, |
| struct regmap *regmap, |
| spinlock_t *lock); |
| diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c |
| index f440f2cd0b6988d2fcc07f344e8d56edde4b617c..a723b012f9ea4918ec5a6e2b2a0a026058a453fa 100644 |
| --- a/drivers/clk/mediatek/clk-pll.c |
| +++ b/drivers/clk/mediatek/clk-pll.c |
| @@ -44,6 +44,7 @@ struct mtk_clk_pll { |
| void __iomem *tuner_en_addr; |
| void __iomem *pcw_addr; |
| void __iomem *pcw_chg_addr; |
| + void __iomem *en_addr; |
| const struct mtk_pll_data *data; |
| }; |
| |
| @@ -56,7 +57,10 @@ static int mtk_pll_is_prepared(struct clk_hw *hw) |
| { |
| struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); |
| |
| - return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; |
| + if (pll->en_addr) |
| + return (readl(pll->en_addr) & BIT(pll->data->base_en_bit)) != 0; |
| + else |
| + return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; |
| } |
| |
| static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, |
| @@ -251,6 +255,12 @@ static int mtk_pll_prepare(struct clk_hw *hw) |
| r |= pll->data->en_mask; |
| writel(r, pll->base_addr + REG_CON0); |
| |
| + if (pll->en_addr) { |
| + r = readl(pll->en_addr); |
| + r |= BIT(pll->data->base_en_bit); |
| + writel(r, pll->en_addr); |
| + } |
| + |
| __mtk_pll_tuner_enable(pll); |
| |
| udelay(20); |
| @@ -277,9 +287,16 @@ static void mtk_pll_unprepare(struct clk_hw *hw) |
| |
| __mtk_pll_tuner_disable(pll); |
| |
| - r = readl(pll->base_addr + REG_CON0); |
| - r &= ~CON0_BASE_EN; |
| - writel(r, pll->base_addr + REG_CON0); |
| + if (pll->en_addr) { |
| + r = readl(pll->en_addr); |
| + r &= ~BIT(pll->data->base_en_bit); |
| + writel(r, pll->en_addr); |
| + } |
| + else { |
| + r = readl(pll->base_addr + REG_CON0); |
| + r &= ~CON0_BASE_EN; |
| + writel(r, pll->base_addr + REG_CON0); |
| + } |
| |
| r = readl(pll->pwr_addr) | CON0_ISO_EN; |
| writel(r, pll->pwr_addr); |
| @@ -321,6 +338,8 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, |
| pll->tuner_addr = base + data->tuner_reg; |
| if (data->tuner_en_reg) |
| pll->tuner_en_addr = base + data->tuner_en_reg; |
| + if (data->en_reg) |
| + pll->en_addr = base + data->en_reg; |
| pll->hw.init = &init; |
| pll->data = data; |
| |
| diff --git a/drivers/clk/mediatek/clkdbg-mt8192.c b/drivers/clk/mediatek/clkdbg-mt8192.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..eba7ea85f893d9fdd2a7879a17adb3b580f1471e |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clkdbg-mt8192.c |
| @@ -0,0 +1,1267 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#include <linux/clk-provider.h> |
| +#include <linux/io.h> |
| +#include <linux/seq_file.h> |
| + |
| +#include "clkdbg.h" |
| + |
| +#define DUMP_INIT_STATE 0 |
| + |
| +/* |
| + * clkdbg dump_regs |
| + */ |
| + |
| +enum { |
| + topckgen, |
| + infracfg, |
| + pericfg, |
| + scpsys, |
| + apmixedsys, |
| + scp_adsp, |
| + imp_iic_wrap_c, |
| + audsys, |
| + imp_iic_wrap_e, |
| + imp_iic_wrap_s, |
| + imp_iic_wrap_ws, |
| + imp_iic_wrap_w, |
| + imp_iic_wrap_n, |
| + msdc_top, |
| + msdc, |
| + mfgcfg, |
| + mmsys, |
| + imgsys, |
| + imgsys2, |
| + vdecsys_soc, |
| + vdecsys, |
| + vencsys, |
| + apu_conn, |
| + apu_vcore, |
| + apu0, |
| + apu1, |
| + apu_mdla0, |
| + camsys, |
| + camsys_rawa, |
| + camsys_rawb, |
| + camsys_rawc, |
| + ipesys, |
| + mdpsys, |
| +}; |
| + |
| +#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name } |
| + |
| +/* |
| + * checkpatch.pl ERROR:COMPLEX_MACRO |
| + * |
| + * #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name) |
| + */ |
| + |
| +static struct regbase rb[] = { |
| + [topckgen] = REGBASE_V(0x10000000, topckgen), |
| + [infracfg] = REGBASE_V(0x10001000, infracfg), |
| + [pericfg] = REGBASE_V(0x10003000, pericfg), |
| + [scpsys] = REGBASE_V(0x10006000, scpsys), |
| + [apmixedsys] = REGBASE_V(0x1000c000, apmixedsys), |
| + [scp_adsp] = REGBASE_V(0x10720000, scp_adsp), |
| + [imp_iic_wrap_c] = REGBASE_V(0x11007000, imp_iic_wrap_c), |
| + [audsys] = REGBASE_V(0x11210000, audsys), |
| + [imp_iic_wrap_e] = REGBASE_V(0x11cb1000, imp_iic_wrap_e), |
| + [imp_iic_wrap_s] = REGBASE_V(0x11d03000, imp_iic_wrap_s), |
| + [imp_iic_wrap_ws] = REGBASE_V(0x11d23000, imp_iic_wrap_ws), |
| + [imp_iic_wrap_w] = REGBASE_V(0x11e01000, imp_iic_wrap_w), |
| + [imp_iic_wrap_n] = REGBASE_V(0x11f02000, imp_iic_wrap_n), |
| + [msdc_top] = REGBASE_V(0x11f10000, msdc_top), |
| + [msdc] = REGBASE_V(0x11f60000, msdc), |
| + [mfgcfg] = REGBASE_V(0x13fbf000, mfgcfg), |
| + [mmsys] = REGBASE_V(0x14000000, mmsys), |
| + [imgsys] = REGBASE_V(0x15020000, imgsys), |
| + [imgsys2] = REGBASE_V(0x15820000, imgsys2), |
| + [vdecsys_soc] = REGBASE_V(0x1600f000, vdecsys_soc), |
| + [vdecsys] = REGBASE_V(0x1602f000, vdecsys), |
| + [vencsys] = REGBASE_V(0x17000000, vencsys), |
| + [apu_conn] = REGBASE_V(0x19020000, apu_conn), |
| + [apu_vcore] = REGBASE_V(0x19029000, apu_vcore), |
| + [apu0] = REGBASE_V(0x19030000, apu0), |
| + [apu1] = REGBASE_V(0x19031000, apu1), |
| + [apu_mdla0] = REGBASE_V(0x19034000, apu_mdla0), |
| + [camsys] = REGBASE_V(0x1a000000, camsys), |
| + [camsys_rawa] = REGBASE_V(0x1a04f000, camsys_rawa), |
| + [camsys_rawb] = REGBASE_V(0x1a06f000, camsys_rawb), |
| + [camsys_rawc] = REGBASE_V(0x1a08f000, camsys_rawc), |
| + [ipesys] = REGBASE_V(0x1b000000, ipesys), |
| + [mdpsys] = REGBASE_V(0x1f000000, mdpsys), |
| +}; |
| + |
| +#define REGNAME(_base, _ofs, _name) \ |
| + { .base = &rb[_base], .ofs = _ofs, .name = #_name } |
| + |
| +static struct regname rn[] = { |
| + REGNAME(apmixedsys, 0x050, PLLON_CON0), |
| + REGNAME(apmixedsys, 0x054, PLLON_CON1), |
| + REGNAME(apmixedsys, 0x058, PLLON_CON2), |
| + REGNAME(apmixedsys, 0x05C, PLLON_CON3), |
| + REGNAME(apmixedsys, 0x208, ARMPLL_LL_CON0), |
| + REGNAME(apmixedsys, 0x20C, ARMPLL_LL_CON1), |
| + REGNAME(apmixedsys, 0x210, ARMPLL_LL_CON2), |
| + REGNAME(apmixedsys, 0x214, ARMPLL_LL_CON3), |
| + REGNAME(apmixedsys, 0x218, ARMPLL_BL0_CON0), |
| + REGNAME(apmixedsys, 0x21C, ARMPLL_BL0_CON1), |
| + REGNAME(apmixedsys, 0x220, ARMPLL_BL0_CON2), |
| + REGNAME(apmixedsys, 0x224, ARMPLL_BL0_CON3), |
| + REGNAME(apmixedsys, 0x228, ARMPLL_BL1_CON0), |
| + REGNAME(apmixedsys, 0x22C, ARMPLL_BL1_CON1), |
| + REGNAME(apmixedsys, 0x230, ARMPLL_BL1_CON2), |
| + REGNAME(apmixedsys, 0x234, ARMPLL_BL1_CON3), |
| + REGNAME(apmixedsys, 0x238, ARMPLL_BL2_CON0), |
| + REGNAME(apmixedsys, 0x23C, ARMPLL_BL2_CON1), |
| + REGNAME(apmixedsys, 0x240, ARMPLL_BL2_CON2), |
| + REGNAME(apmixedsys, 0x244, ARMPLL_BL2_CON3), |
| + REGNAME(apmixedsys, 0x248, ARMPLL_BL3_CON0), |
| + REGNAME(apmixedsys, 0x24C, ARMPLL_BL3_CON1), |
| + REGNAME(apmixedsys, 0x250, ARMPLL_BL3_CON2), |
| + REGNAME(apmixedsys, 0x254, ARMPLL_BL3_CON3), |
| + REGNAME(apmixedsys, 0x258, CCIPLL_CON0), |
| + REGNAME(apmixedsys, 0x25C, CCIPLL_CON1), |
| + REGNAME(apmixedsys, 0x260, CCIPLL_CON2), |
| + REGNAME(apmixedsys, 0x264, CCIPLL_CON3), |
| + REGNAME(apmixedsys, 0x268, MFGPLL_CON0), |
| + REGNAME(apmixedsys, 0x26c, MFGPLL_CON1), |
| + REGNAME(apmixedsys, 0x270, MFGPLL_CON2), |
| + REGNAME(apmixedsys, 0x274, MFGPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x308, UNIVPLL_CON0), |
| + REGNAME(apmixedsys, 0x30c, UNIVPLL_CON1), |
| + REGNAME(apmixedsys, 0x310, UNIVPLL_CON2), |
| + REGNAME(apmixedsys, 0x314, UNIVPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x318, APLL1_CON0), |
| + REGNAME(apmixedsys, 0x31c, APLL1_CON1), |
| + REGNAME(apmixedsys, 0x320, APLL1_CON2), |
| + REGNAME(apmixedsys, 0x328, APLL1_PWR_CON), |
| + REGNAME(apmixedsys, 0x32c, APLL2_CON0), |
| + REGNAME(apmixedsys, 0x330, APLL2_CON1), |
| + REGNAME(apmixedsys, 0x334, APLL2_CON2), |
| + REGNAME(apmixedsys, 0x33c, APLL2_PWR_CON), |
| + REGNAME(apmixedsys, 0x340, MAINPLL_CON0), |
| + REGNAME(apmixedsys, 0x344, MAINPLL_CON1), |
| + REGNAME(apmixedsys, 0x348, MAINPLL_CON2), |
| + REGNAME(apmixedsys, 0x34c, MAINPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x350, MSDCPLL_CON0), |
| + REGNAME(apmixedsys, 0x354, MSDCPLL_CON1), |
| + REGNAME(apmixedsys, 0x358, MSDCPLL_CON2), |
| + REGNAME(apmixedsys, 0x35c, MSDCPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x360, MMPLL_CON0), |
| + REGNAME(apmixedsys, 0x364, MMPLL_CON1), |
| + REGNAME(apmixedsys, 0x368, MMPLL_CON2), |
| + REGNAME(apmixedsys, 0x36c, MMPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x370, ADSPPLL_CON0), |
| + REGNAME(apmixedsys, 0x374, ADSPPLL_CON1), |
| + REGNAME(apmixedsys, 0x378, ADSPPLL_CON2), |
| + REGNAME(apmixedsys, 0x37c, ADSPPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x380, TVDPLL_CON0), |
| + REGNAME(apmixedsys, 0x384, TVDPLL_CON1), |
| + REGNAME(apmixedsys, 0x388, TVDPLL_CON2), |
| + REGNAME(apmixedsys, 0x38c, TVDPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x390, MPLL_CON0), |
| + REGNAME(apmixedsys, 0x394, MPLL_CON1), |
| + REGNAME(apmixedsys, 0x39C, MPLL_CON3), |
| + REGNAME(apmixedsys, 0x3a0, APUPLL_CON0), |
| + REGNAME(apmixedsys, 0x3a4, APUPLL_CON1), |
| + REGNAME(apmixedsys, 0x3a8, APUPLL_CON2), |
| + REGNAME(apmixedsys, 0x3ac, APUPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x3b4, NPUPLL_CON0), |
| + REGNAME(apmixedsys, 0x3b8, NPUPLL_CON1), |
| + REGNAME(apmixedsys, 0x3bc, NPUPLL_CON2), |
| + REGNAME(apmixedsys, 0x3c0, NPUPLL_PWR_CON), |
| + REGNAME(apmixedsys, 0x3c4, USBPLL_CON0), |
| + REGNAME(apmixedsys, 0x3c8, USBPLL_CON1), |
| + REGNAME(apmixedsys, 0x3cc, USBPLL_CON2), |
| + REGNAME(apmixedsys, 0x3cc, USBPLL_PWR_CON), |
| + REGNAME(topckgen, 0x010, CLK_CFG_0), |
| + REGNAME(topckgen, 0x020, CLK_CFG_1), |
| + REGNAME(topckgen, 0x030, CLK_CFG_2), |
| + REGNAME(topckgen, 0x040, CLK_CFG_3), |
| + REGNAME(topckgen, 0x050, CLK_CFG_4), |
| + REGNAME(topckgen, 0x060, CLK_CFG_5), |
| + REGNAME(topckgen, 0x070, CLK_CFG_6), |
| + REGNAME(topckgen, 0x080, CLK_CFG_7), |
| + REGNAME(topckgen, 0x090, CLK_CFG_8), |
| + REGNAME(topckgen, 0x0a0, CLK_CFG_9), |
| + REGNAME(topckgen, 0x0b0, CLK_CFG_10), |
| + REGNAME(topckgen, 0x0c0, CLK_CFG_11), |
| + REGNAME(topckgen, 0x0d0, CLK_CFG_12), |
| + REGNAME(topckgen, 0x0e0, CLK_CFG_13), |
| + REGNAME(topckgen, 0x0f0, CLK_CFG_14), |
| + REGNAME(topckgen, 0x100, CLK_CFG_15), |
| + REGNAME(topckgen, 0x110, CLK_CFG_16), |
| + REGNAME(topckgen, 0x320, CLK_AUDDIV_0), |
| + REGNAME(scpsys, 0x0000, POWERON_CONFIG_EN), |
| + REGNAME(scpsys, 0x016C, PWR_STATUS), |
| + REGNAME(scpsys, 0x0170, PWR_STATUS_2ND), |
| + REGNAME(scpsys, 0x0178, OTHER_PWR_STATUS), |
| + REGNAME(scpsys, 0x300, MD1_PWR_CON), |
| + REGNAME(scpsys, 0x304, CONN_PWR_CON), |
| + REGNAME(scpsys, 0x308, MFG0_PWR_CON), |
| + REGNAME(scpsys, 0x30C, MFG1_PWR_CON), |
| + REGNAME(scpsys, 0x310, MFG2_PWR_CON), |
| + REGNAME(scpsys, 0x314, MFG3_PWR_CON), |
| + REGNAME(scpsys, 0x318, MFG4_PWR_CON), |
| + REGNAME(scpsys, 0x31C, MFG5_PWR_CON), |
| + REGNAME(scpsys, 0x320, MFG6_PWR_CON), |
| + REGNAME(scpsys, 0x324, IFR_PWR_CON), |
| + REGNAME(scpsys, 0x328, IFR_SUB_PWR_CON), |
| + REGNAME(scpsys, 0x32C, DPY_PWR_CON), |
| + REGNAME(scpsys, 0x330, ISP_PWR_CON), |
| + REGNAME(scpsys, 0x334, ISP2_PWR_CON), |
| + REGNAME(scpsys, 0x338, IPE_PWR_CON), |
| + REGNAME(scpsys, 0x33C, VDE_PWR_CON), |
| + REGNAME(scpsys, 0x340, VDE2_PWR_CON), |
| + REGNAME(scpsys, 0x344, VEN_PWR_CON), |
| + REGNAME(scpsys, 0x348, VEN_CORE1_PWR_CON), |
| + REGNAME(scpsys, 0x34C, MDP_PWR_CON), |
| + REGNAME(scpsys, 0x350, DIS_PWR_CON), |
| + REGNAME(scpsys, 0x354, AUDIO_PWR_CON), |
| + REGNAME(scpsys, 0x358, ADSP_PWR_CON), |
| + REGNAME(scpsys, 0x35C, CAM_PWR_CON), |
| + REGNAME(scpsys, 0x360, CAM_RAWA_PWR_CON), |
| + REGNAME(scpsys, 0x364, CAM_RAWB_PWR_CON), |
| + REGNAME(scpsys, 0x368, CAM_RAWC_PWR_CON), |
| + REGNAME(scpsys, 0x3AC, DP_TX_PWR_CON), |
| + REGNAME(scpsys, 0x3C4, DPY2_PWR_CON), |
| + REGNAME(scpsys, 0x398, MD_EXT_BUCK_ISO_CON), |
| + REGNAME(scpsys, 0x39C, EXT_BUCK_ISO), |
| + REGNAME(scpsys, 0x3A4, MSDC_PWR_CON), |
| + REGNAME(infracfg, 0x090, MODULE_SW_CG_0), |
| + REGNAME(infracfg, 0x094, MODULE_SW_CG_1), |
| + REGNAME(infracfg, 0x0ac, MODULE_SW_CG_2), |
| + REGNAME(infracfg, 0x0c8, MODULE_SW_CG_3), |
| + REGNAME(infracfg, 0x0d8, MODULE_SW_CG_5), |
| + REGNAME(infracfg, 0x0e8, MODULE_SW_CG_4), |
| + REGNAME(pericfg, 0x20c, PERIAXI_SI0_CTL), |
| + REGNAME(scp_adsp, 0x180, AUDIODSP_CK_CG), |
| + REGNAME(imp_iic_wrap_c, 0xe00, AP_CLOCK_CG_RO_CEN), |
| + REGNAME(audsys, 0x000, AUDIO_TOP_CON0), |
| + REGNAME(audsys, 0x004, AUDIO_TOP_CON1), |
| + REGNAME(audsys, 0x008, AUDIO_TOP_CON2), |
| + REGNAME(imp_iic_wrap_e, 0xe00, AP_CLOCK_CG_RO_EST), |
| + REGNAME(imp_iic_wrap_s, 0xe00, AP_CLOCK_CG_RO_SOU), |
| + REGNAME(imp_iic_wrap_ws, 0xe00, AP_CLOCK_CG_RO_WEST_SOU), |
| + REGNAME(imp_iic_wrap_w, 0xe00, AP_CLOCK_CG_RO_WST), |
| + REGNAME(imp_iic_wrap_n, 0xe00, AP_CLOCK_CG_RO_NOR), |
| + REGNAME(msdc_top, 0x000, MSDC_CTL_CKEN), |
| + REGNAME(msdc, 0x0b4, PATCH_BIT1), |
| + REGNAME(mfgcfg, 0x000, MFG_CG), |
| + REGNAME(mmsys, 0x100, MMSYS_CG_CON0), |
| + REGNAME(mmsys, 0x110, MMSYS_CG_CON1), |
| + REGNAME(mmsys, 0x1a0, MMSYS_CG_CON2), |
| + REGNAME(imgsys, 0x000, IMG1_CG_CON), |
| + REGNAME(imgsys2, 0x000, IMG2_CG_CON), |
| + REGNAME(vdecsys_soc, 0x000, VDEC_CKEN), |
| + REGNAME(vdecsys_soc, 0x008, LARB_CKEN_CON), |
| + REGNAME(vdecsys_soc, 0x200, LAT_CKEN), |
| + REGNAME(vdecsys, 0x000, VDEC_CKEN), |
| + REGNAME(vdecsys, 0x008, LARB_CKEN_CON), |
| + REGNAME(vdecsys, 0x200, LAT_CKEN), |
| + REGNAME(vencsys, 0x000, VENCSYS_CG), |
| + REGNAME(apu_conn, 0x000, APU_CONN_CG), |
| + REGNAME(apu_vcore, 0x000, APUSYS_VCORE_CG), |
| + REGNAME(apu0, 0x100, CORE0_CG), |
| + REGNAME(apu1, 0x100, CORE1_CG), |
| + REGNAME(apu_mdla0, 0x000, MDLA_CG), |
| + REGNAME(camsys, 0x000, CAMSYS_CG_CON), |
| + REGNAME(camsys_rawa, 0x000, CAMSYS_RAWA_CG_CON), |
| + REGNAME(camsys_rawb, 0x000, CAMSYS_RAWB_CG_CON), |
| + REGNAME(camsys_rawc, 0x000, CAMSYS_RAWC_CG_CON), |
| + REGNAME(ipesys, 0x000, IMG_CG), |
| + REGNAME(mdpsys, 0x100, MDPSYS_CG_CON0), |
| + REGNAME(mdpsys, 0x120, MDPSYS_CG_CON2), |
| + {} |
| +}; |
| + |
| +static const struct regname *get_all_regnames(void) |
| +{ |
| + return rn; |
| +} |
| + |
| +static void __init init_regbase(void) |
| +{ |
| + size_t i; |
| + |
| + for (i = 0; i < ARRAY_SIZE(rb); i++) |
| + rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE); |
| +} |
| + |
| +/* |
| + * clkdbg fmeter |
| + */ |
| + |
| +#include <linux/delay.h> |
| + |
| +#define clk_readl(addr) readl(addr) |
| +#define clk_writel(addr, val) \ |
| + do { writel(val, addr); wmb(); } while (0) /* sync write */ |
| + |
| +#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n } |
| + |
| +static const struct fmeter_clk fclks[] = { |
| + FMCLK(CKGEN, 1, "hd_faxi_ck"), |
| + FMCLK(CKGEN, 2, "hg_fspm_ck"), |
| + FMCLK(CKGEN, 3, "hf_fscp_ck"), |
| + FMCLK(CKGEN, 4, "hd_fbus_aximem_ck"), |
| + FMCLK(CKGEN, 5, "hf_fdisp_ck"), |
| + FMCLK(CKGEN, 6, "hf_fmdp_ck"), |
| + FMCLK(CKGEN, 7, "hf_fimg1_ck"), |
| + FMCLK(CKGEN, 8, "hf_fimg2_ck"), |
| + FMCLK(CKGEN, 9, "hf_fipe_ck"), |
| + FMCLK(CKGEN, 10, "hf_fdpe_ck"), |
| + FMCLK(CKGEN, 11, "hf_fcam_ck"), |
| + FMCLK(CKGEN, 12, "hf_fccu_ck"), |
| + FMCLK(CKGEN, 13, "hf_fdsp_ck"), |
| + FMCLK(CKGEN, 14, "hf_fdsp1_ck"), |
| + FMCLK(CKGEN, 15, "hf_fdsp2_ck"), |
| + FMCLK(CKGEN, 16, "hf_fdsp5_ck"), |
| + FMCLK(CKGEN, 17, "hf_fdsp7_ck"), |
| + FMCLK(CKGEN, 18, "hf_fipu_if_ck"), |
| + FMCLK(CKGEN, 19, "hf_fmfg_ck"), |
| + FMCLK(CKGEN, 20, "f_fcamtg_ck"), |
| + FMCLK(CKGEN, 21, "f_fcamtg2_ck"), |
| + FMCLK(CKGEN, 22, "f_fcamtg3_ck"), |
| + FMCLK(CKGEN, 23, "f_fcamtg4_ck"), |
| + FMCLK(CKGEN, 24, "f_fcamtg5_ck"), |
| + FMCLK(CKGEN, 25, "f_fcamtg6_ck"), |
| + FMCLK(CKGEN, 26, "f_fuart_ck"), |
| + FMCLK(CKGEN, 27, "hf_fspi_ck"), |
| + FMCLK(CKGEN, 28, "hf_fmsdc50_0_hclk_ck"), |
| + FMCLK(CKGEN, 29, "hf_fmsdc50_0_ck"), |
| + FMCLK(CKGEN, 30, "hf_fmsdc30_1_ck"), |
| + FMCLK(CKGEN, 31, "hf_fmsdc30_2_ck"), |
| + FMCLK(CKGEN, 32, "hf_faudio_ck"), |
| + FMCLK(CKGEN, 33, "hf_faud_intbus_ck"), |
| + FMCLK(CKGEN, 34, "f_fpwrap_ulposc_ck"), |
| + FMCLK(CKGEN, 35, "hf_fatb_ck"), |
| + FMCLK(CKGEN, 36, "hf_fpwrmcu_ck"), |
| + FMCLK(CKGEN, 37, "hf_fdpi_ck"), |
| + FMCLK(CKGEN, 38, "hf_fscam_ck"), |
| + FMCLK(CKGEN, 39, "f_fdisp_pwm_ck"), |
| + FMCLK(CKGEN, 40, "f_fusb_top_ck"), |
| + FMCLK(CKGEN, 41, "f_fssusb_xhci_ck"), |
| + FMCLK(CKGEN, 42, "f_fi2c_ck"), |
| + FMCLK(CKGEN, 43, "f_fseninf_ck"), |
| + FMCLK(CKGEN, 44, "f_fseninf1_ck"), |
| + FMCLK(CKGEN, 45, "f_fseninf2_ck"), |
| + FMCLK(CKGEN, 46, "f_fseninf3_ck"), |
| + FMCLK(CKGEN, 47, "hf_ftl_ck"), |
| + FMCLK(CKGEN, 48, "hf_fdxcc_ck"), |
| + FMCLK(CKGEN, 49, "hf_faud_engen1_ck"), |
| + FMCLK(CKGEN, 50, "hf_faud_engen2_ck"), |
| + FMCLK(CKGEN, 51, "hf_faes_ufsfde_ck"), |
| + FMCLK(CKGEN, 52, "hf_fufs_ck"), |
| + FMCLK(CKGEN, 53, "hf_faud_1_ck"), |
| + FMCLK(CKGEN, 54, "hf_faud_2_ck"), |
| + FMCLK(CKGEN, 55, "hf_fadsp_ck"), |
| + FMCLK(CKGEN, 56, "hf_fdpmaif_main_ck"), |
| + FMCLK(CKGEN, 57, "hf_fvenc_ck"), |
| + FMCLK(CKGEN, 58, "hf_fvdec_ck"), |
| + FMCLK(CKGEN, 59, "hf_fcamtm_ck"), |
| + FMCLK(CKGEN, 60, "hf_fpwm_ck"), |
| + FMCLK(CKGEN, 61, "hf_faudio_h_ck"), |
| + FMCLK(CKGEN, 62, "hf_fspmi_mst_ck"), |
| + FMCLK(CKGEN, 63, "hg_fdvfsrc_ck"), |
| + FMCLK(ABIST, 1, "AD_ADSPPLL_CK"), |
| + FMCLK(ABIST, 2, "AD_APLL1_CK"), |
| + FMCLK(ABIST, 3, "AD_APLL2_CK"), |
| + FMCLK(ABIST, 4, "AD_APPLLGP_MON_FM_CK"), |
| + FMCLK(ABIST, 5, "AD_APUPLL_CK"), |
| + FMCLK(ABIST, 6, "AD_ARMPLL_BL_CK"), |
| + FMCLK(ABIST, 7, "AD_NPUPLL_CK"), |
| + FMCLK(ABIST, 10, "AD_ARMPLL_LL_CK"), |
| + FMCLK(ABIST, 11, "AD_CCIPLL_CK"), |
| + FMCLK(ABIST, 12, "AD_CSI0A_CDPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 13, "AD_CSI0B_CDPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 14, "AD_CSI1A_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 15, "AD_CSI1B_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 16, "AD_CSI2A_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 17, "AD_CSI2B_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 18, "AD_CSI3A_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 19, "AD_CSI3B_DPHY_DELAYCAL_CK"), |
| + FMCLK(ABIST, 20, "AD_DSI0_LNTC_DSICLK"), |
| + FMCLK(ABIST, 21, "AD_DSI0_MPPLL_TST_CK"), |
| + FMCLK(ABIST, 23, "mfgpll_ck"), |
| + FMCLK(ABIST, 24, "AD_MAINPLL_CK"), |
| + FMCLK(ABIST, 25, "AD_MDPLL_FS26M_CK"), |
| + FMCLK(ABIST, 26, "AD_MGPLL_CK"), |
| + FMCLK(ABIST, 27, "AD_MPLL_CK"), |
| + FMCLK(ABIST, 28, "AD_MMPLL_D3_CK"), |
| + FMCLK(ABIST, 29, "AD_MPLL_CK"), |
| + FMCLK(ABIST, 30, "AD_MSDCPLL_CK"), |
| + FMCLK(ABIST, 31, "AD_RCLRPLL_DIV4_CK_ch2"), |
| + FMCLK(ABIST, 32, "AD_RCLRPLL_DIV4_CK_ch13"), |
| + FMCLK(ABIST, 33, "AD_RPHYPLL_DIV4_CK_ch2"), |
| + FMCLK(ABIST, 34, "AD_RPHYPLL_DIV4_CK_ch13"), |
| + FMCLK(ABIST, 35, "AD_TVDPLL_CK"), |
| + FMCLK(ABIST, 36, "AD_ULPOSC2_CK"), |
| + FMCLK(ABIST, 37, "AD_ULPOSC_CK"), |
| + FMCLK(ABIST, 38, "AD_UNIVPLL_CK"), |
| + FMCLK(ABIST, 39, "AD_USB20_192M_CK"), |
| + FMCLK(ABIST, 40, "AD_USBPLL_192M_CK"), |
| + FMCLK(ABIST, 41, "UFS_MP_CLK2FREQ"), |
| + FMCLK(ABIST, 42, "ad_wbg_dig_bpll_ck"), |
| + FMCLK(ABIST, 43, "ad_wbg_dig_wpll_ck960"), |
| + FMCLK(ABIST, 44, "fmem_ck_aft_dcm_ch0"), |
| + FMCLK(ABIST, 45, "fmem_ck_aft_dcm_ch1"), |
| + FMCLK(ABIST, 46, "fmem_ck_aft_dcm_ch2"), |
| + FMCLK(ABIST, 47, "fmem_ck_aft_dcm_ch3"), |
| + FMCLK(ABIST, 48, "fmem_ck_bfe_dcm_ch0"), |
| + FMCLK(ABIST, 49, "fmem_ck_bfe_dcm_ch1"), |
| + FMCLK(ABIST, 50, "hd_466m_fmem_ck_infrasys"), |
| + FMCLK(ABIST, 51, "mcusys_arm_clk_out_all"), |
| + FMCLK(ABIST, 52, "msdc01_in_ck"), |
| + FMCLK(ABIST, 53, "msdc02_in_ck"), |
| + FMCLK(ABIST, 54, "msdc11_in_ck"), |
| + FMCLK(ABIST, 55, "msdc12_in_ck"), |
| + FMCLK(ABIST, 56, "msdc21_in_ck"), |
| + FMCLK(ABIST, 57, "msdc22_in_ck"), |
| + FMCLK(ABIST, 58, "rtc32k_ck_i"), |
| + FMCLK(ABIST, 60, "ckmon1_ck"), |
| + FMCLK(ABIST, 61, "ckmon2_ck"), |
| + FMCLK(ABIST, 62, "ckmon3_ck"), |
| + FMCLK(ABIST, 63, "ckmon4_ck"), |
| + {} |
| +}; |
| + |
| +#define CLK_MISC_CFG_0 (rb[topckgen].virt + 0x140) |
| +#define CLK_DBG_CFG (rb[topckgen].virt + 0x17C) |
| +#define CLK26CALI_0 (rb[topckgen].virt + 0x220) |
| +#define CLK26CALI_1 (rb[topckgen].virt + 0x224) |
| + |
| +static unsigned int mt_get_ckgen_freq(unsigned int ID) |
| +{ |
| + int output = 0, i = 0; |
| + unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0; |
| + |
| + clk_dbg_cfg = clk_readl(CLK_DBG_CFG); |
| + clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFFFC0FC)|(ID << 8)|(0x1)); |
| + |
| + clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0); |
| + clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF)); |
| + |
| + clk26cali_1 = clk_readl(CLK26CALI_1); |
| + clk_writel(CLK26CALI_0, 0x1000); |
| + clk_writel(CLK26CALI_0, 0x1010); |
| + |
| + /* wait frequency meter finish */ |
| + while (clk_readl(CLK26CALI_0) & 0x10) { |
| + udelay(10); |
| + i++; |
| + if (i > 20) |
| + break; |
| + } |
| + /* illegal pass */ |
| + if (i == 0) { |
| + clk_writel(CLK26CALI_0, 0x0000); |
| + //re-trigger |
| + clk_writel(CLK26CALI_0, 0x1000); |
| + clk_writel(CLK26CALI_0, 0x1010); |
| + while (clk_readl(CLK26CALI_0) & 0x10) { |
| + udelay(10); |
| + i++; |
| + if (i > 20) |
| + break; |
| + } |
| + } |
| + |
| + temp = clk_readl(CLK26CALI_1) & 0xFFFF; |
| + |
| + output = (temp * 26000) / 1024; |
| + |
| + clk_writel(CLK_DBG_CFG, clk_dbg_cfg); |
| + clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0); |
| + /*clk_writel(CLK26CALI_0, clk26cali_0);*/ |
| + /*clk_writel(CLK26CALI_1, clk26cali_1);*/ |
| + |
| + clk_writel(CLK26CALI_0, 0x0000); |
| + /*print("ckgen meter[%d] = %d Khz\n", ID, output);*/ |
| + if (i > 20) |
| + return 0; |
| + else |
| + return output; |
| +} |
| + |
| +static unsigned int mt_get_abist_freq(unsigned int ID) |
| +{ |
| + int output = 0, i = 0; |
| + unsigned int temp, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1 = 0; |
| + |
| + clk_dbg_cfg = clk_readl(CLK_DBG_CFG); |
| + clk_writel(CLK_DBG_CFG, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16)); |
| + |
| + clk_misc_cfg_0 = clk_readl(CLK_MISC_CFG_0); |
| + clk_writel(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (1 << 24)); |
| + |
| + clk26cali_1 = clk_readl(CLK26CALI_1); |
| + |
| + clk_writel(CLK26CALI_0, 0x1000); |
| + clk_writel(CLK26CALI_0, 0x1010); |
| + |
| + /* wait frequency meter finish */ |
| + while (clk_readl(CLK26CALI_0) & 0x10) { |
| + udelay(10); |
| + i++; |
| + if (i > 20) |
| + break; |
| + } |
| + /* illegal pass */ |
| + if (i == 0) { |
| + clk_writel(CLK26CALI_0, 0x0000); |
| + //re-trigger |
| + clk_writel(CLK26CALI_0, 0x1000); |
| + clk_writel(CLK26CALI_0, 0x1010); |
| + while (clk_readl(CLK26CALI_0) & 0x10) { |
| + udelay(10); |
| + i++; |
| + if (i > 20) |
| + break; |
| + } |
| + } |
| + |
| + temp = clk_readl(CLK26CALI_1) & 0xFFFF; |
| + |
| + output = (temp * 26000) / 1024; |
| + |
| + clk_writel(CLK_DBG_CFG, clk_dbg_cfg); |
| + clk_writel(CLK_MISC_CFG_0, clk_misc_cfg_0); |
| + /*clk_writel(CLK26CALI_0, clk26cali_0);*/ |
| + /*clk_writel(CLK26CALI_1, clk26cali_1);*/ |
| + clk_writel(CLK26CALI_0, 0x0000); |
| + /*pr_debug("%s = %d Khz\n", abist_array[ID-1], output);*/ |
| + if (i > 20) |
| + return 0; |
| + else |
| + return (output * 2); |
| +} |
| + |
| +static u32 fmeter_freq_op(const struct fmeter_clk *fclk) |
| +{ |
| + if (fclk->type == ABIST) |
| + return mt_get_abist_freq(fclk->id); |
| + else if (fclk->type == CKGEN) |
| + return mt_get_ckgen_freq(fclk->id); |
| + return 0; |
| +} |
| + |
| +static const struct fmeter_clk *get_all_fmeter_clks(void) |
| +{ |
| + return fclks; |
| +} |
| + |
| +/* |
| + * clkdbg dump_state |
| + */ |
| + |
| +static const char * const *get_all_clk_names(void) |
| +{ |
| + static const char * const clks[] = { |
| + "clk26m", |
| + "clk32k", |
| + "mainpll", |
| + "univpll", |
| + "usbpll", |
| + "msdcpll", |
| + "mmpll", |
| + "adsppll", |
| + "mfgpll", |
| + "tvdpll", |
| + "apll1", |
| + "apll2", |
| + "apupll", |
| + "npupll", |
| + "mipid26m", |
| + "axi_sel", |
| + "spm_sel", |
| + "scp_sel", |
| + "bus_aximem_sel", |
| + "disp_sel", |
| + "mdp_sel", |
| + "img1_sel", |
| + "img2_sel", |
| + "ipe_sel", |
| + "dpe_sel", |
| + "cam_sel", |
| + "ccu_sel", |
| + "dsp_sel", |
| + "dsp1_sel", |
| + "dsp1_npupll_sel", |
| + "dsp2_sel", |
| + "dsp2_npupll_sel", |
| + "dsp5_sel", |
| + "dsp5_apupll_sel", |
| + "dsp7_sel", |
| + "ipu_if_sel", |
| + "mfg_ref_sel", |
| + "mfg_pll_sel", |
| + "camtg_sel", |
| + "camtg2_sel", |
| + "camtg3_sel", |
| + "camtg4_sel", |
| + "camtg5_sel", |
| + "camtg6_sel", |
| + "uart_sel", |
| + "spi_sel", |
| + "msdc50_0_h_sel", |
| + "msdc50_0_sel", |
| + "msdc30_1_sel", |
| + "msdc30_2_sel", |
| + "audio_sel", |
| + "aud_intbus_sel", |
| + "pwrap_ulposc_sel", |
| + "atb_sel", |
| + "sspm_sel", |
| + "dpi_sel", |
| + "scam_sel", |
| + "disp_pwm_sel", |
| + "usb_top_sel", |
| + "ssusb_xhci_sel", |
| + "i2c_sel", |
| + "seninf_sel", |
| + "seninf1_sel", |
| + "seninf2_sel", |
| + "seninf3_sel", |
| + "tl_sel", |
| + "dxcc_sel", |
| + "aud_engen1_sel", |
| + "aud_engen2_sel", |
| + "aes_ufsfde_sel", |
| + "ufs_sel", |
| + "aud_1_sel", |
| + "aud_2_sel", |
| + "adsp_sel", |
| + "dpmaif_main_sel", |
| + "venc_sel", |
| + "vdec_sel", |
| + "camtm_sel", |
| + "pwm_sel", |
| + "audio_h_sel", |
| + "spmi_mst_sel", |
| + "dvfsrc_sel", |
| + "aes_msdcfde_sel", |
| + "mcupm_sel", |
| + "sflash_sel", |
| + "apll_i2s0_m_sel", |
| + "apll_i2s1_m_sel", |
| + "apll_i2s2_m_sel", |
| + "apll_i2s3_m_sel", |
| + "apll_i2s4_m_sel", |
| + "apll_i2s5_m_sel", |
| + "apll_i2s6_m_sel", |
| + "apll_i2s7_m_sel", |
| + "apll_i2s8_m_sel", |
| + "apll_i2s9_m_sel", |
| + "mainpll_d3", |
| + "mainpll_d4", |
| + "mainpll_d4_d2", |
| + "mainpll_d4_d4", |
| + "mainpll_d4_d8", |
| + "mainpll_d4_d16", |
| + "mainpll_d5", |
| + "mainpll_d5_d2", |
| + "mainpll_d5_d4", |
| + "mainpll_d5_d8", |
| + "mainpll_d6", |
| + "mainpll_d6_d2", |
| + "mainpll_d6_d4", |
| + "mainpll_d7", |
| + "mainpll_d7_d2", |
| + "mainpll_d7_d4", |
| + "mainpll_d7_d8", |
| + "univpll_d3", |
| + "univpll_d4", |
| + "univpll_d4_d2", |
| + "univpll_d4_d4", |
| + "univpll_d4_d8", |
| + "univpll_d5", |
| + "univpll_d5_d2", |
| + "univpll_d5_d4", |
| + "univpll_d5_d8", |
| + "univpll_d6", |
| + "univpll_d6_d2", |
| + "univpll_d6_d4", |
| + "univpll_d6_d8", |
| + "univpll_d6_d16", |
| + "univpll_d7", |
| + "apll1_ck", |
| + "apll1_d2", |
| + "apll1_d4", |
| + "apll1_d8", |
| + "apll2_ck", |
| + "apll2_d2", |
| + "apll2_d4", |
| + "apll2_d8", |
| + "mmpll_d4", |
| + "mmpll_d4_d2", |
| + "mmpll_d5", |
| + "mmpll_d5_d2", |
| + "mmpll_d6", |
| + "mmpll_d6_d2", |
| + "mmpll_d7", |
| + "mmpll_d9", |
| + "apupll_ck", |
| + "npupll_ck", |
| + "tvdpll_ck", |
| + "tvdpll_d2", |
| + "tvdpll_d4", |
| + "tvdpll_d8", |
| + "tvdpll_d16", |
| + "msdcpll_ck", |
| + "msdcpll_d2", |
| + "msdcpll_d4", |
| + "ulposc", |
| + "osc_d2", |
| + "osc_d4", |
| + "osc_d8", |
| + "osc_d10", |
| + "osc_d16", |
| + "osc_d20", |
| + "csw_f26m_d2", |
| + "adsppll_ck", |
| + "univpll_192m", |
| + "univpll_192m_d2", |
| + "univpll_192m_d4", |
| + "univpll_192m_d8", |
| + "univpll_192m_d16", |
| + "univpll_192m_d32", |
| + "apll12_div0", |
| + "apll12_div1", |
| + "apll12_div2", |
| + "apll12_div3", |
| + "apll12_div4", |
| + "apll12_divb", |
| + "apll12_div5", |
| + "apll12_div6", |
| + "apll12_div7", |
| + "apll12_div8", |
| + "apll12_div9", |
| + "infra_pmic_tmr", |
| + "infra_pmic_ap", |
| + "infra_pmic_md", |
| + "infra_pmic_conn", |
| + "infra_scpsys", |
| + "infra_sej", |
| + "infra_apxgpt", |
| + "infra_mcupm", |
| + "infra_gce", |
| + "infra_gce2", |
| + "infra_therm", |
| + "infra_i2c0", |
| + "infra_ap_dma_pseudo", |
| + "infra_i2c2", |
| + "infra_i2c3", |
| + "infra_pwm_h", |
| + "infra_pwm1", |
| + "infra_pwm2", |
| + "infra_pwm3", |
| + "infra_pwm4", |
| + "infra_pwm", |
| + "infra_uart0", |
| + "infra_uart1", |
| + "infra_uart2", |
| + "infra_uart3", |
| + "infra_gce_26m", |
| + "infra_cq_dma_fpc", |
| + "infra_btif", |
| + "infra_spi0", |
| + "infra_msdc0", |
| + "infra_msdc1", |
| + "infra_msdc2", |
| + "infra_msdc0_src", |
| + "infra_dvfsrc", |
| + "infra_gcpu", |
| + "infra_trng", |
| + "infra_auxadc", |
| + "infra_cpum", |
| + "infra_ccif1_ap", |
| + "infra_ccif1_md", |
| + "infra_auxadc_md", |
| + "infra_pcie_tl_26m", |
| + "infra_msdc1_src", |
| + "infra_msdc2_src", |
| + "infra_pcie_tl_96m", |
| + "infra_pcie_pl_p_250m", |
| + "infra_device_apc", |
| + "infra_ccif_ap", |
| + "infra_debugsys", |
| + "infra_audio", |
| + "infra_ccif_md", |
| + "infra_dxcc_sec_core", |
| + "infra_dxcc_ao", |
| + "infra_dbg_trace", |
| + "infra_devmpu_b", |
| + "infra_dramc_f26m", |
| + "infra_irtx", |
| + "infra_ssusb", |
| + "infra_disp_pwm", |
| + "infra_cldma_b", |
| + "infra_audio_26m_b", |
| + "infra_modem_temp_share", |
| + "infra_spi1", |
| + "infra_i2c4", |
| + "infra_spi2", |
| + "infra_spi3", |
| + "infra_unipro_sys", |
| + "infra_unipro_tick", |
| + "infra_ufs_mp_sap_b", |
| + "infra_md32_b", |
| + "infra_sspm", |
| + "infra_unipro_mbist", |
| + "infra_sspm_bus_h", |
| + "infra_i2c5", |
| + "infra_i2c5_arbiter", |
| + "infra_i2c5_imm", |
| + "infra_i2c1_arbiter", |
| + "infra_i2c1_imm", |
| + "infra_i2c2_arbiter", |
| + "infra_i2c2_imm", |
| + "infra_spi4", |
| + "infra_spi5", |
| + "infra_cq_dma", |
| + "infra_ufs", |
| + "infra_aes_ufsfde", |
| + "infra_ufs_tick", |
| + "infra_ssusb_xhci", |
| + "infra_msdc0_self", |
| + "infra_msdc1_self", |
| + "infra_msdc2_self", |
| + "infra_sspm_26m_self", |
| + "infra_sspm_32k_self", |
| + "infra_ufs_axi", |
| + "infra_i2c6", |
| + "infra_ap_msdc0", |
| + "infra_md_msdc0", |
| + "infra_ccif5_ap", |
| + "infra_ccif5_md", |
| + "infra_pcie_top_h_133m", |
| + "infra_flashif_top_h_133m", |
| + "infra_pcie_peri_26m", |
| + "infra_ccif2_ap", |
| + "infra_ccif2_md", |
| + "infra_ccif3_ap", |
| + "infra_ccif3_md", |
| + "infra_sej_f13m", |
| + "infra_aes", |
| + "infra_i2c7", |
| + "infra_i2c8", |
| + "infra_fbist2fpc", |
| + "infra_device_apc_sync", |
| + "infra_dpmaif_main", |
| + "infra_pcie_tl_32k", |
| + "infra_ccif4_ap", |
| + "infra_ccif4_md", |
| + "infra_spi6", |
| + "infra_spi7", |
| + "infra_133m", |
| + "infra_66m", |
| + "infra_66m_peri_bus", |
| + "infra_free_dcm_133m", |
| + "infra_free_dcm_66m", |
| + "infra_peri_bus_dcm_133m", |
| + "infra_peri_bus_dcm_66m", |
| + "infra_flashif_peri_26m", |
| + "infra_flashif_fsflash", |
| + "infra_ap_dma", |
| + "peri_periaxi", |
| + "scp_adsp_audiodsp", |
| + "imp_iic_wrap_c_i2c10", |
| + "imp_iic_wrap_c_i2c11", |
| + "imp_iic_wrap_c_i2c12", |
| + "imp_iic_wrap_c_i2c13", |
| + "aud_afe", |
| + "aud_22m", |
| + "aud_24m", |
| + "aud_apll2_tuner", |
| + "aud_apll_tuner", |
| + "aud_tdm", |
| + "aud_adc", |
| + "aud_dac", |
| + "aud_dac_predis", |
| + "aud_tml", |
| + "aud_nle", |
| + "aud_i2s1_b", |
| + "aud_i2s2_b", |
| + "aud_i2s3_b", |
| + "aud_i2s4_b", |
| + "aud_connsys_i2s_asrc", |
| + "aud_general1_asrc", |
| + "aud_general2_asrc", |
| + "aud_dac_hires", |
| + "aud_adc_hires", |
| + "aud_adc_hires_tml", |
| + "aud_adda6_adc", |
| + "aud_adda6_adc_hires", |
| + "aud_3rd_dac", |
| + "aud_3rd_dac_predis", |
| + "aud_3rd_dac_tml", |
| + "aud_3rd_dac_hires", |
| + "aud_i2s5_b", |
| + "aud_i2s6_b", |
| + "aud_i2s7_b", |
| + "aud_i2s8_b", |
| + "aud_i2s9_b", |
| + "imp_iic_wrap_e_i2c3", |
| + "imp_iic_wrap_s_i2c7", |
| + "imp_iic_wrap_s_i2c8", |
| + "imp_iic_wrap_s_i2c9", |
| + "imp_iic_wrap_ws_i2c1", |
| + "imp_iic_wrap_ws_i2c2", |
| + "imp_iic_wrap_ws_i2c4", |
| + "imp_iic_wrap_w_i2c5", |
| + "imp_iic_wrap_n_i2c0", |
| + "imp_iic_wrap_n_i2c6", |
| + "msdc_top_aes_0p", |
| + "msdc_top_src_0p", |
| + "msdc_top_src_1p", |
| + "msdc_top_src_2p", |
| + "msdc_top_p_msdc0", |
| + "msdc_top_p_msdc1", |
| + "msdc_top_p_msdc2", |
| + "msdc_top_p_cfg", |
| + "msdc_top_axi", |
| + "msdc_top_h_mst_0p", |
| + "msdc_top_h_mst_1p", |
| + "msdc_top_h_mst_2p", |
| + "msdc_top_mem_off_dly_26m", |
| + "msdc_top_32k", |
| + "msdc_top_ahb2axi_brg_axi", |
| + "msdc_axi_wrap", |
| + "mfg_bg3d", |
| + "mm_disp_mutex0", |
| + "mm_disp_config", |
| + "mm_disp_ovl0", |
| + "mm_disp_rdma0", |
| + "mm_disp_ovl0_2l", |
| + "mm_disp_wdma0", |
| + "mm_disp_ufbc_wdma0", |
| + "mm_disp_rsz0", |
| + "mm_disp_aal0", |
| + "mm_disp_ccorr0", |
| + "mm_disp_dither0", |
| + "mm_smi_infra", |
| + "mm_disp_gamma0", |
| + "mm_disp_postmask0", |
| + "mm_disp_dsc_wrap0", |
| + "mm_dsi0", |
| + "mm_disp_color0", |
| + "mm_smi_common", |
| + "mm_disp_fake_eng0", |
| + "mm_disp_fake_eng1", |
| + "mm_mdp_tdshp4", |
| + "mm_mdp_rsz4", |
| + "mm_mdp_aal4", |
| + "mm_mdp_hdr4", |
| + "mm_mdp_rdma4", |
| + "mm_mdp_color4", |
| + "mm_disp_y2r0", |
| + "mm_smi_gals", |
| + "mm_disp_ovl2_2l", |
| + "mm_disp_rdma4", |
| + "mm_disp_dpi0", |
| + "mm_smi_iommu", |
| + "mm_dsi_dsi0", |
| + "mm_dpi_dpi0", |
| + "mm_26mhz", |
| + "mm_32khz", |
| + "img_larb9", |
| + "img_larb10", |
| + "img_dip", |
| + "img_gals", |
| + "img2_larb11", |
| + "img2_larb12", |
| + "img2_mfb", |
| + "img2_wpe", |
| + "img2_mss", |
| + "img2_gals", |
| + "vdec_soc_larb1", |
| + "vdec_soc_lat", |
| + "vdec_soc_lat_active", |
| + "vdec_soc_vdec", |
| + "vdec_soc_vdec_active", |
| + "vdec_larb1", |
| + "vdec_lat", |
| + "vdec_lat_active", |
| + "vdec_vdec", |
| + "vdec_active", |
| + "venc_set0_larb", |
| + "venc_set1_venc", |
| + "venc_set2_jpgenc", |
| + "venc_set5_gals", |
| + "apu_conn_apu", |
| + "apu_conn_ahb", |
| + "apu_conn_axi", |
| + "apu_conn_isp", |
| + "apu_conn_cam_adl", |
| + "apu_conn_img_adl", |
| + "apu_conn_emi_26m", |
| + "apu_conn_vpu_udi", |
| + "apu_conn_edma_0", |
| + "apu_conn_edma_1", |
| + "apu_conn_edmal_0", |
| + "apu_conn_edmal_1", |
| + "apu_conn_mnoc", |
| + "apu_conn_tcm", |
| + "apu_conn_md32", |
| + "apu_conn_iommu_0", |
| + "apu_conn_iommu_1", |
| + "apu_conn_md32_32k", |
| + "apu_vcore_ahb", |
| + "apu_vcore_axi", |
| + "apu_vcore_adl", |
| + "apu_vcore_qos", |
| + "apu0_apu", |
| + "apu0_axi_m", |
| + "apu0_jtag", |
| + "apu1_apu", |
| + "apu1_axi_m", |
| + "apu1_jtag", |
| + "apu_mdla0_cg0", |
| + "apu_mdla0_cg1", |
| + "apu_mdla0_cg2", |
| + "apu_mdla0_cg3", |
| + "apu_mdla0_cg4", |
| + "apu_mdla0_cg5", |
| + "apu_mdla0_cg6", |
| + "apu_mdla0_cg7", |
| + "apu_mdla0_cg8", |
| + "apu_mdla0_cg9", |
| + "apu_mdla0_cg10", |
| + "apu_mdla0_cg11", |
| + "apu_mdla0_cg12", |
| + "apu_mdla0_apb", |
| + "apu_mdla0_axi_m", |
| + "cam_larb13", |
| + "cam_dfp_vad", |
| + "cam_larb14", |
| + "cam_cam", |
| + "cam_camtg", |
| + "cam_seninf", |
| + "cam_camsv0", |
| + "cam_camsv1", |
| + "cam_camsv2", |
| + "cam_camsv3", |
| + "cam_ccu0", |
| + "cam_ccu1", |
| + "cam_mraw0", |
| + "cam_fake_eng", |
| + "cam_ccu_gals", |
| + "cam2mm_gals", |
| + "cam_rawa_larbx", |
| + "cam_rawa_cam", |
| + "cam_rawa_camtg", |
| + "cam_rawb_larbx", |
| + "cam_rawb_cam", |
| + "cam_rawb_camtg", |
| + "cam_rawc_larbx", |
| + "cam_rawc_cam", |
| + "cam_rawc_camtg", |
| + "ipe_larb19", |
| + "ipe_larb20", |
| + "ipe_smi_subcom", |
| + "ipe_fd", |
| + "ipe_fe", |
| + "ipe_rsc", |
| + "ipe_dpe", |
| + "ipe_gals", |
| + "mdp_mdp_rdma0", |
| + "mdp_mdp_tdshp0", |
| + "mdp_img_dl_async0", |
| + "mdp_img_dl_async1", |
| + "mdp_mdp_rdma1", |
| + "mdp_mdp_tdshp1", |
| + "mdp_smi0", |
| + "mdp_apb_bus", |
| + "mdp_mdp_wrot0", |
| + "mdp_mdp_rsz0", |
| + "mdp_mdp_hdr0", |
| + "mdp_mdp_mutex0", |
| + "mdp_mdp_wrot1", |
| + "mdp_mdp_rsz1", |
| + "mdp_mdp_hdr1", |
| + "mdp_mdp_fake_eng0", |
| + "mdp_mdp_aal0", |
| + "mdp_mdp_aal1", |
| + "mdp_mdp_color0", |
| + "mdp_mdp_color1", |
| + "mdp_img_dl_relay0_async0", |
| + "mdp_img_dl_relay1_async1", |
| + /* end */ |
| + NULL |
| + }; |
| + |
| + return clks; |
| +} |
| + |
| +/* |
| + * clkdbg pwr_status |
| + */ |
| + |
| +static const char * const *get_pwr_names(void) |
| +{ |
| + static const char * const pwr_names[] = { |
| + [0] = "MD", |
| + [1] = "CONN", |
| + [2] = "MFG0", |
| + [3] = "MFG1", |
| + [4] = "MFG2", |
| + [5] = "MFG3", |
| + [6] = "MFG4", |
| + [7] = "MFG5", |
| + [8] = "MFG6", |
| + [9] = "INFRA", |
| + [10] = "SUB_INFRA", |
| + [11] = "DDRPHY", |
| + [12] = "ISP", |
| + [13] = "ISP2", |
| + [14] = "IPE", |
| + [15] = "VDEC", |
| + [16] = "VDEC2", |
| + [17] = "VEN", |
| + [18] = "VEN_CORE1", |
| + [19] = "MDP", |
| + [20] = "DISP", |
| + [21] = "AUDIO", |
| + [22] = "ADSP", |
| + [23] = "CAM", |
| + [24] = "CAM_RAWA", |
| + [25] = "CAM_RAWB", |
| + [26] = "CAM_RAWC", |
| + [27] = "DP_TX", |
| + [28] = "DDRPHY2", |
| + [29] = "MCUPM", |
| + [30] = "MSDC", |
| + [31] = "PERI", |
| + }; |
| + |
| + return pwr_names; |
| +} |
| + |
| +static u32 get_spm_pwr_status(void) |
| +{ |
| + static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd; |
| + |
| + if (scpsys_base == NULL || pwr_sta == NULL || pwr_sta_2nd == NULL) { |
| + scpsys_base = ioremap(0x10006000, PAGE_SIZE); |
| + pwr_sta = scpsys_base + 0x16c; |
| + pwr_sta_2nd = scpsys_base + 0x170; |
| + } |
| + |
| + return clk_readl(pwr_sta) & clk_readl(pwr_sta_2nd); |
| +} |
| + |
| +static int clkdbg_pwr_status_vpu(struct seq_file *s, void *v) |
| +{ |
| + static void __iomem *scpsys_base; |
| + u32 other_pwr_sta; |
| + const char *st; |
| + |
| + scpsys_base = ioremap(0x10006000, PAGE_SIZE); |
| + other_pwr_sta = clk_readl(scpsys_base + 0x178); |
| + |
| + seq_printf(s, "OTHER_PWR_STATUS: 0x%08x\n", other_pwr_sta); |
| + |
| + st = (other_pwr_sta & BIT(5)) != 0U ? "ON" : "off"; |
| + |
| + seq_printf(s, "[%2d]: %3s: %s\n", 5, st, "VPU"); |
| + |
| + return 0; |
| +} |
| + |
| +/* |
| + * clkdbg dump_clks |
| + */ |
| + |
| +static void setup_provider_clk(struct provider_clk *pvdck) |
| +{ |
| + static const struct { |
| + const char *pvdname; |
| + u32 pwr_mask; |
| + } pvd_pwr_mask[] = { |
| + {"scp_adsp", BIT(22)}, |
| + {"audsys", BIT(21)}, |
| + {"msdc_top", BIT(30)}, |
| + {"msdc", BIT(30)}, |
| + {"mfgcfg", BIT(2)}, |
| + {"mmsys", BIT(20)}, |
| + {"imgsys", BIT(12)}, |
| + {"imgsys2", BIT(13)}, |
| + {"vdecsys_soc", BIT(15)}, |
| + {"vdecsys", BIT(16)}, |
| + {"vencsys", BIT(17)}, |
| +#if 0 // other_pwr_status |
| + {"apu_conn", BIT(5)}, |
| + {"apu_vcore", BIT(5)}, |
| + {"apu0", BIT(5)}, |
| + {"apu1", BIT(5)}, |
| + {"apu_mdla0", BIT(5)}, |
| +#endif |
| + {"camsys", BIT(23)}, |
| + {"camsys_rawa", BIT(24)}, |
| + {"camsys_rawb", BIT(25)}, |
| + {"camsys_rawc", BIT(26)}, |
| + {"ipesys", BIT(14)}, |
| + {"mdpsys", BIT(19)}, |
| + }; |
| + |
| + size_t i; |
| + const char *pvdname = pvdck->provider_name; |
| + |
| + if (pvdname == NULL) |
| + return; |
| + |
| + for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) { |
| + if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) { |
| + pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask; |
| + return; |
| + } |
| + } |
| +} |
| + |
| +/* |
| + * init functions |
| + */ |
| + |
| +static struct clkdbg_ops clkdbg_mt8192_ops = { |
| + .get_all_fmeter_clks = get_all_fmeter_clks, |
| + .fmeter_freq = fmeter_freq_op, |
| + .get_all_regnames = get_all_regnames, |
| + .get_all_clk_names = get_all_clk_names, |
| + .get_pwr_names = get_pwr_names, |
| + .setup_provider_clk = setup_provider_clk, |
| + .get_spm_pwr_status = get_spm_pwr_status, |
| +}; |
| + |
| +static void __init init_custom_cmds(void) |
| +{ |
| + static const struct cmd_fn cmds[] = { |
| + CMDFN("pwr_status_vpu", clkdbg_pwr_status_vpu), |
| + {} |
| + }; |
| + |
| + set_custom_cmds(cmds); |
| +} |
| + |
| +static int __init clkdbg_mt8192_init(void) |
| +{ |
| + if (of_machine_is_compatible("mediatek,mt8192") == 0) |
| + return -ENODEV; |
| + |
| + init_regbase(); |
| + |
| + init_custom_cmds(); |
| + set_clkdbg_ops(&clkdbg_mt8192_ops); |
| + |
| +#if DUMP_INIT_STATE |
| + print_regs(); |
| + print_fmeter_all(); |
| +#endif /* DUMP_INIT_STATE */ |
| + |
| + return 0; |
| +} |
| +device_initcall(clkdbg_mt8192_init); |
| diff --git a/drivers/clk/mediatek/clkdbg.c b/drivers/clk/mediatek/clkdbg.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..5d36d23b12d2071be20c368cb6b6ed9cd1492867 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clkdbg.c |
| @@ -0,0 +1,2271 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| +// Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + |
| +#define pr_fmt(fmt) "[clkdbg] " fmt |
| + |
| +#include <linux/of.h> |
| +#include <linux/of_address.h> |
| +#include <linux/of_platform.h> |
| +#include <linux/slab.h> |
| +#include <linux/delay.h> |
| + |
| +#include <linux/proc_fs.h> |
| +#include <linux/fs.h> |
| +#include <linux/seq_file.h> |
| +#include <linux/uaccess.h> |
| + |
| +#include <linux/clk.h> |
| +#include <linux/clk-provider.h> |
| +#include <linux/pm_domain.h> |
| +#include <linux/pm_runtime.h> |
| +#include <linux/module.h> |
| +#include <linux/version.h> |
| + |
| +#include "clkdbg.h" |
| + |
| +#if defined(CONFIG_PM_DEBUG) |
| +#define CLKDBG_PM_DOMAIN 1 |
| +#else |
| +#define CLKDBG_PM_DOMAIN 0 |
| +#endif |
| +#define CLKDBG_PM_DOMAIN_API_4_9 1 |
| +#define CLKDBG_CCF_API_4_4 1 |
| +#define CLKDBG_HACK_CLK 0 |
| +#define CLKDBG_HACK_CLK_CORE 1 |
| +#define CLKDBG_DROP_GENPD_AS_IN_PARAM 1 |
| + |
| +#define TOTAL_CLK_NUM 550 |
| +#define TOTAL_PD_NUM 32 |
| + |
| +#if !CLKDBG_CCF_API_4_4 |
| + |
| +/* backward compatible */ |
| + |
| +static const char *clk_hw_get_name(const struct clk_hw *hw) |
| +{ |
| + return __clk_get_name(hw->clk); |
| +} |
| + |
| +static bool clk_hw_is_prepared(const struct clk_hw *hw) |
| +{ |
| + return __clk_is_prepared(hw->clk); |
| +} |
| + |
| +static bool clk_hw_is_enabled(const struct clk_hw *hw) |
| +{ |
| + return __clk_is_enabled(hw->clk); |
| +} |
| + |
| +static unsigned long clk_hw_get_rate(const struct clk_hw *hw) |
| +{ |
| + return __clk_get_rate(hw->clk); |
| +} |
| + |
| +static unsigned int clk_hw_get_num_parents(const struct clk_hw *hw) |
| +{ |
| + return __clk_get_num_parents(hw->clk); |
| +} |
| + |
| +static struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, |
| + unsigned int index) |
| +{ |
| + return __clk_get_hw(clk_get_parent_by_index(hw->clk, index)); |
| +} |
| + |
| +#endif /* !CLKDBG_CCF_API_4_4 */ |
| + |
| +#if CLKDBG_HACK_CLK |
| + |
| +#include <linux/clk-private.h> |
| + |
| +static bool clk_hw_is_on(struct clk_hw *hw) |
| +{ |
| + const struct clk_ops *ops = hw->clk->ops; |
| + |
| + if (ops->is_enabled) |
| + return clk_hw_is_enabled(hw); |
| + else if (ops->is_prepared) |
| + return clk_hw_is_prepared(hw); |
| + return clk_hw_is_enabled(hw) || clk_hw_is_prepared(hw); |
| +} |
| + |
| +#elif CLKDBG_HACK_CLK_CORE |
| + |
| +struct clk_core { |
| + const char *name; |
| + const struct clk_ops *ops; |
| + struct clk_hw *hw; |
| +}; |
| + |
| +static bool clk_hw_is_on(struct clk_hw *hw) |
| +{ |
| + const struct clk_ops *ops = hw->core->ops; |
| + |
| + if (ops->is_enabled) |
| + return clk_hw_is_enabled(hw); |
| + else if (ops->is_prepared) |
| + return clk_hw_is_prepared(hw); |
| + return clk_hw_is_enabled(hw) || clk_hw_is_prepared(hw); |
| +} |
| + |
| +#else |
| + |
| +static bool clk_hw_is_on(struct clk_hw *hw) |
| +{ |
| + return __clk_get_enable_count(hw->clk) || clk_hw_is_prepared(hw); |
| +} |
| + |
| +#endif /* !CLKDBG_HACK_CLK && !CLKDBG_HACK_CLK_CORE */ |
| + |
| +static const struct clkdbg_ops *clkdbg_ops; |
| + |
| +void set_clkdbg_ops(const struct clkdbg_ops *ops) |
| +{ |
| + clkdbg_ops = ops; |
| +} |
| + |
| +static const struct fmeter_clk *get_all_fmeter_clks(void) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->get_all_fmeter_clks == NULL) |
| + return NULL; |
| + |
| + return clkdbg_ops->get_all_fmeter_clks(); |
| +} |
| + |
| +static void *prepare_fmeter(void) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->prepare_fmeter == NULL) |
| + return NULL; |
| + |
| + return clkdbg_ops->prepare_fmeter(); |
| +} |
| + |
| +static void unprepare_fmeter(void *data) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->unprepare_fmeter == NULL) |
| + return; |
| + |
| + clkdbg_ops->unprepare_fmeter(data); |
| +} |
| + |
| +static u32 fmeter_freq(const struct fmeter_clk *fclk) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->fmeter_freq == NULL) |
| + return 0; |
| + |
| + return clkdbg_ops->fmeter_freq(fclk); |
| +} |
| + |
| +static const struct regname *get_all_regnames(void) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->get_all_regnames == NULL) |
| + return NULL; |
| + |
| + return clkdbg_ops->get_all_regnames(); |
| +} |
| + |
| +static const char * const *get_all_clk_names(void) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->get_all_clk_names == NULL) |
| + return NULL; |
| + |
| + return clkdbg_ops->get_all_clk_names(); |
| +} |
| + |
| +static const char * const *get_pwr_names(void) |
| +{ |
| + static const char * const default_pwr_names[] = { |
| + [0] = "(MD)", |
| + [1] = "(CONN)", |
| + [2] = "(DDRPHY)", |
| + [3] = "(DISP)", |
| + [4] = "(MFG)", |
| + [5] = "(ISP)", |
| + [6] = "(INFRA)", |
| + [7] = "(VDEC)", |
| + [8] = "(CPU, CA7_CPUTOP)", |
| + [9] = "(FC3, CA7_CPU0, CPUTOP)", |
| + [10] = "(FC2, CA7_CPU1, CPU3)", |
| + [11] = "(FC1, CA7_CPU2, CPU2)", |
| + [12] = "(FC0, CA7_CPU3, CPU1)", |
| + [13] = "(MCUSYS, CA7_DBG, CPU0)", |
| + [14] = "(MCUSYS, VEN, BDP)", |
| + [15] = "(CA15_CPUTOP, ETH, MCUSYS)", |
| + [16] = "(CA15_CPU0, HIF)", |
| + [17] = "(CA15_CPU1, CA15-CX0, INFRA_MISC)", |
| + [18] = "(CA15_CPU2, CA15-CX1)", |
| + [19] = "(CA15_CPU3, CA15-CPU0)", |
| + [20] = "(VEN2, MJC, CA15-CPU1)", |
| + [21] = "(VEN, CA15-CPUTOP)", |
| + [22] = "(MFG_2D)", |
| + [23] = "(MFG_ASYNC, DBG)", |
| + [24] = "(AUDIO, MFG_2D)", |
| + [25] = "(USB, VCORE_PDN, MFG_ASYNC)", |
| + [26] = "(ARMPLL_DIV, CPUTOP_SRM_SLPB)", |
| + [27] = "(MD2, CPUTOP_SRM_PDN)", |
| + [28] = "(CPU3_SRM_PDN)", |
| + [29] = "(CPU2_SRM_PDN)", |
| + [30] = "(CPU1_SRM_PDN)", |
| + [31] = "(CPU0_SRM_PDN)", |
| + }; |
| + |
| + if (clkdbg_ops == NULL || clkdbg_ops->get_pwr_names == NULL) |
| + return default_pwr_names; |
| + |
| + return clkdbg_ops->get_pwr_names(); |
| +} |
| + |
| +static void setup_provider_clk(struct provider_clk *pvdck) |
| +{ |
| + if (clkdbg_ops == NULL || clkdbg_ops->setup_provider_clk == NULL) |
| + return; |
| + |
| + clkdbg_ops->setup_provider_clk(pvdck); |
| +} |
| + |
| +static bool is_valid_reg(void __iomem *addr) |
| +{ |
| +#ifdef CONFIG_64BIT |
| + return ((u64)addr & 0xf0000000) != 0UL || |
| + (((u64)addr >> 32U) & 0xf0000000) != 0UL; |
| +#else |
| + return ((u32)addr & 0xf0000000) != 0U; |
| +#endif |
| +} |
| + |
| +enum clkdbg_opt { |
| + CLKDBG_EN_SUSPEND_SAVE_1, |
| + CLKDBG_EN_SUSPEND_SAVE_2, |
| + CLKDBG_EN_SUSPEND_SAVE_3, |
| + CLKDBG_EN_LOG_SAVE_POINTS, |
| +}; |
| + |
| +static u32 clkdbg_flags; |
| + |
| +static void set_clkdbg_flag(enum clkdbg_opt opt) |
| +{ |
| + clkdbg_flags |= BIT(opt); |
| +} |
| + |
| +static void clr_clkdbg_flag(enum clkdbg_opt opt) |
| +{ |
| + clkdbg_flags &= ~BIT(opt); |
| +} |
| + |
| +static bool has_clkdbg_flag(enum clkdbg_opt opt) |
| +{ |
| + return (clkdbg_flags & BIT(opt)) != 0U; |
| +} |
| + |
| +typedef void (*fn_fclk_freq_proc)(const struct fmeter_clk *fclk, |
| + u32 freq, void *data); |
| + |
| +static void proc_all_fclk_freq(fn_fclk_freq_proc proc, void *data) |
| +{ |
| + void *fmeter_data; |
| + const struct fmeter_clk *fclk; |
| + |
| + fclk = get_all_fmeter_clks(); |
| + |
| + if (fclk == NULL || proc == NULL) |
| + return; |
| + |
| + fmeter_data = prepare_fmeter(); |
| + |
| + for (; fclk->type != FT_NULL; fclk++) { |
| + u32 freq; |
| + |
| + freq = fmeter_freq(fclk); |
| + proc(fclk, freq, data); |
| + } |
| + |
| + unprepare_fmeter(fmeter_data); |
| +} |
| + |
| +static void print_fclk_freq(const struct fmeter_clk *fclk, u32 freq, void *data) |
| +{ |
| + pr_info("%2d: %-29s: %u\n", fclk->id, fclk->name, freq); |
| +} |
| + |
| +void print_fmeter_all(void) |
| +{ |
| + proc_all_fclk_freq(print_fclk_freq, NULL); |
| +} |
| + |
| +static void seq_print_fclk_freq(const struct fmeter_clk *fclk, |
| + u32 freq, void *data) |
| +{ |
| + struct seq_file *s = data; |
| + |
| + seq_printf(s, "%2d: %-29s: %u\n", fclk->id, fclk->name, freq); |
| +} |
| + |
| +static int seq_print_fmeter_all(struct seq_file *s, void *v) |
| +{ |
| + proc_all_fclk_freq(seq_print_fclk_freq, s); |
| + |
| + return 0; |
| +} |
| + |
| +typedef void (*fn_regname_proc)(const struct regname *rn, void *data); |
| + |
| +static void proc_all_regname(fn_regname_proc proc, void *data) |
| +{ |
| + const struct regname *rn = get_all_regnames(); |
| + |
| + if (rn == NULL) |
| + return; |
| + |
| + for (; rn->base != NULL; rn++) |
| + proc(rn, data); |
| +} |
| + |
| +static void print_reg(const struct regname *rn, void *data) |
| +{ |
| + if (!is_valid_reg(ADDR(rn))) |
| + return; |
| + |
| + pr_info("%-21s: [0x%08x][0x%p] = 0x%08x\n", |
| + rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn))); |
| +} |
| + |
| +void print_regs(void) |
| +{ |
| + proc_all_regname(print_reg, NULL); |
| +} |
| + |
| +static void seq_print_reg(const struct regname *rn, void *data) |
| +{ |
| + struct seq_file *s = data; |
| + |
| + if (!is_valid_reg(ADDR(rn))) |
| + return; |
| + |
| + seq_printf(s, "%-21s: [0x%08x][0x%p] = 0x%08x\n", |
| + rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn))); |
| +} |
| + |
| +static int seq_print_regs(struct seq_file *s, void *v) |
| +{ |
| + proc_all_regname(seq_print_reg, s); |
| + |
| + return 0; |
| +} |
| + |
| +static void print_reg2(const struct regname *rn, void *data) |
| +{ |
| + if (!is_valid_reg(ADDR(rn))) |
| + return; |
| + |
| + pr_info("%-21s: [0x%08x][0x%p] = 0x%08x\n", |
| + rn->name, PHYSADDR(rn), ADDR(rn), clk_readl(ADDR(rn))); |
| + |
| + msleep(20); |
| +} |
| + |
| +static int clkdbg_dump_regs2(struct seq_file *s, void *v) |
| +{ |
| + proc_all_regname(print_reg2, s); |
| + |
| + return 0; |
| +} |
| + |
| +static u32 read_spm_pwr_status(void) |
| +{ |
| + static void __iomem *scpsys_base, *pwr_sta, *pwr_sta_2nd; |
| + |
| + if (clkdbg_ops == NULL || clkdbg_ops->get_spm_pwr_status == NULL) { |
| + if (scpsys_base == NULL || |
| + pwr_sta == NULL || pwr_sta_2nd == NULL) { |
| + scpsys_base = ioremap(0x10006000, PAGE_SIZE); |
| + pwr_sta = scpsys_base + 0x60c; |
| + pwr_sta_2nd = scpsys_base + 0x610; |
| + } |
| + |
| + return clk_readl(pwr_sta) & clk_readl(pwr_sta_2nd); |
| + } else |
| + return clkdbg_ops->get_spm_pwr_status(); |
| +} |
| + |
| +static bool clk_hw_pwr_is_on(struct clk_hw *c_hw, |
| + u32 spm_pwr_status, u32 pwr_mask) |
| +{ |
| + if ((spm_pwr_status & pwr_mask) != pwr_mask) |
| + return false; |
| + |
| + return clk_hw_is_on(c_hw); |
| +} |
| + |
| +static bool pvdck_pwr_is_on(struct provider_clk *pvdck, u32 spm_pwr_status) |
| +{ |
| + struct clk *c = pvdck->ck; |
| + struct clk_hw *c_hw = __clk_get_hw(c); |
| + |
| + return clk_hw_pwr_is_on(c_hw, spm_pwr_status, pvdck->pwr_mask); |
| +} |
| + |
| +static bool pvdck_is_on(struct provider_clk *pvdck) |
| +{ |
| + u32 spm_pwr_status = 0; |
| + |
| + if (pvdck->pwr_mask != 0U) |
| + spm_pwr_status = read_spm_pwr_status(); |
| + |
| + return pvdck_pwr_is_on(pvdck, spm_pwr_status); |
| +} |
| + |
| +static const char *ccf_state(struct clk_hw *hw) |
| +{ |
| + if (__clk_get_enable_count(hw->clk)) |
| + return "enabled"; |
| + |
| + if (clk_hw_is_prepared(hw)) |
| + return "prepared"; |
| + |
| + return "disabled"; |
| +} |
| + |
| +static void dump_clk_state(const char *clkname, struct seq_file *s) |
| +{ |
| + struct clk *c = __clk_lookup(clkname); |
| + struct clk *p = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c); |
| + struct clk_hw *c_hw = __clk_get_hw(c); |
| + struct clk_hw *p_hw = __clk_get_hw(p); |
| + |
| + if (IS_ERR_OR_NULL(c)) { |
| + seq_printf(s, "[%17s: NULL]\n", clkname); |
| + return; |
| + } |
| + |
| + seq_printf(s, "[%-17s: %8s, %3d, %3d, %10ld, %17s]\n", |
| + clk_hw_get_name(c_hw), |
| + ccf_state(c_hw), |
| + clk_hw_is_prepared(c_hw), |
| + __clk_get_enable_count(c), |
| + clk_hw_get_rate(c_hw), |
| + p != NULL ? clk_hw_get_name(p_hw) : "- "); |
| +} |
| + |
| +static int clkdbg_dump_state_all(struct seq_file *s, void *v) |
| +{ |
| + const char * const *ckn = get_all_clk_names(); |
| + |
| + if (ckn == NULL) |
| + return 0; |
| + |
| + for (; *ckn != NULL; ckn++) |
| + dump_clk_state(*ckn, s); |
| + |
| + return 0; |
| +} |
| + |
| +static const char *get_provider_name(struct device_node *node, u32 *cells) |
| +{ |
| + const char *name; |
| + const char *p; |
| + u32 cc; |
| + |
| + if (of_property_read_u32(node, "#clock-cells", &cc) != 0) |
| + cc = 0; |
| + |
| + if (cells != NULL) |
| + *cells = cc; |
| + |
| + if (cc == 0U) { |
| + if (of_property_read_string(node, |
| + "clock-output-names", &name) < 0) |
| + name = node->name; |
| + |
| + return name; |
| + } |
| + |
| + if (of_property_read_string(node, "compatible", &name) < 0) |
| + name = node->name; |
| + |
| + p = strchr(name, (int)'-'); |
| + |
| + if (p != NULL) |
| + return p + 1; |
| + else |
| + return name; |
| +} |
| + |
| +struct provider_clk *get_all_provider_clks(void) |
| +{ |
| + static struct provider_clk provider_clks[TOTAL_CLK_NUM]; |
| + struct device_node *node = NULL; |
| + int n = 0; |
| + |
| + if (provider_clks[0].ck != NULL) |
| + return provider_clks; |
| + |
| + do { |
| + const char *node_name; |
| + u32 cells; |
| + |
| + node = of_find_node_with_property(node, "#clock-cells"); |
| + |
| + if (node == NULL) |
| + break; |
| + |
| + node_name = get_provider_name(node, &cells); |
| + |
| + if (cells == 0U) { |
| + struct clk *ck = __clk_lookup(node_name); |
| + |
| + if (IS_ERR_OR_NULL(ck)) |
| + continue; |
| + |
| + provider_clks[n].ck = ck; |
| + setup_provider_clk(&provider_clks[n]); |
| + ++n; |
| + } else { |
| + unsigned int i; |
| + |
| + for (i = 0; i < 256; i++) { |
| + struct of_phandle_args pa; |
| + struct clk *ck; |
| + |
| + pa.np = node; |
| + pa.args[0] = i; |
| + pa.args_count = 1; |
| + ck = of_clk_get_from_provider(&pa); |
| + |
| + if (PTR_ERR(ck) == -EINVAL) |
| + break; |
| + else if (IS_ERR_OR_NULL(ck)) |
| + continue; |
| + |
| + provider_clks[n].ck = ck; |
| + provider_clks[n].idx = i; |
| + provider_clks[n].provider_name = node_name; |
| + setup_provider_clk(&provider_clks[n]); |
| + ++n; |
| + } |
| + } |
| + } while (node != NULL); |
| + |
| + return provider_clks; |
| +} |
| + |
| +static void dump_provider_clk(struct provider_clk *pvdck, struct seq_file *s) |
| +{ |
| + struct clk *c = pvdck->ck; |
| + struct clk *p = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c); |
| + struct clk_hw *c_hw = __clk_get_hw(c); |
| + struct clk_hw *p_hw = __clk_get_hw(p); |
| + |
| + seq_printf(s, "[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n", |
| + pvdck->provider_name != NULL ? pvdck->provider_name : "/ ", |
| + clk_hw_get_name(c_hw), |
| + pvdck_is_on(pvdck) ? "ON" : "off", |
| + clk_hw_is_prepared(c_hw), |
| + __clk_get_enable_count(c), |
| + clk_hw_get_rate(c_hw), |
| + p != NULL ? clk_hw_get_name(p_hw) : "- "); |
| +} |
| + |
| +static int clkdbg_dump_provider_clks(struct seq_file *s, void *v) |
| +{ |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) |
| + dump_provider_clk(pvdck, s); |
| + |
| + return 0; |
| +} |
| + |
| +static void dump_provider_mux(struct provider_clk *pvdck, struct seq_file *s) |
| +{ |
| + unsigned int i; |
| + struct clk *c = pvdck->ck; |
| + struct clk_hw *c_hw = __clk_get_hw(c); |
| + unsigned int np = clk_hw_get_num_parents(c_hw); |
| + |
| + if (np <= 1U) |
| + return; |
| + |
| + dump_provider_clk(pvdck, s); |
| + |
| + for (i = 0; i < np; i++) { |
| + struct clk_hw *p_hw = clk_hw_get_parent_by_index(c_hw, i); |
| + |
| + if (IS_ERR_OR_NULL(p_hw)) |
| + continue; |
| + |
| + seq_printf(s, "\t\t\t(%2d: %-17s: %8s, %10ld)\n", |
| + i, |
| + clk_hw_get_name(p_hw), |
| + ccf_state(p_hw), |
| + clk_hw_get_rate(p_hw)); |
| + } |
| +} |
| + |
| +static int clkdbg_dump_muxes(struct seq_file *s, void *v) |
| +{ |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) |
| + dump_provider_mux(pvdck, s); |
| + |
| + return 0; |
| +} |
| + |
| +static void show_pwr_status(u32 spm_pwr_status) |
| +{ |
| + unsigned int i; |
| + const char * const *pwr_name = get_pwr_names(); |
| + |
| + pr_info("SPM_PWR_STATUS: 0x%08x\n\n", spm_pwr_status); |
| + |
| + for (i = 0; i < 32; i++) { |
| + const char *st = (spm_pwr_status & BIT(i)) != 0U ? "ON" : "off"; |
| + |
| + pr_info("[%2d]: %3s: %s\n", i, st, pwr_name[i]); |
| + mdelay(20); |
| + } |
| +} |
| + |
| +static int dump_pwr_status(u32 spm_pwr_status, struct seq_file *s) |
| +{ |
| + unsigned int i; |
| + const char * const *pwr_name = get_pwr_names(); |
| + |
| + seq_printf(s, "SPM_PWR_STATUS: 0x%08x\n\n", spm_pwr_status); |
| + |
| + for (i = 0; i < 32; i++) { |
| + const char *st = (spm_pwr_status & BIT(i)) != 0U ? "ON" : "off"; |
| + |
| + seq_printf(s, "[%2d]: %3s: %s\n", i, st, pwr_name[i]); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pwr_status(struct seq_file *s, void *v) |
| +{ |
| + return dump_pwr_status(read_spm_pwr_status(), s); |
| +} |
| + |
| +static char last_cmd[128] = "null"; |
| + |
| +const char *get_last_cmd(void) |
| +{ |
| + return last_cmd; |
| +} |
| + |
| +static int clkop_int_ckname(int (*clkop)(struct clk *clk), |
| + const char *clkop_name, const char *clk_name, |
| + struct clk *ck, struct seq_file *s) |
| +{ |
| + struct clk *clk; |
| + |
| + if (!IS_ERR_OR_NULL(ck)) { |
| + clk = ck; |
| + } else { |
| + clk = __clk_lookup(clk_name); |
| + if (IS_ERR_OR_NULL(clk)) { |
| + seq_printf(s, "clk_lookup(%s): 0x%p\n", clk_name, clk); |
| + return PTR_ERR(clk); |
| + } |
| + } |
| + |
| + return clkop(clk); |
| +} |
| + |
| +static int clkdbg_clkop_int_ckname(int (*clkop)(struct clk *clk), |
| + const char *clkop_name, struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *clk_name; |
| + int r = 0; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + clk_name = strsep(&c, " "); |
| + |
| + if (clk_name == NULL) |
| + return 0; |
| + |
| + if (strcmp(clk_name, "all") == 0) { |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) { |
| + r |= clkop_int_ckname(clkop, clkop_name, NULL, |
| + pvdck->ck, s); |
| + } |
| + |
| + seq_printf(s, "%s(%s): %d\n", clkop_name, clk_name, r); |
| + |
| + return r; |
| + } |
| + |
| + r = clkop_int_ckname(clkop, clkop_name, clk_name, NULL, s); |
| + seq_printf(s, "%s(%s): %d\n", clkop_name, clk_name, r); |
| + |
| + return r; |
| +} |
| + |
| +static void clkop_void_ckname(void (*clkop)(struct clk *clk), |
| + const char *clkop_name, const char *clk_name, |
| + struct clk *ck, struct seq_file *s) |
| +{ |
| + struct clk *clk; |
| + |
| + if (!IS_ERR_OR_NULL(ck)) { |
| + clk = ck; |
| + } else { |
| + clk = __clk_lookup(clk_name); |
| + if (IS_ERR_OR_NULL(clk)) { |
| + seq_printf(s, "clk_lookup(%s): 0x%p\n", clk_name, clk); |
| + return; |
| + } |
| + } |
| + |
| + clkop(clk); |
| +} |
| + |
| +static int clkdbg_clkop_void_ckname(void (*clkop)(struct clk *clk), |
| + const char *clkop_name, struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *clk_name; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + clk_name = strsep(&c, " "); |
| + |
| + if (clk_name == NULL) |
| + return 0; |
| + |
| + if (strcmp(clk_name, "all") == 0) { |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) { |
| + clkop_void_ckname(clkop, clkop_name, NULL, |
| + pvdck->ck, s); |
| + } |
| + |
| + seq_printf(s, "%s(%s)\n", clkop_name, clk_name); |
| + |
| + return 0; |
| + } |
| + |
| + clkop_void_ckname(clkop, clkop_name, clk_name, NULL, s); |
| + seq_printf(s, "%s(%s)\n", clkop_name, clk_name); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_prepare(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_int_ckname(clk_prepare, |
| + "clk_prepare", s, v); |
| +} |
| + |
| +static int clkdbg_unprepare(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_void_ckname(clk_unprepare, |
| + "clk_unprepare", s, v); |
| +} |
| + |
| +static int clkdbg_enable(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_int_ckname(clk_enable, |
| + "clk_enable", s, v); |
| +} |
| + |
| +static int clkdbg_disable(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_void_ckname(clk_disable, |
| + "clk_disable", s, v); |
| +} |
| + |
| +static int clkdbg_prepare_enable(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_int_ckname(clk_prepare_enable, |
| + "clk_prepare_enable", s, v); |
| +} |
| + |
| +static int clkdbg_disable_unprepare(struct seq_file *s, void *v) |
| +{ |
| + return clkdbg_clkop_void_ckname(clk_disable_unprepare, |
| + "clk_disable_unprepare", s, v); |
| +} |
| + |
| +void prepare_enable_provider(const char *pvd) |
| +{ |
| + bool allpvd = (pvd == NULL || strcmp(pvd, "all") == 0); |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) { |
| + if (allpvd || (pvdck->provider_name != NULL && |
| + strcmp(pvd, pvdck->provider_name) == 0)) { |
| + int r = clk_prepare_enable(pvdck->ck); |
| + |
| + if (r != 0) |
| + pr_info("clk_prepare_enable(): %d\n", r); |
| + } |
| + } |
| +} |
| + |
| +void disable_unprepare_provider(const char *pvd) |
| +{ |
| + bool allpvd = (pvd == NULL || strcmp(pvd, "all") == 0); |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + |
| + for (; pvdck->ck != NULL; pvdck++) { |
| + if (allpvd || (pvdck->provider_name != NULL && |
| + strcmp(pvd, pvdck->provider_name) == 0)) |
| + clk_disable_unprepare(pvdck->ck); |
| + } |
| +} |
| + |
| +static void clkpvdop(void (*pvdop)(const char *), const char *clkpvdop_name, |
| + struct seq_file *s) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *pvd_name; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + pvd_name = strsep(&c, " "); |
| + |
| + if (pvd_name == NULL) |
| + return; |
| + |
| + pvdop(pvd_name); |
| + seq_printf(s, "%s(%s)\n", clkpvdop_name, pvd_name); |
| +} |
| + |
| +static int clkdbg_prepare_enable_provider(struct seq_file *s, void *v) |
| +{ |
| + clkpvdop(prepare_enable_provider, "prepare_enable_provider", s); |
| + return 0; |
| +} |
| + |
| +static int clkdbg_disable_unprepare_provider(struct seq_file *s, void *v) |
| +{ |
| + clkpvdop(disable_unprepare_provider, "disable_unprepare_provider", s); |
| + return 0; |
| +} |
| + |
| +static int clkdbg_set_parent(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *clk_name; |
| + char *parent_name; |
| + struct clk *clk; |
| + struct clk *parent; |
| + int r; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + clk_name = strsep(&c, " "); |
| + parent_name = strsep(&c, " "); |
| + |
| + if (clk_name == NULL || parent_name == NULL) |
| + return 0; |
| + |
| + seq_printf(s, "clk_set_parent(%s, %s): ", clk_name, parent_name); |
| + |
| + clk = __clk_lookup(clk_name); |
| + if (IS_ERR_OR_NULL(clk)) { |
| + seq_printf(s, "__clk_lookup(): 0x%p\n", clk); |
| + return PTR_ERR(clk); |
| + } |
| + |
| + parent = __clk_lookup(parent_name); |
| + if (IS_ERR_OR_NULL(parent)) { |
| + seq_printf(s, "__clk_lookup(): 0x%p\n", parent); |
| + return PTR_ERR(parent); |
| + } |
| + |
| + r = clk_prepare_enable(clk); |
| + if (r != 0) { |
| + seq_printf(s, "clk_prepare_enable(): %d\n", r); |
| + return r; |
| + } |
| + |
| + r = clk_set_parent(clk, parent); |
| + seq_printf(s, "%d\n", r); |
| + |
| + clk_disable_unprepare(clk); |
| + |
| + return r; |
| +} |
| + |
| +static int clkdbg_set_rate(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *clk_name; |
| + char *rate_str; |
| + struct clk *clk; |
| + unsigned long rate; |
| + int r; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + clk_name = strsep(&c, " "); |
| + rate_str = strsep(&c, " "); |
| + |
| + if (clk_name == NULL || rate_str == NULL) |
| + return 0; |
| + |
| + r = kstrtoul(rate_str, 0, &rate); |
| + |
| + seq_printf(s, "clk_set_rate(%s, %lu): %d: ", clk_name, rate, r); |
| + |
| + clk = __clk_lookup(clk_name); |
| + if (IS_ERR_OR_NULL(clk)) { |
| + seq_printf(s, "__clk_lookup(): 0x%p\n", clk); |
| + return PTR_ERR(clk); |
| + } |
| + |
| + r = clk_set_rate(clk, rate); |
| + seq_printf(s, "%d\n", r); |
| + |
| + return r; |
| +} |
| + |
| +static void *reg_from_str(const char *str) |
| +{ |
| + static phys_addr_t phys; |
| + static void __iomem *virt; |
| + |
| + if (sizeof(void *) == sizeof(unsigned long)) { |
| + unsigned long v; |
| + |
| + if (kstrtoul(str, 0, &v) == 0U) { |
| + if ((0xf0000000 & v) < 0x20000000) { |
| + if (virt != NULL && v > phys |
| + && v < phys + PAGE_SIZE) |
| + return virt + v - phys; |
| + |
| + if (virt != NULL) |
| + iounmap(virt); |
| + |
| + phys = v & ~(PAGE_SIZE - 1U); |
| + virt = ioremap(phys, PAGE_SIZE); |
| + |
| + return virt + v - phys; |
| + } |
| + |
| + return (void *)((uintptr_t)v); |
| + } |
| + } else if (sizeof(void *) == sizeof(unsigned long long)) { |
| + unsigned long long v; |
| + |
| + if (kstrtoull(str, 0, &v) == 0) { |
| + if ((0xfffffffff0000000ULL & v) < 0x20000000) { |
| + if (virt && v > phys && v < phys + PAGE_SIZE) |
| + return virt + v - phys; |
| + |
| + if (virt != NULL) |
| + iounmap(virt); |
| + |
| + phys = v & ~(PAGE_SIZE - 1); |
| + virt = ioremap(phys, PAGE_SIZE); |
| + |
| + return virt + v - phys; |
| + } |
| + |
| + return (void *)((uintptr_t)v); |
| + } |
| + } else { |
| + pr_warn("unexpected pointer size: sizeof(void *): %zu\n", |
| + sizeof(void *)); |
| + } |
| + |
| + pr_warn("%s(): parsing error: %s\n", __func__, str); |
| + |
| + return NULL; |
| +} |
| + |
| +static int parse_reg_val_from_cmd(void __iomem **preg, unsigned long *pval) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *reg_str; |
| + char *val_str; |
| + int r = 0; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + reg_str = strsep(&c, " "); |
| + val_str = strsep(&c, " "); |
| + |
| + if (preg != NULL && reg_str != NULL) { |
| + *preg = reg_from_str(reg_str); |
| + if (*preg != NULL) |
| + r++; |
| + } |
| + |
| + if (pval != NULL && val_str != NULL && kstrtoul(val_str, 0, pval) == 0) |
| + r++; |
| + |
| + return r; |
| +} |
| + |
| +static int clkdbg_reg_read(struct seq_file *s, void *v) |
| +{ |
| + void __iomem *reg; |
| + unsigned long val; |
| + |
| + if (parse_reg_val_from_cmd(®, NULL) != 1) |
| + return 0; |
| + |
| + seq_printf(s, "readl(0x%p): ", reg); |
| + |
| + val = clk_readl(reg); |
| + seq_printf(s, "0x%08x\n", (u32)val); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_reg_write(struct seq_file *s, void *v) |
| +{ |
| + void __iomem *reg; |
| + unsigned long val; |
| + |
| + if (parse_reg_val_from_cmd(®, &val) != 2) |
| + return 0; |
| + |
| + seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val); |
| + |
| + clk_writel(reg, val); |
| + val = clk_readl(reg); |
| + seq_printf(s, "0x%08x\n", (u32)val); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_reg_set(struct seq_file *s, void *v) |
| +{ |
| + void __iomem *reg; |
| + unsigned long val; |
| + |
| + if (parse_reg_val_from_cmd(®, &val) != 2) |
| + return 0; |
| + |
| + seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val); |
| + |
| + clk_setl(reg, val); |
| + val = clk_readl(reg); |
| + seq_printf(s, "0x%08x\n", (u32)val); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_reg_clr(struct seq_file *s, void *v) |
| +{ |
| + void __iomem *reg; |
| + unsigned long val; |
| + |
| + if (parse_reg_val_from_cmd(®, &val) != 2) |
| + return 0; |
| + |
| + seq_printf(s, "writel(0x%p, 0x%08x): ", reg, (u32)val); |
| + |
| + clk_clrl(reg, val); |
| + val = clk_readl(reg); |
| + seq_printf(s, "0x%08x\n", (u32)val); |
| + |
| + return 0; |
| +} |
| + |
| +static int parse_val_from_cmd(unsigned long *pval) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *val_str; |
| + int r = 0; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + val_str = strsep(&c, " "); |
| + |
| + if (pval != NULL && val_str != NULL && kstrtoul(val_str, 0, pval) == 0) |
| + r++; |
| + |
| + return r; |
| +} |
| + |
| +static int clkdbg_show_flags(struct seq_file *s, void *v) |
| +{ |
| + static const char * const clkdbg_opt_name[] = { |
| + "CLKDBG_EN_SUSPEND_SAVE_1", |
| + "CLKDBG_EN_SUSPEND_SAVE_2", |
| + "CLKDBG_EN_SUSPEND_SAVE_3", |
| + "CLKDBG_EN_LOG_SAVE_POINTS", |
| + }; |
| + |
| + size_t i; |
| + |
| + seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags); |
| + |
| + for (i = 0; i < ARRAY_SIZE(clkdbg_opt_name); i++) { |
| + const char *onff = |
| + has_clkdbg_flag((enum clkdbg_opt)i) ? "ON" : "off"; |
| + |
| + seq_printf(s, "[%2zd]: %3s: %s\n", i, onff, clkdbg_opt_name[i]); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_set_flag(struct seq_file *s, void *v) |
| +{ |
| + unsigned long val; |
| + |
| + if (parse_val_from_cmd(&val) != 1) |
| + return 0; |
| + |
| + set_clkdbg_flag((enum clkdbg_opt)val); |
| + |
| + seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_clr_flag(struct seq_file *s, void *v) |
| +{ |
| + unsigned long val; |
| + |
| + if (parse_val_from_cmd(&val) != 1) |
| + return 0; |
| + |
| + clr_clkdbg_flag((enum clkdbg_opt)val); |
| + |
| + seq_printf(s, "clkdbg_flags: 0x%08x\n", clkdbg_flags); |
| + |
| + return 0; |
| +} |
| + |
| +#if CLKDBG_PM_DOMAIN |
| + |
| +/* |
| + * pm_domain support |
| + */ |
| + |
| +static struct generic_pm_domain **get_all_genpd(void) |
| +{ |
| + static struct generic_pm_domain *pds[TOTAL_PD_NUM]; |
| + static int num_pds; |
| + const size_t maxpd = ARRAY_SIZE(pds); |
| + struct device_node *node; |
| +#if CLKDBG_PM_DOMAIN_API_4_9 |
| + struct platform_device *pdev; |
| + int r; |
| +#endif |
| + |
| + if (num_pds != 0) |
| + goto out; |
| + |
| + node = of_find_node_with_property(NULL, "#power-domain-cells"); |
| + |
| + if (node == NULL) |
| + return NULL; |
| + |
| +#if CLKDBG_PM_DOMAIN_API_4_9 |
| + pdev = platform_device_alloc("traverse", 0); |
| +#endif |
| + |
| + for (num_pds = 0; num_pds < maxpd; num_pds++) { |
| + struct of_phandle_args pa; |
| + |
| + pa.np = node; |
| + pa.args[0] = num_pds; |
| + pa.args_count = 1; |
| + |
| +#if CLKDBG_PM_DOMAIN_API_4_9 |
| + r = of_genpd_add_device(&pa, &pdev->dev); |
| + if (r == -EINVAL) |
| + continue; |
| + else if (r != 0) |
| + pr_warn("%s(): of_genpd_add_device(%d)\n", __func__, r); |
| + pds[num_pds] = pd_to_genpd(pdev->dev.pm_domain); |
| +#if CLKDBG_DROP_GENPD_AS_IN_PARAM |
| + r = pm_genpd_remove_device(&pdev->dev); |
| +#else |
| + r = pm_genpd_remove_device(pds[num_pds], &pdev->dev); |
| +#endif |
| + if (r != 0) |
| + pr_warn("%s(): pm_genpd_remove_device(%d)\n", |
| + __func__, r); |
| +#else |
| + pds[num_pds] = of_genpd_get_from_provider(&pa); |
| +#endif |
| + |
| + if (IS_ERR(pds[num_pds])) { |
| + pds[num_pds] = NULL; |
| + break; |
| + } |
| + } |
| + |
| +#if CLKDBG_PM_DOMAIN_API_4_9 |
| + platform_device_put(pdev); |
| +#endif |
| + |
| +out: |
| + return pds; |
| +} |
| + |
| +static struct platform_device *pdev_from_name(const char *name) |
| +{ |
| + struct generic_pm_domain **pds = get_all_genpd(); |
| + |
| + for (; *pds != NULL; pds++) { |
| + struct pm_domain_data *pdd; |
| + struct generic_pm_domain *pd = *pds; |
| + |
| + if (IS_ERR_OR_NULL(pd)) |
| + continue; |
| + |
| + list_for_each_entry(pdd, &pd->dev_list, list_node) { |
| + struct device *dev = pdd->dev; |
| + struct platform_device *pdev = to_platform_device(dev); |
| + |
| + if (strcmp(name, pdev->name) == 0) |
| + return pdev; |
| + } |
| + } |
| + |
| + return NULL; |
| +} |
| + |
| +static struct generic_pm_domain *genpd_from_name(const char *name) |
| +{ |
| + struct generic_pm_domain **pds = get_all_genpd(); |
| + |
| + for (; *pds != NULL; pds++) { |
| + struct generic_pm_domain *pd = *pds; |
| + |
| + if (IS_ERR_OR_NULL(pd)) |
| + continue; |
| + |
| + if (strcmp(name, pd->name) == 0) |
| + return pd; |
| + } |
| + |
| + return NULL; |
| +} |
| + |
| +struct genpd_dev_state { |
| + struct device *dev; |
| + bool active; |
| + atomic_t usage_count; |
| + unsigned int disable_depth; |
| + enum rpm_status runtime_status; |
| +}; |
| + |
| +struct genpd_state { |
| + struct generic_pm_domain *pd; |
| + enum gpd_status status; |
| + struct genpd_dev_state *dev_state; |
| + int num_dev_state; |
| +}; |
| + |
| +static void save_all_genpd_state(struct genpd_state *genpd_states, |
| + struct genpd_dev_state *genpd_dev_states) |
| +{ |
| + struct genpd_state *pdst = genpd_states; |
| + struct genpd_dev_state *devst = genpd_dev_states; |
| + struct generic_pm_domain **pds = get_all_genpd(); |
| + |
| + for (; *pds != NULL; pds++) { |
| + struct pm_domain_data *pdd; |
| + struct generic_pm_domain *pd = *pds; |
| + |
| + if (IS_ERR_OR_NULL(pd)) |
| + continue; |
| + |
| + pdst->pd = pd; |
| + pdst->status = pd->status; |
| + pdst->dev_state = devst; |
| + pdst->num_dev_state = 0; |
| + |
| + list_for_each_entry(pdd, &pd->dev_list, list_node) { |
| + struct device *d = pdd->dev; |
| + |
| + devst->dev = d; |
| + devst->active = pm_runtime_active(d); |
| + devst->usage_count = d->power.usage_count; |
| + devst->disable_depth = d->power.disable_depth; |
| + devst->runtime_status = d->power.runtime_status; |
| + |
| + devst++; |
| + pdst->num_dev_state++; |
| + } |
| + |
| + pdst++; |
| + } |
| + |
| + pdst->pd = NULL; |
| + devst->dev = NULL; |
| +} |
| + |
| +static void show_genpd_state(struct genpd_state *pdst) |
| +{ |
| + static const char * const gpd_status_name[] = { |
| + "ACTIVE", |
| + "POWER_OFF", |
| + }; |
| + |
| + static const char * const prm_status_name[] = { |
| + "active", |
| + "resuming", |
| + "suspended", |
| + "suspending", |
| + }; |
| + |
| + pr_info("domain_on [pmd_name status]\n"); |
| + pr_info("\tdev_on (dev_name usage_count, disable, status)\n"); |
| + pr_info("------------------------------------------------------\n"); |
| + |
| + for (; pdst->pd != NULL; pdst++) { |
| + int i; |
| + struct generic_pm_domain *pd = pdst->pd; |
| + |
| + if (IS_ERR_OR_NULL(pd)) { |
| + pr_info("pd: 0x%p\n", pd); |
| + continue; |
| + } |
| + |
| + pr_info("%c [%-9s %11s]\n", |
| + (pdst->status == GPD_STATE_ACTIVE) ? '+' : '-', |
| + pd->name, gpd_status_name[pdst->status]); |
| + |
| + for (i = 0; i < pdst->num_dev_state; i++) { |
| + struct genpd_dev_state *devst = &pdst->dev_state[i]; |
| + struct device *dev = devst->dev; |
| + struct platform_device *pdev = to_platform_device(dev); |
| + |
| + pr_info("\t%c (%-19s %3d, %d, %10s)\n", |
| + devst->active ? '+' : '-', |
| + pdev->name, |
| + atomic_read(&dev->power.usage_count), |
| + devst->disable_depth, |
| + prm_status_name[devst->runtime_status]); |
| + mdelay(20); |
| + } |
| + } |
| +} |
| + |
| +static void dump_genpd_state(struct genpd_state *pdst, struct seq_file *s) |
| +{ |
| + static const char * const gpd_status_name[] = { |
| + "ACTIVE", |
| + "POWER_OFF", |
| + }; |
| + |
| + static const char * const prm_status_name[] = { |
| + "active", |
| + "resuming", |
| + "suspended", |
| + "suspending", |
| + }; |
| + |
| + seq_puts(s, "domain_on [pmd_name status]\n"); |
| + seq_puts(s, "\tdev_on (dev_name usage_count, disable, status)\n"); |
| + seq_puts(s, "------------------------------------------------------\n"); |
| + |
| + for (; pdst->pd != NULL; pdst++) { |
| + int i; |
| + struct generic_pm_domain *pd = pdst->pd; |
| + |
| + if (IS_ERR_OR_NULL(pd)) { |
| + seq_printf(s, "pd: 0x%p\n", pd); |
| + continue; |
| + } |
| + |
| + seq_printf(s, "%c [%-9s %11s]\n", |
| + (pdst->status == GPD_STATE_ACTIVE) ? '+' : '-', |
| + pd->name, gpd_status_name[pdst->status]); |
| + |
| + for (i = 0; i < pdst->num_dev_state; i++) { |
| + struct genpd_dev_state *devst = &pdst->dev_state[i]; |
| + struct device *dev = devst->dev; |
| + struct platform_device *pdev = to_platform_device(dev); |
| + |
| + seq_printf(s, "\t%c (%-19s %3d, %d, %10s)\n", |
| + devst->active ? '+' : '-', |
| + pdev->name, |
| + atomic_read(&dev->power.usage_count), |
| + devst->disable_depth, |
| + prm_status_name[devst->runtime_status]); |
| + } |
| + } |
| +} |
| + |
| +static void seq_print_all_genpd(struct seq_file *s) |
| +{ |
| + static struct genpd_dev_state devst[100]; |
| + static struct genpd_state pdst[TOTAL_PD_NUM]; |
| + |
| + save_all_genpd_state(pdst, devst); |
| + dump_genpd_state(pdst, s); |
| +} |
| + |
| +static int clkdbg_dump_genpd(struct seq_file *s, void *v) |
| +{ |
| + seq_print_all_genpd(s); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pm_runtime_enable(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *dev_name; |
| + struct platform_device *pdev; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + dev_name = strsep(&c, " "); |
| + |
| + if (dev_name == NULL) |
| + return 0; |
| + |
| + seq_printf(s, "pm_runtime_enable(%s): ", dev_name); |
| + |
| + pdev = pdev_from_name(dev_name); |
| + if (pdev != NULL) { |
| + pm_runtime_enable(&pdev->dev); |
| + seq_puts(s, "\n"); |
| + } else { |
| + seq_puts(s, "NULL\n"); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pm_runtime_disable(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *dev_name; |
| + struct platform_device *pdev; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + dev_name = strsep(&c, " "); |
| + |
| + if (dev_name == NULL) |
| + return 0; |
| + |
| + seq_printf(s, "pm_runtime_disable(%s): ", dev_name); |
| + |
| + pdev = pdev_from_name(dev_name); |
| + if (pdev != NULL) { |
| + pm_runtime_disable(&pdev->dev); |
| + seq_puts(s, "\n"); |
| + } else { |
| + seq_puts(s, "NULL\n"); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pm_runtime_get_sync(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *dev_name; |
| + struct platform_device *pdev; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + dev_name = strsep(&c, " "); |
| + |
| + if (dev_name == NULL) |
| + return 0; |
| + |
| + seq_printf(s, "pm_runtime_get_sync(%s): ", dev_name); |
| + |
| + pdev = pdev_from_name(dev_name); |
| + if (pdev != NULL) { |
| + int r = pm_runtime_get_sync(&pdev->dev); |
| + |
| + seq_printf(s, "%d\n", r); |
| + } else { |
| + seq_puts(s, "NULL\n"); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pm_runtime_put_sync(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *dev_name; |
| + struct platform_device *pdev; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + dev_name = strsep(&c, " "); |
| + |
| + if (dev_name == NULL) |
| + return 0; |
| + |
| + seq_printf(s, "pm_runtime_put_sync(%s): ", dev_name); |
| + |
| + pdev = pdev_from_name(dev_name); |
| + if (pdev != NULL) { |
| + int r = pm_runtime_put_sync(&pdev->dev); |
| + |
| + seq_printf(s, "%d\n", r); |
| + } else { |
| + seq_puts(s, "NULL\n"); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int genpd_op(const char *gpd_op_name, struct seq_file *s) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *pd_name; |
| + struct generic_pm_domain *genpd; |
| + int gpd_op_id; |
| + int (*gpd_op)(struct generic_pm_domain *genpd); |
| + int r = 0; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + pd_name = strsep(&c, " "); |
| + |
| + if (pd_name == NULL) |
| + return 0; |
| + |
| + if (strcmp(gpd_op_name, "power_on") == 0) |
| + gpd_op_id = 1; |
| + else |
| + gpd_op_id = 0; |
| + |
| + if (strcmp(pd_name, "all") == 0) { |
| + struct generic_pm_domain **pds = get_all_genpd(); |
| + |
| + for (; *pds != NULL; pds++) { |
| + genpd = *pds; |
| + |
| + if (IS_ERR_OR_NULL(genpd)) |
| + continue; |
| + |
| + gpd_op = (gpd_op_id == 1) ? |
| + genpd->power_on : genpd->power_off; |
| + r |= gpd_op(genpd); |
| + } |
| + |
| + seq_printf(s, "%s(%s): %d\n", gpd_op_name, pd_name, r); |
| + |
| + return 0; |
| + } |
| + |
| + genpd = genpd_from_name(pd_name); |
| + if (genpd != NULL) { |
| + gpd_op = (gpd_op_id == 1) ? genpd->power_on : genpd->power_off; |
| + r = gpd_op(genpd); |
| + |
| + seq_printf(s, "%s(%s): %d\n", gpd_op_name, pd_name, r); |
| + } else { |
| + seq_printf(s, "genpd_from_name(%s): NULL\n", pd_name); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pwr_on(struct seq_file *s, void *v) |
| +{ |
| + return genpd_op("power_on", s); |
| +} |
| + |
| +static int clkdbg_pwr_off(struct seq_file *s, void *v) |
| +{ |
| + return genpd_op("power_off", s); |
| +} |
| + |
| +/* |
| + * clkdbg reg_pdrv/runeg_pdrv support |
| + */ |
| + |
| +static int clkdbg_probe(struct platform_device *pdev) |
| +{ |
| + int r; |
| + |
| + pm_runtime_enable(&pdev->dev); |
| + r = pm_runtime_get_sync(&pdev->dev); |
| + if (r != 0) |
| + pr_warn("%s(): pm_runtime_get_sync(%d)\n", __func__, r); |
| + |
| + return r; |
| +} |
| + |
| +static int clkdbg_remove(struct platform_device *pdev) |
| +{ |
| + int r; |
| + |
| + r = pm_runtime_put_sync(&pdev->dev); |
| + if (r != 0) |
| + pr_warn("%s(): pm_runtime_put_sync(%d)\n", __func__, r); |
| + pm_runtime_disable(&pdev->dev); |
| + |
| + return r; |
| +} |
| + |
| +struct pdev_drv { |
| + struct platform_driver pdrv; |
| + struct platform_device *pdev; |
| + struct generic_pm_domain *genpd; |
| +}; |
| + |
| +#define PDEV_DRV(_name) { \ |
| + .pdrv = { \ |
| + .probe = clkdbg_probe, \ |
| + .remove = clkdbg_remove, \ |
| + .driver = { \ |
| + .name = _name, \ |
| + }, \ |
| + }, \ |
| +} |
| + |
| +static struct pdev_drv pderv[] = { |
| + PDEV_DRV("clkdbg-pd0"), |
| + PDEV_DRV("clkdbg-pd1"), |
| + PDEV_DRV("clkdbg-pd2"), |
| + PDEV_DRV("clkdbg-pd3"), |
| + PDEV_DRV("clkdbg-pd4"), |
| + PDEV_DRV("clkdbg-pd5"), |
| + PDEV_DRV("clkdbg-pd6"), |
| + PDEV_DRV("clkdbg-pd7"), |
| + PDEV_DRV("clkdbg-pd8"), |
| + PDEV_DRV("clkdbg-pd9"), |
| + PDEV_DRV("clkdbg-pd10"), |
| + PDEV_DRV("clkdbg-pd11"), |
| + PDEV_DRV("clkdbg-pd12"), |
| + PDEV_DRV("clkdbg-pd13"), |
| + PDEV_DRV("clkdbg-pd14"), |
| + PDEV_DRV("clkdbg-pd15"), |
| + PDEV_DRV("clkdbg-pd16"), |
| + PDEV_DRV("clkdbg-pd17"), |
| + PDEV_DRV("clkdbg-pd18"), |
| + PDEV_DRV("clkdbg-pd19"), |
| + PDEV_DRV("clkdbg-pd20"), |
| + PDEV_DRV("clkdbg-pd21"), |
| + PDEV_DRV("clkdbg-pd22"), |
| + PDEV_DRV("clkdbg-pd23"), |
| + PDEV_DRV("clkdbg-pd24"), |
| + PDEV_DRV("clkdbg-pd25"), |
| + PDEV_DRV("clkdbg-pd26"), |
| + PDEV_DRV("clkdbg-pd27"), |
| + PDEV_DRV("clkdbg-pd28"), |
| + PDEV_DRV("clkdbg-pd29"), |
| + PDEV_DRV("clkdbg-pd30"), |
| + PDEV_DRV("clkdbg-pd31"), |
| +}; |
| + |
| +static void reg_pdev_drv(const char *pdname, struct seq_file *s) |
| +{ |
| + size_t i; |
| + struct generic_pm_domain **pds = get_all_genpd(); |
| + bool allpd = (pdname == NULL || strcmp(pdname, "all") == 0); |
| + int r; |
| + |
| + for (i = 0; i < ARRAY_SIZE(pderv) && *pds != NULL; i++, pds++) { |
| + const char *name = pderv[i].pdrv.driver.name; |
| + struct generic_pm_domain *pd = *pds; |
| + |
| + if (IS_ERR_OR_NULL(pd) || pderv[i].genpd != NULL) |
| + continue; |
| + |
| + if (!allpd && strcmp(pdname, pd->name) != 0) |
| + continue; |
| + |
| + pderv[i].genpd = pd; |
| + |
| + pderv[i].pdev = platform_device_alloc(name, 0); |
| + r = platform_device_add(pderv[i].pdev); |
| + if (r != 0 && s != NULL) |
| + seq_printf(s, "%s(): platform_device_add(%d)\n", |
| + __func__, r); |
| + |
| + r = pm_genpd_add_device(pd, &pderv[i].pdev->dev); |
| + if (r != 0 && s != NULL) |
| + seq_printf(s, "%s(): pm_genpd_add_device(%d)\n", |
| + __func__, r); |
| + r = platform_driver_register(&pderv[i].pdrv); |
| + if (r != 0 && s != NULL) |
| + seq_printf(s, "%s(): platform_driver_register(%d)\n", |
| + __func__, r); |
| + |
| + if (s != NULL) |
| + seq_printf(s, "%s --> %s\n", name, pd->name); |
| + } |
| +} |
| + |
| +static void unreg_pdev_drv(const char *pdname, struct seq_file *s) |
| +{ |
| + ssize_t i; |
| + bool allpd = (pdname == NULL || strcmp(pdname, "all") == 0); |
| + int r; |
| + |
| + for (i = ARRAY_SIZE(pderv) - 1L; i >= 0L; i--) { |
| + const char *name = pderv[i].pdrv.driver.name; |
| + struct generic_pm_domain *pd = pderv[i].genpd; |
| + |
| + if (IS_ERR_OR_NULL(pd)) |
| + continue; |
| + |
| + if (!allpd && strcmp(pdname, pd->name) != 0) |
| + continue; |
| + |
| +#if CLKDBG_DROP_GENPD_AS_IN_PARAM |
| + r = pm_genpd_remove_device(&pderv[i].pdev->dev); |
| +#else |
| + r = pm_genpd_remove_device(pd, &pderv[i].pdev->dev); |
| +#endif |
| + if (r != 0 && s != NULL) |
| + seq_printf(s, "%s(): pm_genpd_remove_device(%d)\n", |
| + __func__, r); |
| + |
| + platform_driver_unregister(&pderv[i].pdrv); |
| + platform_device_unregister(pderv[i].pdev); |
| + |
| + pderv[i].genpd = NULL; |
| + |
| + if (s != NULL) |
| + seq_printf(s, "%s -x- %s\n", name, pd->name); |
| + } |
| +} |
| + |
| +static int clkdbg_reg_pdrv(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *pd_name; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + pd_name = strsep(&c, " "); |
| + |
| + if (pd_name == NULL) |
| + return 0; |
| + |
| + reg_pdev_drv(pd_name, s); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_unreg_pdrv(struct seq_file *s, void *v) |
| +{ |
| + char cmd[sizeof(last_cmd)]; |
| + char *c = cmd; |
| + char *ign; |
| + char *pd_name; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + ign = strsep(&c, " "); |
| + pd_name = strsep(&c, " "); |
| + |
| + if (pd_name == NULL) |
| + return 0; |
| + |
| + unreg_pdev_drv(pd_name, s); |
| + |
| + return 0; |
| +} |
| + |
| +#endif /* CLKDBG_PM_DOMAIN */ |
| + |
| +void reg_pdrv(const char *pdname) |
| +{ |
| +#if CLKDBG_PM_DOMAIN |
| + reg_pdev_drv(pdname, NULL); |
| +#endif |
| +} |
| + |
| +void unreg_pdrv(const char *pdname) |
| +{ |
| +#if CLKDBG_PM_DOMAIN |
| + unreg_pdev_drv(pdname, NULL); |
| +#endif |
| +} |
| + |
| +/* |
| + * Suspend / resume handler |
| + */ |
| + |
| +#include <linux/suspend.h> |
| +#include <linux/syscore_ops.h> |
| + |
| +struct provider_clk_state { |
| + struct provider_clk *pvdck; |
| + bool prepared; |
| + bool enabled; |
| + unsigned int enable_count; |
| + unsigned long rate; |
| + struct clk *parent; |
| +}; |
| + |
| +struct save_point { |
| + u32 spm_pwr_status; |
| + struct provider_clk_state clks_states[TOTAL_CLK_NUM]; |
| +#if CLKDBG_PM_DOMAIN |
| + struct genpd_state genpd_states[TOTAL_PD_NUM]; |
| + struct genpd_dev_state genpd_dev_states[100]; |
| +#endif |
| +}; |
| + |
| +static struct save_point save_point_1; |
| +static struct save_point save_point_2; |
| +static struct save_point save_point_3; |
| + |
| +static void save_pwr_status(u32 *spm_pwr_status) |
| +{ |
| + *spm_pwr_status = read_spm_pwr_status(); |
| +} |
| + |
| +static void save_all_clks_state(struct provider_clk_state *clks_states, |
| + u32 spm_pwr_status) |
| +{ |
| + struct provider_clk *pvdck = get_all_provider_clks(); |
| + struct provider_clk_state *st = clks_states; |
| + |
| + for (; pvdck->ck != NULL; pvdck++, st++) { |
| + struct clk *c = pvdck->ck; |
| + struct clk_hw *c_hw = __clk_get_hw(c); |
| + |
| + st->pvdck = pvdck; |
| + st->prepared = clk_hw_is_prepared(c_hw); |
| + st->enabled = clk_hw_pwr_is_on(c_hw, spm_pwr_status, |
| + pvdck->pwr_mask); |
| + st->enable_count = __clk_get_enable_count(c); |
| + st->rate = clk_hw_get_rate(c_hw); |
| + st->parent = IS_ERR_OR_NULL(c) ? NULL : clk_get_parent(c); |
| + } |
| +} |
| + |
| +static void show_provider_clk_state(struct provider_clk_state *st) |
| +{ |
| + struct provider_clk *pvdck = st->pvdck; |
| + struct clk_hw *c_hw = __clk_get_hw(pvdck->ck); |
| + |
| + pr_info("[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n", |
| + pvdck->provider_name != NULL ? pvdck->provider_name : "/ ", |
| + clk_hw_get_name(c_hw), |
| + st->enabled ? "ON" : "off", |
| + st->prepared, |
| + st->enable_count, |
| + st->rate, |
| + st->parent != NULL ? |
| + clk_hw_get_name(__clk_get_hw(st->parent)) : "- "); |
| + mdelay(20); |
| +} |
| + |
| +static void dump_provider_clk_state(struct provider_clk_state *st, |
| + struct seq_file *s) |
| +{ |
| + struct provider_clk *pvdck = st->pvdck; |
| + struct clk_hw *c_hw = __clk_get_hw(pvdck->ck); |
| + |
| + seq_printf(s, "[%10s: %-17s: %3s, %3d, %3d, %10ld, %17s]\n", |
| + pvdck->provider_name != NULL ? pvdck->provider_name : "/ ", |
| + clk_hw_get_name(c_hw), |
| + st->enabled ? "ON" : "off", |
| + st->prepared, |
| + st->enable_count, |
| + st->rate, |
| + st->parent != NULL ? |
| + clk_hw_get_name(__clk_get_hw(st->parent)) : "- "); |
| +} |
| + |
| +static void show_save_point(struct save_point *sp) |
| +{ |
| + struct provider_clk_state *st = sp->clks_states; |
| + |
| + for (; st->pvdck != NULL; st++) |
| + show_provider_clk_state(st); |
| + |
| + pr_info("\n"); |
| + show_pwr_status(sp->spm_pwr_status); |
| + |
| +#if CLKDBG_PM_DOMAIN |
| + pr_info("\n"); |
| + show_genpd_state(sp->genpd_states); |
| +#endif |
| +} |
| + |
| +static void store_save_point(struct save_point *sp) |
| +{ |
| + save_pwr_status(&sp->spm_pwr_status); |
| + save_all_clks_state(sp->clks_states, sp->spm_pwr_status); |
| + |
| +#if CLKDBG_PM_DOMAIN |
| + save_all_genpd_state(sp->genpd_states, sp->genpd_dev_states); |
| +#endif |
| + |
| + if (has_clkdbg_flag(CLKDBG_EN_LOG_SAVE_POINTS)) |
| + show_save_point(sp); |
| +} |
| + |
| +static void dump_save_point(struct save_point *sp, struct seq_file *s) |
| +{ |
| + struct provider_clk_state *st = sp->clks_states; |
| + |
| + for (; st->pvdck != NULL; st++) |
| + dump_provider_clk_state(st, s); |
| + |
| + seq_puts(s, "\n"); |
| + dump_pwr_status(sp->spm_pwr_status, s); |
| + |
| +#if CLKDBG_PM_DOMAIN |
| + seq_puts(s, "\n"); |
| + dump_genpd_state(sp->genpd_states, s); |
| +#endif |
| +} |
| + |
| +static int clkdbg_dump_suspend_clks_1(struct seq_file *s, void *v) |
| +{ |
| + dump_save_point(&save_point_1, s); |
| + return 0; |
| +} |
| + |
| +static int clkdbg_dump_suspend_clks_2(struct seq_file *s, void *v) |
| +{ |
| + dump_save_point(&save_point_2, s); |
| + return 0; |
| +} |
| + |
| +static int clkdbg_dump_suspend_clks_3(struct seq_file *s, void *v) |
| +{ |
| + dump_save_point(&save_point_3, s); |
| + return 0; |
| +} |
| + |
| +static int clkdbg_dump_suspend_clks(struct seq_file *s, void *v) |
| +{ |
| + if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3) && |
| + save_point_3.spm_pwr_status != 0U) |
| + return clkdbg_dump_suspend_clks_3(s, v); |
| + else if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_2) && |
| + save_point_2.spm_pwr_status != 0U) |
| + return clkdbg_dump_suspend_clks_2(s, v); |
| + else if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_1) && |
| + save_point_1.spm_pwr_status != 0U) |
| + return clkdbg_dump_suspend_clks_1(s, v); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_pm_event_handler(struct notifier_block *nb, |
| + unsigned long event, void *ptr) |
| +{ |
| + switch (event) { |
| + case PM_HIBERNATION_PREPARE: |
| + case PM_SUSPEND_PREPARE: |
| + /* suspend */ |
| + if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_1)) { |
| + store_save_point(&save_point_1); |
| + return NOTIFY_OK; |
| + } |
| + |
| + break; |
| + case PM_POST_HIBERNATION: |
| + case PM_POST_SUSPEND: |
| + /* resume */ |
| + break; |
| + } |
| + |
| + return NOTIFY_DONE; |
| +} |
| + |
| +static struct notifier_block clkdbg_pm_notifier = { |
| + .notifier_call = clkdbg_pm_event_handler, |
| +}; |
| + |
| +static int clkdbg_syscore_suspend(void) |
| +{ |
| + if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_2)) |
| + store_save_point(&save_point_2); |
| + |
| + return 0; |
| +} |
| + |
| +static void clkdbg_syscore_resume(void) |
| +{ |
| +} |
| + |
| +static struct syscore_ops clkdbg_syscore_ops = { |
| + .suspend = clkdbg_syscore_suspend, |
| + .resume = clkdbg_syscore_resume, |
| +}; |
| + |
| +static int __init clkdbg_pm_init(void) |
| +{ |
| + int r; |
| + |
| + register_syscore_ops(&clkdbg_syscore_ops); |
| + r = register_pm_notifier(&clkdbg_pm_notifier); |
| + if (r != 0) |
| + pr_warn("%s(): register_pm_notifier(%d)\n", __func__, r); |
| + |
| + return r; |
| +} |
| +subsys_initcall(clkdbg_pm_init); |
| + |
| +static int clkdbg_suspend_ops_valid(suspend_state_t state) |
| +{ |
| + return state == PM_SUSPEND_MEM ? 1 : 0; |
| +} |
| + |
| +static int clkdbg_suspend_ops_begin(suspend_state_t state) |
| +{ |
| + return 0; |
| +} |
| + |
| +static int clkdbg_suspend_ops_prepare(void) |
| +{ |
| + return 0; |
| +} |
| + |
| +static int clkdbg_suspend_ops_enter(suspend_state_t state) |
| +{ |
| + if (has_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3)) |
| + store_save_point(&save_point_3); |
| + |
| + return 0; |
| +} |
| + |
| +static void clkdbg_suspend_ops_finish(void) |
| +{ |
| +} |
| + |
| +static void clkdbg_suspend_ops_end(void) |
| +{ |
| +} |
| + |
| +static const struct platform_suspend_ops clkdbg_suspend_ops = { |
| + .valid = clkdbg_suspend_ops_valid, |
| + .begin = clkdbg_suspend_ops_begin, |
| + .prepare = clkdbg_suspend_ops_prepare, |
| + .enter = clkdbg_suspend_ops_enter, |
| + .finish = clkdbg_suspend_ops_finish, |
| + .end = clkdbg_suspend_ops_end, |
| +}; |
| + |
| +static int clkdbg_suspend_set_ops(struct seq_file *s, void *v) |
| +{ |
| + suspend_set_ops(&clkdbg_suspend_ops); |
| + |
| + return 0; |
| +} |
| + |
| +static const struct cmd_fn *custom_cmds; |
| + |
| +void set_custom_cmds(const struct cmd_fn *cmds) |
| +{ |
| + custom_cmds = cmds; |
| +} |
| + |
| +static int clkdbg_cmds(struct seq_file *s, void *v); |
| + |
| +static const struct cmd_fn common_cmds[] = { |
| + CMDFN("dump_regs", seq_print_regs), |
| + CMDFN("dump_regs2", clkdbg_dump_regs2), |
| + CMDFN("dump_state", clkdbg_dump_state_all), |
| + CMDFN("dump_clks", clkdbg_dump_provider_clks), |
| + CMDFN("dump_muxes", clkdbg_dump_muxes), |
| + CMDFN("fmeter", seq_print_fmeter_all), |
| + CMDFN("pwr_status", clkdbg_pwr_status), |
| + CMDFN("prepare", clkdbg_prepare), |
| + CMDFN("unprepare", clkdbg_unprepare), |
| + CMDFN("enable", clkdbg_enable), |
| + CMDFN("disable", clkdbg_disable), |
| + CMDFN("prepare_enable", clkdbg_prepare_enable), |
| + CMDFN("disable_unprepare", clkdbg_disable_unprepare), |
| + CMDFN("prepare_enable_provider", clkdbg_prepare_enable_provider), |
| + CMDFN("disable_unprepare_provider", clkdbg_disable_unprepare_provider), |
| + CMDFN("set_parent", clkdbg_set_parent), |
| + CMDFN("set_rate", clkdbg_set_rate), |
| + CMDFN("reg_read", clkdbg_reg_read), |
| + CMDFN("reg_write", clkdbg_reg_write), |
| + CMDFN("reg_set", clkdbg_reg_set), |
| + CMDFN("reg_clr", clkdbg_reg_clr), |
| + CMDFN("show_flags", clkdbg_show_flags), |
| + CMDFN("set_flag", clkdbg_set_flag), |
| + CMDFN("clr_flag", clkdbg_clr_flag), |
| +#if CLKDBG_PM_DOMAIN |
| + CMDFN("dump_genpd", clkdbg_dump_genpd), |
| + CMDFN("pm_runtime_enable", clkdbg_pm_runtime_enable), |
| + CMDFN("pm_runtime_disable", clkdbg_pm_runtime_disable), |
| + CMDFN("pm_runtime_get_sync", clkdbg_pm_runtime_get_sync), |
| + CMDFN("pm_runtime_put_sync", clkdbg_pm_runtime_put_sync), |
| + CMDFN("pwr_on", clkdbg_pwr_on), |
| + CMDFN("pwr_off", clkdbg_pwr_off), |
| + CMDFN("reg_pdrv", clkdbg_reg_pdrv), |
| + CMDFN("unreg_pdrv", clkdbg_unreg_pdrv), |
| +#endif /* CLKDBG_PM_DOMAIN */ |
| + CMDFN("suspend_set_ops", clkdbg_suspend_set_ops), |
| + CMDFN("dump_suspend_clks", clkdbg_dump_suspend_clks), |
| + CMDFN("dump_suspend_clks_1", clkdbg_dump_suspend_clks_1), |
| + CMDFN("dump_suspend_clks_2", clkdbg_dump_suspend_clks_2), |
| + CMDFN("dump_suspend_clks_3", clkdbg_dump_suspend_clks_3), |
| + CMDFN("cmds", clkdbg_cmds), |
| + {} |
| +}; |
| + |
| +static int clkdbg_cmds(struct seq_file *s, void *v) |
| +{ |
| + const struct cmd_fn *cf; |
| + |
| + for (cf = common_cmds; cf->cmd != NULL; cf++) |
| + seq_printf(s, "%s\n", cf->cmd); |
| + |
| + for (cf = custom_cmds; cf != NULL && cf->cmd != NULL; cf++) |
| + seq_printf(s, "%s\n", cf->cmd); |
| + |
| + seq_puts(s, "\n"); |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_show(struct seq_file *s, void *v) |
| +{ |
| + const struct cmd_fn *cf; |
| + char cmd[sizeof(last_cmd)]; |
| + |
| + strncpy(cmd, last_cmd, sizeof(cmd)); |
| + cmd[sizeof(cmd) - 1UL] = '\0'; |
| + |
| + for (cf = custom_cmds; cf != NULL && cf->cmd != NULL; cf++) { |
| + char *c = cmd; |
| + char *token = strsep(&c, " "); |
| + |
| + if (strcmp(cf->cmd, token) == 0) |
| + return cf->fn(s, v); |
| + } |
| + |
| + for (cf = common_cmds; cf->cmd != NULL; cf++) { |
| + char *c = cmd; |
| + char *token = strsep(&c, " "); |
| + |
| + if (strcmp(cf->cmd, token) == 0) |
| + return cf->fn(s, v); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int clkdbg_open(struct inode *inode, struct file *file) |
| +{ |
| + return single_open(file, clkdbg_show, NULL); |
| +} |
| + |
| +static ssize_t clkdbg_write( |
| + struct file *file, |
| + const char __user *buffer, |
| + size_t count, |
| + loff_t *data) |
| +{ |
| + size_t len = 0; |
| + |
| + len = (count < (sizeof(last_cmd) - 1UL)) ? |
| + count : (sizeof(last_cmd) - 1UL); |
| + if (copy_from_user(last_cmd, buffer, len) != 0UL) |
| + return 0; |
| + |
| + last_cmd[len] = '\0'; |
| + |
| + if (last_cmd[len - 1UL] == '\n') |
| + last_cmd[len - 1UL] = '\0'; |
| + |
| + return (ssize_t)len; |
| +} |
| + |
| +#if 0 |
| +static const struct proc_ops clkdbg_fops = { |
| + .proc_open = clkdbg_open, |
| + .proc_read = seq_read, |
| + .proc_write = clkdbg_write, |
| + .proc_lseek = seq_lseek, |
| + .proc_release = single_release, |
| +}; |
| +#else |
| +static const struct file_operations clkdbg_fops = { |
| + .owner = THIS_MODULE, |
| + .open = clkdbg_open, |
| + .read = seq_read, |
| + .write = clkdbg_write, |
| + .llseek = seq_lseek, |
| + .release = single_release, |
| +}; |
| +#endif |
| + |
| +/* |
| + * init functions |
| + */ |
| + |
| +static int __init clkdbg_debug_init(void) |
| +{ |
| + struct proc_dir_entry *entry; |
| + |
| + entry = proc_create("clkdbg", 0644, NULL, &clkdbg_fops); |
| + if (entry == 0) |
| + return -ENOMEM; |
| + |
| + set_clkdbg_flag(CLKDBG_EN_SUSPEND_SAVE_3); |
| + |
| + return 0; |
| +} |
| +module_init(clkdbg_debug_init); |
| diff --git a/drivers/clk/mediatek/clkdbg.h b/drivers/clk/mediatek/clkdbg.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..3ecd48d6626020493889046b5e9279b3ad83bfb6 |
| --- /dev/null |
| +++ b/drivers/clk/mediatek/clkdbg.h |
| @@ -0,0 +1,83 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + */ |
| + |
| +struct seq_file; |
| + |
| +#define clk_readl(addr) readl(addr) |
| +#define clk_writel(addr, val) \ |
| + do { writel(val, addr); wmb(); } while (0) /* sync write */ |
| +#define clk_setl(addr, val) clk_writel(addr, clk_readl(addr) | (val)) |
| +#define clk_clrl(addr, val) clk_writel(addr, clk_readl(addr) & ~(val)) |
| + |
| +enum FMETER_TYPE { |
| + FT_NULL, |
| + ABIST, |
| + CKGEN |
| +}; |
| + |
| +struct fmeter_clk { |
| + enum FMETER_TYPE type; |
| + u32 id; |
| + const char *name; |
| +}; |
| + |
| +struct regbase { |
| + u32 phys; |
| + void __iomem *virt; |
| + const char *name; |
| +}; |
| + |
| +struct regname { |
| + struct regbase *base; |
| + u32 ofs; |
| + const char *name; |
| +}; |
| + |
| +#define ADDR(rn) (rn->base->virt + rn->ofs) |
| +#define PHYSADDR(rn) (rn->base->phys + rn->ofs) |
| + |
| +struct cmd_fn { |
| + const char *cmd; |
| + int (*fn)(struct seq_file *s, void *v); |
| +}; |
| + |
| +#define CMDFN(_cmd, _fn) { \ |
| + .cmd = _cmd, \ |
| + .fn = _fn, \ |
| +} |
| + |
| +struct provider_clk { |
| + const char *provider_name; |
| + u32 idx; |
| + struct clk *ck; |
| + u32 pwr_mask; |
| +}; |
| + |
| +struct clkdbg_ops { |
| + const struct fmeter_clk *(*get_all_fmeter_clks)(void); |
| + void *(*prepare_fmeter)(void); |
| + void (*unprepare_fmeter)(void *data); |
| + u32 (*fmeter_freq)(const struct fmeter_clk *fclk); |
| + const struct regname *(*get_all_regnames)(void); |
| + const char * const *(*get_all_clk_names)(void); |
| + const char * const *(*get_pwr_names)(void); |
| + void (*setup_provider_clk)(struct provider_clk *pvdck); |
| + u32 (*get_spm_pwr_status)(void); |
| +}; |
| + |
| +void set_clkdbg_ops(const struct clkdbg_ops *ops); |
| +void set_custom_cmds(const struct cmd_fn *cmds); |
| + |
| +struct provider_clk *get_all_provider_clks(void); |
| +const char *get_last_cmd(void); |
| + |
| +void reg_pdrv(const char *pdname); |
| +void unreg_pdrv(const char *pdname); |
| +void prepare_enable_provider(const char *pvd); |
| +void disable_unprepare_provider(const char *pvd); |
| + |
| +void print_regs(void); |
| +void print_fmeter_all(void); |
| diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c |
| old mode 100644 |
| new mode 100755 |
| index cb939c071b0ccabeeda89331043002967209cf17..89916acf0bc3290101194ae03b801f8c0aef8a39 |
| --- a/drivers/clk/mediatek/reset.c |
| +++ b/drivers/clk/mediatek/reset.c |
| @@ -25,7 +25,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, |
| struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); |
| unsigned int reg = data->regofs + ((id / 32) << 4); |
| |
| - return regmap_write(data->regmap, reg, 1); |
| + return regmap_write(data->regmap, reg, BIT(id % 32)); |
| } |
| |
| static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, |
| @@ -34,7 +34,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, |
| struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); |
| unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; |
| |
| - return regmap_write(data->regmap, reg, 1); |
| + return regmap_write(data->regmap, reg, BIT(id % 32)); |
| } |
| |
| static int mtk_reset_assert(struct reset_controller_dev *rcdev, |
| diff --git a/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_devfreq.c b/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_devfreq.c |
| index 177398bea550ab676f05440c1f981695e864991d..f027b0113de95610abfeaa881ed8a5c9743eb905 100644 |
| --- a/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_devfreq.c |
| +++ b/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_devfreq.c |
| @@ -91,6 +91,33 @@ static void opp_translate(struct kbase_device *kbdev, unsigned long freq, |
| } |
| } |
| |
| +static void voltage_range_check(struct kbase_device *kbdev, |
| + unsigned long *voltages) |
| +{ |
| + if (kbdev->devfreq_ops.voltage_range_check) |
| + kbdev->devfreq_ops.voltage_range_check(kbdev, voltages); |
| +} |
| + |
| +static int set_frequency(struct kbase_device *kbdev, unsigned long freq) |
| +{ |
| + int err = 0, i; |
| + if (kbdev->devfreq_ops.set_frequency) |
| + return kbdev->devfreq_ops.set_frequency(kbdev, freq); |
| + |
| + for (i = 0; i < kbdev->nr_clocks; i++) { |
| + if (kbdev->clocks[i]) { |
| + err = clk_set_rate(kbdev->clocks[i], freq); |
| + if (!err) { |
| + kbdev->current_freqs[i] = freq; |
| + } else { |
| + return err; |
| + } |
| + } |
| + } |
| + return err; |
| +} |
| + |
| + |
| static int |
| kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) |
| { |
| @@ -101,6 +128,7 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) |
| unsigned long volts[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; |
| unsigned int i; |
| u64 core_mask; |
| + int err; |
| |
| nominal_freq = *target_freq; |
| |
| @@ -128,6 +156,7 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) |
| } |
| |
| opp_translate(kbdev, nominal_freq, &core_mask, freqs, volts); |
| + voltage_range_check(kbdev, volts); |
| |
| #ifdef CONFIG_REGULATOR |
| /* Regulators and clocks work in pairs: every clock has a regulator, |
| @@ -162,19 +191,11 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) |
| } |
| #endif |
| |
| - for (i = 0; i < kbdev->nr_clocks; i++) { |
| - if (kbdev->clocks[i]) { |
| - int err; |
| - |
| - err = clk_set_rate(kbdev->clocks[i], freqs[i]); |
| - if (!err) { |
| - kbdev->current_freqs[i] = freqs[i]; |
| - } else { |
| - dev_err(dev, "Failed to set clock %lu (target %lu)\n", |
| - freqs[i], *target_freq); |
| - return err; |
| - } |
| - } |
| + err = set_frequency(kbdev, freqs[0]); |
| + if (err) { |
| + dev_err(dev, "Failed to set clock %lu (target %lu)\n", |
| + freqs[0], *target_freq); |
| + return err; |
| } |
| |
| #ifdef CONFIG_REGULATOR |
| diff --git a/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_gpuprops_backend.c b/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_gpuprops_backend.c |
| index ae3ed9ca41998e4c89493070e4153af1dd04631d..bc03c7e728de498678eeb55c569341030f5f67c4 100644 |
| --- a/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_gpuprops_backend.c |
| +++ b/drivers/gpu/arm/valhall/backend/gpu/mali_kbase_gpuprops_backend.c |
| @@ -38,6 +38,11 @@ void kbase_backend_gpuprops_get(struct kbase_device *kbdev, |
| |
| /* Fill regdump with the content of the relevant registers */ |
| regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); |
| + if (regdump->gpu_id == 0x90930000) { |
| + u32 new_id = 0x90910000; |
| + dev_err(kbdev->dev, "gpu_id=%08x HACK to %08x", regdump->gpu_id, new_id); |
| + regdump->gpu_id = new_id; |
| + } |
| |
| regdump->l2_features = kbase_reg_read(kbdev, |
| GPU_CONTROL_REG(L2_FEATURES)); |
| diff --git a/drivers/gpu/arm/valhall/mali_kbase_core_linux.c b/drivers/gpu/arm/valhall/mali_kbase_core_linux.c |
| old mode 100644 |
| new mode 100755 |
| index 0da37270ac4837a7a5cc3ca5c64a24f10b9bdbfe..131e72d2d59651dfdbf58adb36fa553b52246d32 |
| --- a/drivers/gpu/arm/valhall/mali_kbase_core_linux.c |
| +++ b/drivers/gpu/arm/valhall/mali_kbase_core_linux.c |
| @@ -3389,10 +3389,7 @@ int power_control_init(struct kbase_device *kbdev) |
| int err = 0; |
| unsigned int i; |
| #if defined(CONFIG_REGULATOR) |
| - static const char *regulator_names[] = { |
| - "mali", "shadercores" |
| - }; |
| - BUILD_BUG_ON(ARRAY_SIZE(regulator_names) < BASE_MAX_NR_CLOCKS_REGULATORS); |
| + const char *regulator_names[BASE_MAX_NR_CLOCKS_REGULATORS]; |
| #endif /* CONFIG_REGULATOR */ |
| |
| if (!kbdev) |
| @@ -3401,6 +3398,37 @@ int power_control_init(struct kbase_device *kbdev) |
| pdev = to_platform_device(kbdev->dev); |
| |
| #if defined(CONFIG_REGULATOR) |
| + |
| + kbdev->nr_regulators = of_property_count_strings(kbdev->dev->of_node, |
| + "supply-names"); |
| + |
| + if (kbdev->nr_regulators == -EINVAL) { |
| + /* The 'supply-names' is optional; if not there assume default */ |
| +#if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE) || \ |
| + defined(LSK_OPPV2_BACKPORT) |
| + regulator_names[0] = "mali"; |
| + regulator_names[1] = "shadercores"; |
| +#else |
| + regulator_names[0] = "mali"; |
| +#endif |
| + } else if (kbdev->nr_regulators > BASE_MAX_NR_CLOCKS_REGULATORS) { |
| + dev_err(&pdev->dev, "Too many regulators: %d > %d\n", |
| + kbdev->nr_regulators, BASE_MAX_NR_CLOCKS_REGULATORS); |
| + return -EINVAL; |
| + } else if (kbdev->nr_regulators < 0) { |
| + err = kbdev->nr_regulators; |
| + } else { |
| + err = of_property_read_string_array(kbdev->dev->of_node, |
| + "supply-names", |
| + regulator_names, |
| + kbdev->nr_regulators); |
| + } |
| + |
| + if (err < 0) { |
| + dev_err(&pdev->dev, "Error reading supply-names: %d\n", err); |
| + return err; |
| + } |
| + |
| /* Since the error code EPROBE_DEFER causes the entire probing |
| * procedure to be restarted from scratch at a later time, |
| * all regulators will be released before returning. |
| @@ -3444,22 +3472,6 @@ int power_control_init(struct kbase_device *kbdev) |
| kbdev->clocks[i] = NULL; |
| break; |
| } |
| - |
| - err = clk_prepare_enable(kbdev->clocks[i]); |
| - if (err) { |
| - dev_err(kbdev->dev, |
| - "Failed to prepare and enable clock (%d)\n", |
| - err); |
| - clk_put(kbdev->clocks[i]); |
| - break; |
| - } |
| - } |
| - if (err == -EPROBE_DEFER) { |
| - while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) { |
| - clk_disable_unprepare(kbdev->clocks[--i]); |
| - clk_put(kbdev->clocks[i]); |
| - } |
| - goto clocks_probe_defer; |
| } |
| |
| kbdev->nr_clocks = i; |
| @@ -3491,12 +3503,6 @@ int power_control_init(struct kbase_device *kbdev) |
| #endif /* KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE */ |
| return 0; |
| |
| -clocks_probe_defer: |
| -#if defined(CONFIG_REGULATOR) |
| - for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) |
| - regulator_put(kbdev->regulators[i]); |
| -#endif |
| - return err; |
| #endif /* KERNEL_VERSION(3, 18, 0) > LINUX_VERSION_CODE */ |
| } |
| |
| @@ -3524,8 +3530,6 @@ void power_control_term(struct kbase_device *kbdev) |
| |
| for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { |
| if (kbdev->clocks[i]) { |
| - if (__clk_is_enabled(kbdev->clocks[i])) |
| - clk_disable_unprepare(kbdev->clocks[i]); |
| clk_put(kbdev->clocks[i]); |
| kbdev->clocks[i] = NULL; |
| } else |
| @@ -4192,6 +4196,7 @@ static const struct of_device_id kbase_dt_ids[] = { |
| { .compatible = "arm,malit6xx" }, |
| { .compatible = "arm,mali-midgard" }, |
| { .compatible = "arm,mali-bifrost" }, |
| + { .compatible = "arm,mali-valhall" }, |
| { /* sentinel */ } |
| }; |
| MODULE_DEVICE_TABLE(of, kbase_dt_ids); |
| diff --git a/drivers/gpu/arm/valhall/mali_kbase_defs.h b/drivers/gpu/arm/valhall/mali_kbase_defs.h |
| old mode 100644 |
| new mode 100755 |
| index bd2301f383df5bf4a7641c18638562d731fbb25a..0ae29b55419d67fd314e56011af9a9e1c42c8ccb |
| --- a/drivers/gpu/arm/valhall/mali_kbase_defs.h |
| +++ b/drivers/gpu/arm/valhall/mali_kbase_defs.h |
| @@ -108,6 +108,8 @@ |
| */ |
| #define BASE_MAX_NR_AS 16 |
| |
| +#define MAX_PM_DOMAINS 5 |
| + |
| /* mmu */ |
| #define MIDGARD_MMU_LEVEL(x) (x) |
| |
| @@ -891,6 +893,9 @@ struct kbase_device { |
| |
| struct clk *clocks[BASE_MAX_NR_CLOCKS_REGULATORS]; |
| unsigned int nr_clocks; |
| + /* pm_domains for devices with more than one. */ |
| + struct device *pm_domain_devs[MAX_PM_DOMAINS]; |
| + int num_pm_domains; |
| #ifdef CONFIG_REGULATOR |
| struct regulator *regulators[BASE_MAX_NR_CLOCKS_REGULATORS]; |
| unsigned int nr_regulators; |
| @@ -990,6 +995,17 @@ struct kbase_device { |
| struct kbase_devfreq_queue_info devfreq_queue; |
| #endif |
| |
| + struct { |
| + void (*voltage_range_check)(struct kbase_device *kbdev, |
| + unsigned long *voltages); |
| +#ifdef CONFIG_REGULATOR |
| + int (*set_voltages)(struct kbase_device *kbdev, |
| + unsigned long *voltages, bool inc); |
| +#endif |
| + int (*set_frequency)(struct kbase_device *kbdev, |
| + unsigned long freq); |
| + } devfreq_ops; |
| + |
| #ifdef CONFIG_DEVFREQ_THERMAL |
| #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) |
| struct devfreq_cooling_device *devfreq_cooling; |
| diff --git a/drivers/gpu/arm/valhall/mali_kbase_dummy_job_wa.c b/drivers/gpu/arm/valhall/mali_kbase_dummy_job_wa.c |
| index 5830e8e74e434777fecdb89f808a212be556c375..411a8acd66f8687994eed3866e0f5dc656cb2d8c 100644 |
| --- a/drivers/gpu/arm/valhall/mali_kbase_dummy_job_wa.c |
| +++ b/drivers/gpu/arm/valhall/mali_kbase_dummy_job_wa.c |
| @@ -295,6 +295,7 @@ static int check_wa_validity(struct kbase_device *kbdev, |
| ret = SKIP_WA; |
| } else if ((major_revision > 0) && !wa_blob_present) |
| ret = SKIP_WA; |
| + ret = SKIP_WA; |
| break; |
| case GPU_ID2_PRODUCT_TBEX: |
| /* WA needed for r0p0 only */ |
| diff --git a/drivers/gpu/arm/valhall/platform/mt8192/Kbuild b/drivers/gpu/arm/valhall/platform/mt8192/Kbuild |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..72bbe2311639bbce8af727eea466c52f6e5dfa62 |
| --- /dev/null |
| +++ b/drivers/gpu/arm/valhall/platform/mt8192/Kbuild |
| @@ -0,0 +1,14 @@ |
| +# Copyright (C) 2018 MediaTek Inc. |
| +# |
| +# This program is free software; you can redistribute it and/or modify |
| +# it under the terms of the GNU General Public License version 2 as |
| +# published by the Free Software Foundation. |
| +# |
| +# This program is distributed in the hope that it will be useful, |
| +# but WITHOUT ANY WARRANTY; without even the implied warranty of |
| +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| +# See http://www.gnu.org/licenses/gpl-2.0.html for more details. |
| + |
| +mali_kbase-y += \ |
| + $(MALI_PLATFORM_DIR)/mali_kbase_config_mt8192.o \ |
| + $(MALI_PLATFORM_DIR)/mali_kbase_runtime_pm.o |
| diff --git a/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_mt8192.c b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_mt8192.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..a2737171371195af712ab092556d314751ec5517 |
| --- /dev/null |
| +++ b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_mt8192.c |
| @@ -0,0 +1,37 @@ |
| +/* |
| + * Copyright (C) 2018 MediaTek Inc. |
| + * |
| + * This program is free software; you can redistribute it and/or modify |
| + * it under the terms of the GNU General Public License version 2 as |
| + * published by the Free Software Foundation. |
| + * |
| + * This program is distributed in the hope that it will be useful, |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. |
| + */ |
| + |
| + |
| +#include <mali_kbase_config.h> |
| + |
| +int kbase_platform_early_init(void) |
| +{ |
| + /* Nothing needed at this stage */ |
| + return 0; |
| +} |
| + |
| +static struct kbase_platform_config dummy_platform_config; |
| + |
| +struct kbase_platform_config *kbase_get_platform_config(void) |
| +{ |
| + return &dummy_platform_config; |
| +} |
| + |
| +int kbase_platform_register(void) |
| +{ |
| + return 0; |
| +} |
| + |
| +void kbase_platform_unregister(void) |
| +{ |
| +} |
| diff --git a/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_platform.h b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_platform.h |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..dbfa8fa413a148d47d6f36541e0292829ed8883b |
| --- /dev/null |
| +++ b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_config_platform.h |
| @@ -0,0 +1,98 @@ |
| +/* |
| + * Copyright (C) 2018 MediaTek Inc. |
| + * |
| + * This program is free software; you can redistribute it and/or modify |
| + * it under the terms of the GNU General Public License version 2 as |
| + * published by the Free Software Foundation. |
| + * |
| + * This program is distributed in the hope that it will be useful, |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. |
| + */ |
| + |
| +struct mfg_base { |
| + struct clk *clk_mux; |
| + struct clk *clk_main_parent; |
| + struct clk *clk_sub_parent; |
| + struct clk *subsys_mfg_cg; |
| + void __iomem *g_mfg_base; |
| + bool is_powered; |
| +}; |
| + |
| +/* Definition for PMIC regulators */ |
| +#define VSRAM_GPU_MAX_VOLT (843750) /* uV */ |
| +#define VSRAM_GPU_MIN_VOLT (750000) /* uV */ |
| +#define VGPU_MAX_VOLT (843750) /* uV */ |
| +#define VGPU_MIN_VOLT (562500) /* uV */ |
| + |
| +#define MIN_VOLT_BIAS (0) /* uV */ |
| +#define MAX_VOLT_BIAS (250000) /* uV */ |
| +#define VOLT_TOL (125) /* uV */ |
| + |
| +#define GPU_CORE_NUM 5 |
| + |
| +/** |
| + * Maximum frequency GPU will be clocked at. Given in kHz. |
| + * This must be specified as there is no default value. |
| + * |
| + * Attached value: number in kHz |
| + * Default value: NA |
| + */ |
| +#define GPU_FREQ_KHZ_MAX (950000) |
| +/** |
| + * Minimum frequency GPU will be clocked at. Given in kHz. |
| + * This must be specified as there is no default value. |
| + * |
| + * Attached value: number in kHz |
| + * Default value: NA |
| + */ |
| +#define GPU_FREQ_KHZ_MIN (358000) |
| + |
| +/** |
| + * CPU_SPEED_FUNC - A pointer to a function that calculates the CPU clock |
| + * |
| + * CPU clock speed of the platform is in MHz - see kbase_cpu_clk_speed_func |
| + * for the function prototype. |
| + * |
| + * Attached value: A kbase_cpu_clk_speed_func. |
| + * Default Value: NA |
| + */ |
| +#define CPU_SPEED_FUNC (NULL) |
| + |
| +/** |
| + * GPU_SPEED_FUNC - A pointer to a function that calculates the GPU clock |
| + * |
| + * GPU clock speed of the platform in MHz - see kbase_gpu_clk_speed_func |
| + * for the function prototype. |
| + * |
| + * Attached value: A kbase_gpu_clk_speed_func. |
| + * Default Value: NA |
| + */ |
| +#define GPU_SPEED_FUNC (NULL) |
| + |
| +/** |
| + * Power management configuration |
| + * |
| + * Attached value: pointer to @ref kbase_pm_callback_conf |
| + * Default value: See @ref kbase_pm_callback_conf |
| + */ |
| +#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks) |
| + |
| +/** |
| + * Platform specific configuration functions |
| + * |
| + * Attached value: pointer to @ref kbase_platform_funcs_conf |
| + * Default value: See @ref kbase_platform_funcs_conf |
| + */ |
| +#define PLATFORM_FUNCS (&platform_funcs) |
| + |
| +extern struct kbase_pm_callback_conf pm_callbacks; |
| +extern struct kbase_platform_funcs_conf platform_funcs; |
| + |
| +/** |
| + * Autosuspend delay |
| + * |
| + * The delay time (in milliseconds) to be used for autosuspend |
| + */ |
| +#define AUTO_SUSPEND_DELAY (100) |
| diff --git a/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_runtime_pm.c b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_runtime_pm.c |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..d6e617de4fdbd82a4ea1d442c1fbaf2da89f8857 |
| --- /dev/null |
| +++ b/drivers/gpu/arm/valhall/platform/mt8192/mali_kbase_runtime_pm.c |
| @@ -0,0 +1,454 @@ |
| +/* |
| + * Copyright (C) 2018 MediaTek Inc. |
| + * |
| + * This program is free software; you can redistribute it and/or modify |
| + * it under the terms of the GNU General Public License version 2 as |
| + * published by the Free Software Foundation. |
| + * |
| + * This program is distributed in the hope that it will be useful, |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. |
| + */ |
| + |
| +#include <linux/of_address.h> |
| +#include <linux/of_device.h> |
| +#include <linux/pm_domain.h> |
| +#include <linux/pm_runtime.h> |
| +#include <linux/regulator/consumer.h> |
| +#include <mali_kbase.h> |
| +#include "mali_kbase_config_platform.h" |
| +#include <mali_kbase_defs.h> |
| + |
| +static void pm_domain_term(struct kbase_device *kbdev) |
| +{ |
| + int i; |
| + |
| + for (i = 0; i < ARRAY_SIZE(kbdev->pm_domain_devs); i++) { |
| + if (kbdev->pm_domain_devs[i]) |
| + dev_pm_domain_detach(kbdev->pm_domain_devs[i], true); |
| + } |
| +} |
| + |
| +static int pm_domain_init(struct kbase_device *kbdev) |
| +{ |
| + int err; |
| + int i, num_domains, num_domain_names; |
| + const char *pd_names[GPU_CORE_NUM]; |
| + |
| + num_domains = of_count_phandle_with_args(kbdev->dev->of_node, |
| + "power-domains", |
| + "#power-domain-cells"); |
| + |
| + num_domain_names = of_property_count_strings(kbdev->dev->of_node, |
| + "power-domain-names"); |
| + |
| + /* |
| + * Single domain is handled by the core, and, if only a single power |
| + * the power domain is requested, the property is optional. |
| + */ |
| + if (num_domains < 2 && kbdev->num_pm_domains < 2) |
| + return 0; |
| + |
| + if (num_domains != num_domain_names) { |
| + dev_err(kbdev->dev, |
| + "Device tree power domains are not match: PD %d, PD names %d\n", |
| + num_domains, num_domain_names); |
| + return -EINVAL; |
| + } |
| + |
| + if (num_domains != kbdev->num_pm_domains) { |
| + dev_err(kbdev->dev, |
| + "Incorrect number of power domains: %d provided, %d needed\n", |
| + num_domains, kbdev->num_pm_domains); |
| + return -EINVAL; |
| + } |
| + |
| + if (WARN(num_domains > ARRAY_SIZE(kbdev->pm_domain_devs), |
| + "Too many supplies in compatible structure.\n")) |
| + return -EINVAL; |
| + |
| + err = of_property_read_string_array(kbdev->dev->of_node, |
| + "power-domain-names", |
| + pd_names, |
| + num_domain_names); |
| + |
| + if (err < 0) { |
| + dev_err(kbdev->dev, "Error reading supply-names: %d\n", err); |
| + return err; |
| + } |
| + |
| + for (i = 0; i < num_domains; i++) { |
| + kbdev->pm_domain_devs[i] = |
| + dev_pm_domain_attach_by_name(kbdev->dev, |
| + pd_names[i]); |
| + if (IS_ERR_OR_NULL(kbdev->pm_domain_devs[i])) { |
| + err = PTR_ERR(kbdev->pm_domain_devs[i]) ? : -ENODATA; |
| + kbdev->pm_domain_devs[i] = NULL; |
| + if (err == -EPROBE_DEFER) { |
| + dev_err(kbdev->dev, |
| + "Probe deferral for pm-domain %s(%d)\n", |
| + pd_names[i], i); |
| + } else { |
| + dev_err(kbdev->dev, |
| + "failed to get pm-domain %s(%d): %d\n", |
| + pd_names[i], i, err); |
| + } |
| + goto err; |
| + } |
| + } |
| + |
| + return 0; |
| + |
| +err: |
| + pm_domain_term(kbdev); |
| + return err; |
| +} |
| + |
| +static void check_bus_idle(struct kbase_device *kbdev) |
| +{ |
| + struct mfg_base *mfg = kbdev->platform_context; |
| + u32 val; |
| + |
| + /* MFG_QCHANNEL_CON (0x13fb_f0b4) bit [1:0] = 0x1 */ |
| + writel(0x00000001, mfg->g_mfg_base + 0xb4); |
| + |
| + /* set register MFG_DEBUG_SEL (0x13fb_f170) bit [7:0] = 0x03 */ |
| + writel(0x00000003, mfg->g_mfg_base + 0x170); |
| + |
| + /* polling register MFG_DEBUG_TOP (0x13fb_f178) bit 2 = 0x1 */ |
| + /* => 1 for bus idle, 0 for bus non-idle */ |
| + do { |
| + val = readl(mfg->g_mfg_base + 0x178); |
| + } while ((val & 0x4) != 0x4); |
| +} |
| + |
| +static void *get_mfg_base(const char *node_name) |
| +{ |
| + struct device_node *node; |
| + |
| + node = of_find_compatible_node(NULL, NULL, node_name); |
| + |
| + if (node) |
| + return of_iomap(node, 0); |
| + |
| + return NULL; |
| +} |
| + |
| +static int pm_callback_power_on(struct kbase_device *kbdev) |
| +{ |
| + int error, i; |
| + struct mfg_base *mfg = kbdev->platform_context; |
| + |
| + if (mfg->is_powered) { |
| + dev_dbg(kbdev->dev, "mali_device is already powered\n"); |
| + return 0; |
| + } |
| + |
| + for (i = 0; i < kbdev->nr_regulators; i++) { |
| + error = regulator_enable(kbdev->regulators[i]); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "Power on reg %d failed error = %d\n", |
| + i, error); |
| + return error; |
| + } |
| + } |
| + |
| + for(i = 0; i < kbdev->num_pm_domains; i++) { |
| + error = pm_runtime_get_sync(kbdev->pm_domain_devs[i]); |
| + if (error < 0) |
| + dev_err(kbdev->dev, |
| + "Power on core %d failed (err: %d)\n", i+1, error); |
| + } |
| + |
| + error = clk_prepare_enable(mfg->clk_main_parent); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "clk_main_parent clock enable failed (err: %d)\n", |
| + error); |
| + return error; |
| + } |
| + |
| + error = clk_prepare_enable(mfg->clk_sub_parent); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "clk_sub_parent clock enable failed (err: %d)\n", |
| + error); |
| + return error; |
| + } |
| + |
| + error = clk_prepare_enable(mfg->clk_mux); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "clk_mux clock enable failed (err: %d)\n", error); |
| + return error; |
| + } |
| + |
| + error = clk_prepare_enable(mfg->subsys_mfg_cg); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "subsys_mfg_cg clock enable failed (err: %d)\n", error); |
| + return error; |
| + } |
| + |
| + mfg->is_powered = true; |
| + |
| + return 1; |
| +} |
| + |
| +static void pm_callback_power_off(struct kbase_device *kbdev) |
| +{ |
| + struct mfg_base *mfg = kbdev->platform_context; |
| + int error, i; |
| + |
| + if (!mfg->is_powered) { |
| + dev_dbg(kbdev->dev, "mali_device is already powered off\n"); |
| + return; |
| + } |
| + |
| + mfg->is_powered = false; |
| + |
| + check_bus_idle(kbdev); |
| + |
| + clk_disable_unprepare(mfg->subsys_mfg_cg); |
| + |
| + clk_disable_unprepare(mfg->clk_mux); |
| + |
| + clk_disable_unprepare(mfg->clk_sub_parent); |
| + |
| + clk_disable_unprepare(mfg->clk_main_parent); |
| + |
| + for(i = kbdev->num_pm_domains - 1; i >= 0; i--) { |
| + pm_runtime_mark_last_busy(kbdev->pm_domain_devs[i]); |
| + error = pm_runtime_put_autosuspend(kbdev->pm_domain_devs[i]); |
| + if (error < 0) |
| + dev_err(kbdev->dev, |
| + "Power off core %d failed (err: %d)\n", i+1, error); |
| + } |
| + |
| + for (i = kbdev->nr_regulators - 1; i >= 0; i--) { |
| + error = regulator_disable(kbdev->regulators[i]); |
| + if (error < 0) { |
| + dev_err(kbdev->dev, |
| + "Power off reg %d failed error = %d\n", |
| + i, error); |
| + } |
| + } |
| +} |
| + |
| +static int kbase_device_runtime_init(struct kbase_device *kbdev) |
| +{ |
| + dev_dbg(kbdev->dev, "%s\n", __func__); |
| + |
| + return 0; |
| +} |
| + |
| +static void kbase_device_runtime_disable(struct kbase_device *kbdev) |
| +{ |
| + dev_dbg(kbdev->dev, "%s\n", __func__); |
| +} |
| + |
| +static int pm_callback_runtime_on(struct kbase_device *kbdev) |
| +{ |
| + return 0; |
| +} |
| + |
| +static void pm_callback_runtime_off(struct kbase_device *kbdev) |
| +{ |
| +} |
| + |
| +static void pm_callback_resume(struct kbase_device *kbdev) |
| +{ |
| + pm_callback_power_on(kbdev); |
| +} |
| + |
| +static void pm_callback_suspend(struct kbase_device *kbdev) |
| +{ |
| + pm_callback_power_off(kbdev); |
| +} |
| + |
| +struct kbase_pm_callback_conf pm_callbacks = { |
| + .power_on_callback = pm_callback_power_on, |
| + .power_off_callback = pm_callback_power_off, |
| + .power_suspend_callback = pm_callback_suspend, |
| + .power_resume_callback = pm_callback_resume, |
| +#ifdef KBASE_PM_RUNTIME |
| + .power_runtime_init_callback = kbase_device_runtime_init, |
| + .power_runtime_term_callback = kbase_device_runtime_disable, |
| + .power_runtime_on_callback = pm_callback_runtime_on, |
| + .power_runtime_off_callback = pm_callback_runtime_off, |
| +#else /* KBASE_PM_RUNTIME */ |
| + .power_runtime_init_callback = NULL, |
| + .power_runtime_term_callback = NULL, |
| + .power_runtime_on_callback = NULL, |
| + .power_runtime_off_callback = NULL, |
| +#endif /* KBASE_PM_RUNTIME */ |
| +}; |
| + |
| + |
| +int mali_mfgsys_init(struct kbase_device *kbdev, struct mfg_base *mfg) |
| +{ |
| + int err, i; |
| + unsigned long volt; |
| + |
| + kbdev->num_pm_domains = GPU_CORE_NUM; |
| + |
| + err = pm_domain_init(kbdev); |
| + if (err < 0) |
| + return err; |
| + |
| + for (i = 0; i < kbdev->nr_regulators; i++) |
| + if (kbdev->regulators[i] == NULL) |
| + return -EINVAL; |
| + |
| + mfg->clk_main_parent = devm_clk_get(kbdev->dev, "clk_main_parent"); |
| + if (IS_ERR(mfg->clk_main_parent)) { |
| + err = PTR_ERR(mfg->clk_main_parent); |
| + dev_err(kbdev->dev, "devm_clk_get clk_main_parent failed\n"); |
| + return err; |
| + } |
| + |
| + mfg->clk_sub_parent = devm_clk_get(kbdev->dev, "clk_sub_parent"); |
| + if (IS_ERR(mfg->clk_sub_parent)) { |
| + err = PTR_ERR(mfg->clk_sub_parent); |
| + dev_err(kbdev->dev, "devm_clk_get clk_sub_parent failed\n"); |
| + return err; |
| + } |
| + |
| + mfg->clk_mux = devm_clk_get(kbdev->dev, "clk_mux"); |
| + if (IS_ERR(mfg->clk_mux)) { |
| + err = PTR_ERR(mfg->clk_mux); |
| + dev_err(kbdev->dev, "devm_clk_get clk_mux failed\n"); |
| + return err; |
| + } |
| + |
| + mfg->subsys_mfg_cg = devm_clk_get(kbdev->dev, "subsys_mfg_cg"); |
| + if (IS_ERR(mfg->subsys_mfg_cg)) { |
| + err = PTR_ERR(mfg->subsys_mfg_cg); |
| + dev_err(kbdev->dev, "devm_clk_get subsys_mfg_cg failed\n"); |
| + return err; |
| + } |
| + |
| + for (i = 0; i < kbdev->nr_regulators; i++) { |
| + volt = (0 == i) ? VGPU_MAX_VOLT : VSRAM_GPU_MAX_VOLT; |
| + err = regulator_set_voltage(kbdev->regulators[i], |
| + volt, volt + VOLT_TOL); |
| + if (err < 0) { |
| + dev_err(kbdev->dev, |
| + "Regulator %d set voltage failed: %d\n", |
| + i, err); |
| + return err; |
| + } |
| + kbdev->current_voltages[i] = volt; |
| + } |
| + |
| + mfg->g_mfg_base = get_mfg_base("mediatek,mt8192-mfgcfg"); |
| + if (!mfg->g_mfg_base) { |
| + dev_err(kbdev->dev, "Cannot find mfgcfg node\n"); |
| + return -ENODEV; |
| + } |
| + |
| + mfg->is_powered = false; |
| + |
| + return 0; |
| +} |
| + |
| +static void voltage_range_check(struct kbase_device *kbdev, |
| + unsigned long *voltages) |
| +{ |
| + if (voltages[1] - voltages[0] < MIN_VOLT_BIAS || |
| + voltages[1] - voltages[0] > MAX_VOLT_BIAS) |
| + voltages[1] = voltages[0] + MIN_VOLT_BIAS; |
| + voltages[1] = clamp_t(unsigned long, voltages[1], VSRAM_GPU_MIN_VOLT, |
| + VSRAM_GPU_MAX_VOLT); |
| +} |
| + |
| +static int set_frequency(struct kbase_device *kbdev, unsigned long freq) |
| +{ |
| + int err; |
| + struct mfg_base *mfg = kbdev->platform_context; |
| + |
| + if (kbdev->current_freqs[0] != freq) { |
| + err = clk_set_parent(mfg->clk_mux, mfg->clk_sub_parent); |
| + if (err) { |
| + dev_err(kbdev->dev, "Failed to select sub clock src\n"); |
| + return err; |
| + } |
| + |
| + err = clk_set_rate(mfg->clk_main_parent, freq); |
| + if (err) |
| + return err; |
| + |
| + err = clk_set_parent(mfg->clk_mux, mfg->clk_main_parent); |
| + if (err) { |
| + dev_err(kbdev->dev, |
| + "Failed to select main clock src\n"); |
| + return err; |
| + } |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int platform_init(struct kbase_device *kbdev) |
| +{ |
| + int err,i; |
| + struct mfg_base *mfg; |
| + |
| + mfg = kzalloc(sizeof(*mfg), GFP_KERNEL); |
| + if (!mfg) |
| + return -ENOMEM; |
| + |
| + err = mali_mfgsys_init(kbdev, mfg); |
| + if (err) |
| + goto platform_init_err; |
| + |
| + kbdev->platform_context = mfg; |
| + for(i = 0; i < kbdev->num_pm_domains; i++) { |
| + pm_runtime_set_autosuspend_delay(kbdev->pm_domain_devs[i], 50); |
| + pm_runtime_use_autosuspend(kbdev->pm_domain_devs[i]); |
| + } |
| + |
| + err = clk_set_parent(mfg->clk_mux, mfg->clk_sub_parent); |
| + if (err) { |
| + dev_err(kbdev->dev, "Failed to select sub clock src\n"); |
| + goto platform_init_err; |
| + } |
| + |
| + err = clk_set_rate(mfg->clk_main_parent, GPU_FREQ_KHZ_MAX * 1000); |
| + if (err) { |
| + dev_err(kbdev->dev, "Failed to set clock %d kHz\n", |
| + GPU_FREQ_KHZ_MAX); |
| + goto platform_init_err; |
| + } |
| + |
| + err = clk_set_parent(mfg->clk_mux, mfg->clk_main_parent); |
| + if (err) { |
| + dev_err(kbdev->dev, "Failed to select main clock src\n"); |
| + goto platform_init_err; |
| + } |
| + |
| + kbdev->devfreq_ops.set_frequency = set_frequency; |
| + kbdev->devfreq_ops.voltage_range_check = voltage_range_check; |
| + |
| + return 0; |
| + |
| +platform_init_err: |
| + kfree(mfg); |
| + return err; |
| +} |
| + |
| +static void platform_term(struct kbase_device *kbdev) |
| +{ |
| + struct mfg_base *mfg = kbdev->platform_context; |
| + |
| + kfree(mfg); |
| + kbdev->platform_context = NULL; |
| + pm_domain_term(kbdev); |
| +} |
| + |
| +struct kbase_platform_funcs_conf platform_funcs = { |
| + .platform_init_func = platform_init, |
| + .platform_term_func = platform_term |
| +}; |
| diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c |
| index 3ae9c810845bbfebb49f36a232fc7eaec5f8dc63..83b075a0d3a57b434b39893cb1eacbcca800addb 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c |
| @@ -17,6 +17,8 @@ |
| #define DISP_COLOR_CFG_MAIN 0x0400 |
| #define DISP_COLOR_START_MT2701 0x0f00 |
| #define DISP_COLOR_START_MT8173 0x0c00 |
| +#define DISP_COLOR_SHADOW_CTRL 0x0cb0 |
| +#define COLOR_BYPASS_SHADOW BIT(0) |
| #define DISP_COLOR_START(comp) ((comp)->data->color_offset) |
| #define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50) |
| #define DISP_COLOR_HEIGHT(comp) (DISP_COLOR_START(comp) + 0x54) |
| @@ -26,6 +28,7 @@ |
| |
| struct mtk_disp_color_data { |
| unsigned int color_offset; |
| + bool has_shadow; |
| }; |
| |
| /** |
| @@ -63,9 +66,21 @@ static void mtk_color_start(struct mtk_ddp_comp *comp) |
| writel(0x1, comp->regs + DISP_COLOR_START(color)); |
| } |
| |
| +static void mtk_color_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + struct mtk_disp_color *color = comp_to_color(comp); |
| + |
| + if (color->data->has_shadow) { |
| + mtk_ddp_write_mask(NULL, COLOR_BYPASS_SHADOW, comp, |
| + DISP_COLOR_SHADOW_CTRL, |
| + COLOR_BYPASS_SHADOW); |
| + } |
| +} |
| + |
| static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = { |
| .config = mtk_color_config, |
| .start = mtk_color_start, |
| + .bypass_shadow = mtk_color_bypass_shadow, |
| }; |
| |
| static int mtk_disp_color_bind(struct device *dev, struct device *master, |
| @@ -152,11 +167,18 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = { |
| .color_offset = DISP_COLOR_START_MT8173, |
| }; |
| |
| +static const struct mtk_disp_color_data mt8192_color_driver_data = { |
| + .color_offset = DISP_COLOR_START_MT8173, |
| + .has_shadow = true, |
| +}; |
| + |
| static const struct of_device_id mtk_disp_color_driver_dt_match[] = { |
| { .compatible = "mediatek,mt2701-disp-color", |
| .data = &mt2701_color_driver_data}, |
| { .compatible = "mediatek,mt8173-disp-color", |
| .data = &mt8173_color_driver_data}, |
| + { .compatible = "mediatek,mt8192-disp-color", |
| + .data = &mt8192_color_driver_data}, |
| {}, |
| }; |
| MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
| index 0f445d5ca5492c6bba406112b14ee09b58b0d2c8..2be19d3e949ac9d4cc789d8be145b7062570429b 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
| @@ -3,6 +3,8 @@ |
| * Copyright (c) 2015 MediaTek Inc. |
| */ |
| |
| +#include <drm/drmP.h> |
| + |
| #include <drm/drm_fourcc.h> |
| |
| #include <linux/clk.h> |
| @@ -11,6 +13,7 @@ |
| #include <linux/of_device.h> |
| #include <linux/of_irq.h> |
| #include <linux/platform_device.h> |
| +#include <linux/pm_runtime.h> |
| #include <linux/soc/mediatek/mtk-cmdq.h> |
| |
| #include "mtk_drm_crtc.h" |
| @@ -19,6 +22,9 @@ |
| #define DISP_REG_OVL_INTEN 0x0004 |
| #define OVL_FME_CPL_INT BIT(1) |
| #define DISP_REG_OVL_INTSTA 0x0008 |
| +#define OVL_EN BIT(0) |
| +#define OVL_READ_WORK_REG BIT(20) |
| +#define OVL_BYPASS_SHADOW BIT(22) |
| #define DISP_REG_OVL_EN 0x000c |
| #define DISP_REG_OVL_RST 0x0014 |
| #define DISP_REG_OVL_ROI_SIZE 0x0020 |
| @@ -61,6 +67,7 @@ struct mtk_disp_ovl_data { |
| unsigned int gmc_bits; |
| unsigned int layer_nr; |
| bool fmt_rgb565_is_0; |
| + bool has_shadow; |
| }; |
| |
| /** |
| @@ -115,12 +122,23 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) |
| |
| static void mtk_ovl_start(struct mtk_ddp_comp *comp) |
| { |
| - writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); |
| + mtk_ddp_write_mask(NULL, OVL_EN, comp, DISP_REG_OVL_EN, OVL_EN); |
| } |
| |
| static void mtk_ovl_stop(struct mtk_ddp_comp *comp) |
| { |
| - writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); |
| + mtk_ddp_write_mask(NULL, 0, comp, DISP_REG_OVL_EN, OVL_EN); |
| +} |
| + |
| +static void mtk_ovl_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); |
| + |
| + if (ovl->data->has_shadow) { |
| + mtk_ddp_write_mask(NULL, OVL_BYPASS_SHADOW, comp, |
| + DISP_REG_OVL_EN, |
| + OVL_BYPASS_SHADOW); |
| + } |
| } |
| |
| static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, |
| @@ -132,6 +150,11 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, |
| DISP_REG_OVL_ROI_SIZE); |
| mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR); |
| |
| + DRM_DEBUG_DRIVER("cmdq_pkt %px 0x%X %d comp_id %d reg %px bgclr 0x%X\n", |
| + cmdq_pkt, cmdq_pkt, cmdq_pkt?1:0, |
| + comp->id, comp->regs, |
| + readl(comp->regs + DISP_REG_OVL_ROI_BGCLR)); |
| + |
| mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST); |
| mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST); |
| } |
| @@ -260,11 +283,13 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, |
| unsigned int src_size = (pending->height << 16) | pending->width; |
| unsigned int con; |
| |
| - if (!pending->enable) |
| + if (!pending->enable) { |
| mtk_ovl_layer_off(comp, idx, cmdq_pkt); |
| + return; |
| + } |
| |
| con = ovl_fmt_convert(ovl, fmt); |
| - if (idx != 0) |
| + if (state->base.fb->format->has_alpha) |
| con |= OVL_CON_AEN | OVL_CON_ALPHA; |
| |
| if (pending->rotation & DRM_MODE_REFLECT_Y) { |
| @@ -288,8 +313,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, |
| mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, |
| DISP_REG_OVL_ADDR(ovl, idx)); |
| |
| - if (pending->enable) |
| - mtk_ovl_layer_on(comp, idx, cmdq_pkt); |
| + mtk_ovl_layer_on(comp, idx, cmdq_pkt); |
| } |
| |
| static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) |
| @@ -314,6 +338,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { |
| .config = mtk_ovl_config, |
| .start = mtk_ovl_start, |
| .stop = mtk_ovl_stop, |
| + .bypass_shadow = mtk_ovl_bypass_shadow, |
| .enable_vblank = mtk_ovl_enable_vblank, |
| .disable_vblank = mtk_ovl_disable_vblank, |
| .supported_rotations = mtk_ovl_supported_rotations, |
| @@ -401,6 +426,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) |
| return ret; |
| } |
| |
| + pm_runtime_enable(dev); |
| + |
| ret = component_add(dev, &mtk_disp_ovl_component_ops); |
| if (ret) |
| dev_err(dev, "Failed to add component: %d\n", ret); |
| @@ -412,6 +439,8 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) |
| { |
| component_del(&pdev->dev, &mtk_disp_ovl_component_ops); |
| |
| + pm_runtime_disable(&pdev->dev); |
| + |
| return 0; |
| } |
| |
| @@ -429,11 +458,49 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { |
| .fmt_rgb565_is_0 = true, |
| }; |
| |
| +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { |
| + .addr = DISP_REG_OVL_ADDR_MT8173, |
| + .gmc_bits = 10, |
| + .layer_nr = 4, |
| + .fmt_rgb565_is_0 = true, |
| +}; |
| + |
| +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { |
| + .addr = DISP_REG_OVL_ADDR_MT8173, |
| + .gmc_bits = 10, |
| + .layer_nr = 2, |
| + .fmt_rgb565_is_0 = true, |
| +}; |
| + |
| +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { |
| + .addr = DISP_REG_OVL_ADDR_MT8173, |
| + .gmc_bits = 10, |
| + .layer_nr = 4, |
| + .fmt_rgb565_is_0 = true, |
| + .has_shadow = true, |
| +}; |
| + |
| +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { |
| + .addr = DISP_REG_OVL_ADDR_MT8173, |
| + .gmc_bits = 10, |
| + .layer_nr = 2, |
| + .fmt_rgb565_is_0 = true, |
| + .has_shadow = true, |
| +}; |
| + |
| static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { |
| { .compatible = "mediatek,mt2701-disp-ovl", |
| .data = &mt2701_ovl_driver_data}, |
| { .compatible = "mediatek,mt8173-disp-ovl", |
| .data = &mt8173_ovl_driver_data}, |
| + { .compatible = "mediatek,mt8183-disp-ovl", |
| + .data = &mt8183_ovl_driver_data}, |
| + { .compatible = "mediatek,mt8183-disp-ovl-2l", |
| + .data = &mt8183_ovl_2l_driver_data}, |
| + { .compatible = "mediatek,mt8192-disp-ovl", |
| + .data = &mt8192_ovl_driver_data}, |
| + { .compatible = "mediatek,mt8192-disp-ovl-2l", |
| + .data = &mt8192_ovl_2l_driver_data}, |
| {}, |
| }; |
| MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c |
| index e04319fedf463e47ae3c54677471ec3c6c8aa5ad..efd84285eaa4bb057c29db3f510064878f9b82d2 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c |
| @@ -9,6 +9,7 @@ |
| #include <linux/of_device.h> |
| #include <linux/of_irq.h> |
| #include <linux/platform_device.h> |
| +#include <linux/pm_runtime.h> |
| #include <linux/soc/mediatek/mtk-cmdq.h> |
| |
| #include "mtk_drm_crtc.h" |
| @@ -46,12 +47,16 @@ |
| #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) |
| #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) |
| #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) |
| +#define DISP_REG_RDMA_SHADOW_UPDATE 0x00bc |
| +#define DISP_RDMA_BYPASS_SHADOW BIT(1) |
| +#define DISP_RDMA_READ_WORK_REG BIT(2) |
| #define DISP_RDMA_MEM_START_ADDR 0x0f00 |
| |
| #define RDMA_MEM_GMC 0x40402020 |
| |
| struct mtk_disp_rdma_data { |
| unsigned int fifo_size; |
| + bool has_shadow; |
| }; |
| |
| /** |
| @@ -63,6 +68,7 @@ struct mtk_disp_rdma { |
| struct mtk_ddp_comp ddp_comp; |
| struct drm_crtc *crtc; |
| const struct mtk_disp_rdma_data *data; |
| + u32 fifo_size; |
| }; |
| |
| static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) |
| @@ -124,6 +130,21 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp) |
| rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); |
| } |
| |
| +static void mtk_rdma_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + struct mtk_disp_rdma *rdma = comp_to_rdma(comp); |
| + |
| + if (rdma->data->has_shadow) { |
| + pr_err("disable rdma shadow\n"); |
| + mtk_ddp_write_mask(NULL, DISP_RDMA_BYPASS_SHADOW, comp, |
| + DISP_REG_RDMA_SHADOW_UPDATE, |
| + DISP_RDMA_BYPASS_SHADOW); |
| + mtk_ddp_write_mask(NULL, DISP_RDMA_READ_WORK_REG, comp, |
| + DISP_REG_RDMA_SHADOW_UPDATE, |
| + DISP_RDMA_READ_WORK_REG); |
| + } |
| +} |
| + |
| static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, |
| unsigned int height, unsigned int vrefresh, |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| @@ -131,12 +152,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, |
| unsigned int threshold; |
| unsigned int reg; |
| struct mtk_disp_rdma *rdma = comp_to_rdma(comp); |
| + u32 rdma_fifo_size; |
| |
| mtk_ddp_write_mask(cmdq_pkt, width, comp, |
| DISP_REG_RDMA_SIZE_CON_0, 0xfff); |
| mtk_ddp_write_mask(cmdq_pkt, height, comp, |
| DISP_REG_RDMA_SIZE_CON_1, 0xfffff); |
| |
| + if (rdma->fifo_size) |
| + rdma_fifo_size = rdma->fifo_size; |
| + else |
| + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); |
| + |
| /* |
| * Enable FIFO underflow since DSI and DPI can't be blocked. |
| * Keep the FIFO pseudo size reset default of 8 KiB. Set the |
| @@ -144,8 +171,11 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, |
| * account for blanking, and with a pixel depth of 4 bytes: |
| */ |
| threshold = width * height * vrefresh * 4 * 7 / 1000000; |
| + if (threshold > rdma_fifo_size) |
| + threshold = rdma_fifo_size; |
| + |
| reg = RDMA_FIFO_UNDERFLOW_EN | |
| - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | |
| + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | |
| RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); |
| mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); |
| } |
| @@ -231,6 +261,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { |
| .config = mtk_rdma_config, |
| .start = mtk_rdma_start, |
| .stop = mtk_rdma_stop, |
| + .bypass_shadow = mtk_rdma_bypass_shadow, |
| .enable_vblank = mtk_rdma_enable_vblank, |
| .disable_vblank = mtk_rdma_disable_vblank, |
| .layer_nr = mtk_rdma_layer_nr, |
| @@ -291,6 +322,18 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) |
| return comp_id; |
| } |
| |
| + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { |
| + ret = of_property_read_u32(dev->of_node, |
| + "mediatek,rdma_fifo_size", |
| + &priv->fifo_size); |
| + if (ret) { |
| + dev_err(dev, "Failed to get rdma fifo size\n"); |
| + return ret; |
| + } |
| + |
| + priv->fifo_size *= SZ_1K; |
| + } |
| + |
| ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, |
| &mtk_disp_rdma_funcs); |
| if (ret) { |
| @@ -316,6 +359,8 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) |
| |
| platform_set_drvdata(pdev, priv); |
| |
| + pm_runtime_enable(dev); |
| + |
| ret = component_add(dev, &mtk_disp_rdma_component_ops); |
| if (ret) |
| dev_err(dev, "Failed to add component: %d\n", ret); |
| @@ -327,6 +372,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) |
| { |
| component_del(&pdev->dev, &mtk_disp_rdma_component_ops); |
| |
| + pm_runtime_disable(&pdev->dev); |
| + |
| return 0; |
| } |
| |
| @@ -338,11 +385,24 @@ static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { |
| .fifo_size = SZ_8K, |
| }; |
| |
| +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { |
| + .fifo_size = 5 * SZ_1K, |
| +}; |
| + |
| +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { |
| + .fifo_size = 5 * SZ_1K, |
| + .has_shadow = true, |
| +}; |
| + |
| static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { |
| { .compatible = "mediatek,mt2701-disp-rdma", |
| .data = &mt2701_rdma_driver_data}, |
| { .compatible = "mediatek,mt8173-disp-rdma", |
| .data = &mt8173_rdma_driver_data}, |
| + { .compatible = "mediatek,mt8183-disp-rdma", |
| + .data = &mt8183_rdma_driver_data}, |
| + { .compatible = "mediatek,mt8192-disp-rdma", |
| + .data = &mt8192_rdma_driver_data}, |
| {}, |
| }; |
| MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c |
| index feedbac027d99e23e426f2095ffe5f19440e0507..af4505be0a9f072763d8e5ad300dd2dde794c553 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c |
| @@ -287,6 +287,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) |
| return ret; |
| } |
| |
| + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) |
| + mtk_ddp_comp_prepare(mtk_crtc->ddp_comp[i]); |
| + |
| ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); |
| if (ret < 0) { |
| DRM_ERROR("Failed to enable mutex clock: %d\n", ret); |
| @@ -299,6 +302,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) |
| goto err_mutex_unprepare; |
| } |
| |
| + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) |
| + mtk_ddp_comp_bypass_shadow(mtk_crtc->ddp_comp[i]); |
| + |
| DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); |
| for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { |
| mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, |
| @@ -355,7 +361,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) |
| if (i == 1) |
| mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); |
| } |
| - |
| for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) |
| mtk_disp_mutex_remove_comp(mtk_crtc->mutex, |
| mtk_crtc->ddp_comp[i]->id); |
| @@ -371,6 +376,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) |
| mtk_crtc_ddp_clk_disable(mtk_crtc); |
| mtk_disp_mutex_unprepare(mtk_crtc->mutex); |
| |
| + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) |
| + mtk_ddp_comp_unprepare(mtk_crtc->ddp_comp[i]); |
| + |
| pm_runtime_put(drm->dev); |
| |
| if (crtc->state->event && !crtc->state->active) { |
| @@ -533,15 +541,14 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, |
| |
| DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); |
| |
| - ret = mtk_smi_larb_get(comp->larb_dev); |
| - if (ret) { |
| - DRM_ERROR("Failed to get larb: %d\n", ret); |
| - return; |
| - } |
| + ret = pm_runtime_get_sync(comp->dev); |
| + if (ret < 0) |
| + DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", |
| + ret); |
| |
| ret = mtk_crtc_ddp_hw_init(mtk_crtc); |
| if (ret) { |
| - mtk_smi_larb_put(comp->larb_dev); |
| + pm_runtime_put(comp->dev); |
| return; |
| } |
| |
| @@ -554,7 +561,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, |
| { |
| struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); |
| struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; |
| - int i; |
| + int i, ret; |
| |
| DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); |
| if (!mtk_crtc->enabled) |
| @@ -577,9 +584,13 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, |
| |
| drm_crtc_vblank_off(crtc); |
| mtk_crtc_ddp_hw_fini(mtk_crtc); |
| - mtk_smi_larb_put(comp->larb_dev); |
| |
| mtk_crtc->enabled = false; |
| + |
| + ret = pm_runtime_put(comp->dev); |
| + if (ret < 0) |
| + DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", |
| + ret); |
| } |
| |
| static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, |
| @@ -591,12 +602,15 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, |
| if (mtk_crtc->event && state->base.event) |
| DRM_ERROR("new event while there is still a pending event\n"); |
| |
| + spin_lock_irq(&crtc->dev->event_lock); |
| if (state->base.event) { |
| state->base.event->pipe = drm_crtc_index(crtc); |
| WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
| + WARN_ON(mtk_crtc->event); |
| mtk_crtc->event = state->base.event; |
| state->base.event = NULL; |
| } |
| + spin_unlock_irq(&crtc->dev->event_lock); |
| } |
| |
| static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c |
| index 014c1bbe1df2ce82512032341f96296fd02293f4..0ce644cff4447624d93983e593264b8f8ffd79b9 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c |
| @@ -13,8 +13,32 @@ |
| #include "mtk_drm_ddp.h" |
| #include "mtk_drm_ddp_comp.h" |
| |
| +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 |
| +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 |
| +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 |
| +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c |
| +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 |
| +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 |
| +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 |
| +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 |
| +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 |
| +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac |
| +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 |
| +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 |
| +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 |
| +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 |
| + |
| +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 |
| +#define DISP_REG_CONFIG_OUT_SEL 0x04c |
| +#define DISP_REG_CONFIG_DSI_SEL 0x050 |
| +#define DISP_REG_CONFIG_DPI_SEL 0x064 |
| + |
| + |
| + |
| #define MT2701_DISP_MUTEX0_MOD0 0x2c |
| #define MT2701_DISP_MUTEX0_SOF0 0x30 |
| +#define MT8183_DISP_MUTEX0_MOD0 0x30 |
| +#define MT8183_DISP_MUTEX0_SOF0 0x2c |
| |
| #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) |
| #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) |
| @@ -25,6 +49,30 @@ |
| |
| #define INT_MUTEX BIT(1) |
| |
| +#define MT8192_MUTEX_MOD_DISP_OVL0 0 |
| +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 |
| +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 |
| +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 |
| +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 |
| +#define MT8192_MUTEX_MOD_DISP_AAL0 6 |
| +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 |
| +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 |
| +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 |
| +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 |
| +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 |
| + |
| +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 |
| +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 |
| +#define MT8183_MUTEX_MOD_DISP_OVL0 9 |
| +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 |
| +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 |
| +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 |
| +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 |
| +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 |
| +#define MT8183_MUTEX_MOD_DISP_AAL0 15 |
| +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 |
| +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 |
| + |
| #define MT8173_MUTEX_MOD_DISP_OVL0 11 |
| #define MT8173_MUTEX_MOD_DISP_OVL1 12 |
| #define MT8173_MUTEX_MOD_DISP_RDMA0 13 |
| @@ -74,6 +122,9 @@ |
| #define MUTEX_SOF_DSI2 5 |
| #define MUTEX_SOF_DSI3 6 |
| |
| +#define MT8183_MUTEX_SOF_DPI0 2 |
| +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) |
| +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) |
| |
| struct mtk_disp_mutex { |
| int id; |
| @@ -100,7 +151,7 @@ struct mtk_ddp_data { |
| |
| struct mtk_ddp { |
| struct device *dev; |
| - struct clk *clk; |
| + struct clk *clk[3]; |
| void __iomem *regs; |
| struct mtk_disp_mutex mutex[10]; |
| const struct mtk_ddp_data *data; |
| @@ -153,6 +204,34 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
| [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, |
| }; |
| |
| +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
| + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, |
| + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, |
| + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, |
| + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, |
| + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, |
| + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, |
| + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, |
| + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, |
| + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, |
| + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, |
| + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, |
| +}; |
| + |
| +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
| + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, |
| + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, |
| + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, |
| + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, |
| + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, |
| + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, |
| + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, |
| + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, |
| + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, |
| + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, |
| + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, |
| +}; |
| + |
| static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { |
| [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
| [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, |
| @@ -163,6 +242,12 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { |
| [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, |
| }; |
| |
| +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { |
| + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
| + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, |
| + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, |
| +}; |
| + |
| static const struct mtk_ddp_data mt2701_ddp_driver_data = { |
| .mutex_mod = mt2701_mutex_mod, |
| .mutex_sof = mt2712_mutex_sof, |
| @@ -184,6 +269,20 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = { |
| .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, |
| }; |
| |
| +static const struct mtk_ddp_data mt8183_ddp_driver_data = { |
| + .mutex_mod = mt8183_mutex_mod, |
| + .mutex_sof = mt8183_mutex_sof, |
| + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, |
| + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, |
| +}; |
| + |
| +static const struct mtk_ddp_data mt8192_ddp_driver_data = { |
| + .mutex_mod = mt8192_mutex_mod, |
| + .mutex_sof = mt8183_mutex_sof, |
| + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, |
| + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, |
| +}; |
| + |
| struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) |
| { |
| struct mtk_ddp *ddp = dev_get_drvdata(dev); |
| @@ -212,14 +311,41 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) |
| { |
| struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, |
| mutex[mutex->id]); |
| - return clk_prepare_enable(ddp->clk); |
| + int ret; |
| + int i; |
| + |
| + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { |
| + if (IS_ERR(ddp->clk[i])) |
| + continue; |
| + ret = clk_prepare_enable(ddp->clk[i]); |
| + if (ret) { |
| + pr_err("failed to enable clock, err %d. i:%d\n", |
| + ret, i); |
| + goto err; |
| + } |
| + } |
| + |
| + return 0; |
| + |
| +err: |
| + while (--i >= 0) |
| + clk_disable_unprepare(ddp->clk[i]); |
| + return ret; |
| + |
| } |
| |
| void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) |
| { |
| struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, |
| mutex[mutex->id]); |
| - clk_disable_unprepare(ddp->clk); |
| + int i; |
| + |
| + |
| + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { |
| + if (IS_ERR(ddp->clk[i])) |
| + continue; |
| + clk_disable_unprepare(ddp->clk[i]); |
| + } |
| } |
| |
| void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, |
| @@ -370,12 +496,21 @@ static int mtk_ddp_probe(struct platform_device *pdev) |
| ddp->data = of_device_get_match_data(dev); |
| |
| if (!ddp->data->no_clk) { |
| - ddp->clk = devm_clk_get(dev, NULL); |
| - if (IS_ERR(ddp->clk)) { |
| - if (PTR_ERR(ddp->clk) != -EPROBE_DEFER) |
| - dev_err(dev, "Failed to get clock\n"); |
| - return PTR_ERR(ddp->clk); |
| + int ret; |
| + |
| + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { |
| + ddp->clk[i] = of_clk_get(dev->of_node, i); |
| + |
| + if (IS_ERR(ddp->clk[i])) { |
| + ret = PTR_ERR(ddp->clk[i]); |
| + if (ret != EPROBE_DEFER) |
| + dev_err(dev, "Failed to get clock %d\n", |
| + ret); |
| + |
| + return ret; |
| + } |
| } |
| + |
| } |
| |
| regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -402,6 +537,10 @@ static const struct of_device_id ddp_driver_dt_match[] = { |
| .data = &mt2712_ddp_driver_data}, |
| { .compatible = "mediatek,mt8173-disp-mutex", |
| .data = &mt8173_ddp_driver_data}, |
| + { .compatible = "mediatek,mt8183-disp-mutex", |
| + .data = &mt8183_ddp_driver_data}, |
| + { .compatible = "mediatek,mt8192-disp-mutex", |
| + .data = &mt8192_ddp_driver_data}, |
| {}, |
| }; |
| MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
| index 57c88de9a3293447e70965c6628258f7c9f31e05..74e2394965858d07719f828fc2c31ff0fac5b63b 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
| @@ -23,6 +23,9 @@ |
| #define DISP_OD_INTSTA 0x000c |
| #define DISP_OD_CFG 0x0020 |
| #define DISP_OD_SIZE 0x0030 |
| + |
| +#define DITHER_REG(idx) (0x100 + (idx) * 4) |
| +#define DITHER_BYPASS_SHADOW BIT(0) |
| #define DISP_DITHER_5 0x0114 |
| #define DISP_DITHER_7 0x011c |
| #define DISP_DITHER_15 0x013c |
| @@ -31,7 +34,13 @@ |
| #define DISP_REG_UFO_START 0x0000 |
| |
| #define DISP_AAL_EN 0x0000 |
| +#define DISP_AAL_CFG 0x0020 |
| +#define AAL_RELAY_MODE BIT(0) |
| +#define AAL_ENGINE_EN BIT(1) |
| #define DISP_AAL_SIZE 0x0030 |
| +#define DISP_AAL_SHADOW_CTRL 0x00f0 |
| +#define AAL_BYPASS_SHADOW BIT(0) |
| +#define DISP_AAL_OUTPUT_SIZE 0x04d8 |
| |
| #define DISP_CCORR_EN 0x0000 |
| #define CCORR_EN BIT(0) |
| @@ -46,6 +55,8 @@ |
| #define DISP_CCORR_COEF_2 0x0088 |
| #define DISP_CCORR_COEF_3 0x008C |
| #define DISP_CCORR_COEF_4 0x0090 |
| +#define DISP_CCORR_SHADOW 0x00A0 |
| +#define CCORR_BYPASS_SHADOW BIT(2) |
| |
| #define DISP_DITHER_EN 0x0000 |
| #define DITHER_EN BIT(0) |
| @@ -58,6 +69,10 @@ |
| #define DISP_GAMMA_SIZE 0x0030 |
| #define DISP_GAMMA_LUT 0x0700 |
| |
| +#define DISP_POSTMASK_EN 0x0000 |
| +#define DISP_POSTMASK_CFG 0x0020 |
| +#define DISP_POSTMASK_SIZE 0x0030 |
| + |
| #define LUT_10BIT_MASK 0x03ff |
| |
| #define OD_RELAYMODE BIT(0) |
| @@ -178,7 +193,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, |
| unsigned int h, unsigned int vrefresh, |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| { |
| - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE); |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE); |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE); |
| + |
| + mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG, |
| + AAL_RELAY_MODE | AAL_ENGINE_EN); |
| } |
| |
| static void mtk_aal_start(struct mtk_ddp_comp *comp) |
| @@ -191,11 +210,18 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp) |
| writel_relaxed(0x0, comp->regs + DISP_AAL_EN); |
| } |
| |
| +static void mtk_aal_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + mtk_ddp_write_mask(NULL, AAL_BYPASS_SHADOW, comp, |
| + DISP_AAL_SHADOW_CTRL, |
| + AAL_BYPASS_SHADOW); |
| +} |
| + |
| static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, |
| unsigned int h, unsigned int vrefresh, |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| { |
| - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE); |
| mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); |
| } |
| |
| @@ -260,11 +286,18 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, |
| comp, DISP_CCORR_COEF_4); |
| } |
| |
| +static void mtk_ccorr_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + mtk_ddp_write_mask(NULL, CCORR_BYPASS_SHADOW, comp, |
| + DISP_CCORR_SHADOW, |
| + CCORR_BYPASS_SHADOW); |
| +} |
| + |
| static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, |
| unsigned int h, unsigned int vrefresh, |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| { |
| - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE); |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_DITHER_SIZE); |
| mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG); |
| } |
| |
| @@ -278,11 +311,18 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp) |
| writel_relaxed(0x0, comp->regs + DISP_DITHER_EN); |
| } |
| |
| +static void mtk_dither_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + mtk_ddp_write_mask(NULL, DITHER_BYPASS_SHADOW, comp, |
| + DITHER_REG(0), |
| + DITHER_BYPASS_SHADOW); |
| +} |
| + |
| static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, |
| unsigned int h, unsigned int vrefresh, |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| { |
| - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE); |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE); |
| mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); |
| } |
| |
| @@ -319,11 +359,30 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, |
| } |
| } |
| |
| +static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w, |
| + unsigned int h, unsigned int vrefresh, |
| + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
| +{ |
| + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE); |
| + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_POSTMASK_CFG); |
| +} |
| + |
| +static void mtk_postmask_start(struct mtk_ddp_comp *comp) |
| +{ |
| + writel(DITHER_EN, comp->regs + DISP_POSTMASK_EN); |
| +} |
| + |
| +static void mtk_postmask_stop(struct mtk_ddp_comp *comp) |
| +{ |
| + writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN); |
| +} |
| + |
| static const struct mtk_ddp_comp_funcs ddp_aal = { |
| .gamma_set = mtk_gamma_set, |
| .config = mtk_aal_config, |
| .start = mtk_aal_start, |
| .stop = mtk_aal_stop, |
| + .bypass_shadow = mtk_aal_bypass_shadow, |
| }; |
| |
| static const struct mtk_ddp_comp_funcs ddp_ccorr = { |
| @@ -331,12 +390,14 @@ static const struct mtk_ddp_comp_funcs ddp_ccorr = { |
| .start = mtk_ccorr_start, |
| .stop = mtk_ccorr_stop, |
| .ctm_set = mtk_ccorr_ctm_set, |
| + .bypass_shadow = mtk_ccorr_bypass_shadow |
| }; |
| |
| static const struct mtk_ddp_comp_funcs ddp_dither = { |
| .config = mtk_dither_config, |
| .start = mtk_dither_start, |
| .stop = mtk_dither_stop, |
| + .bypass_shadow = mtk_dither_bypass_shadow, |
| }; |
| |
| static const struct mtk_ddp_comp_funcs ddp_gamma = { |
| @@ -346,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = { |
| .stop = mtk_gamma_stop, |
| }; |
| |
| +static const struct mtk_ddp_comp_funcs ddp_postmask = { |
| + .config = mtk_postmask_config, |
| + .start = mtk_postmask_start, |
| + .stop = mtk_postmask_stop, |
| +}; |
| + |
| static const struct mtk_ddp_comp_funcs ddp_od = { |
| .config = mtk_od_config, |
| .start = mtk_od_start, |
| @@ -372,6 +439,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { |
| [MTK_DISP_MUTEX] = "mutex", |
| [MTK_DISP_OD] = "od", |
| [MTK_DISP_BLS] = "bls", |
| + [MTK_DISP_POSTMASK] = "postmask", |
| }; |
| |
| struct mtk_ddp_comp_match { |
| @@ -401,12 +469,16 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { |
| [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, |
| [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL }, |
| [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL }, |
| + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL }, |
| + [DDP_COMPONENT_POSTMASK0] |
| + = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, |
| [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, |
| [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, |
| [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, |
| [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, |
| [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, |
| [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, |
| + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL }, |
| [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, |
| [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, |
| [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, |
| @@ -431,9 +503,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, |
| struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, |
| const struct mtk_ddp_comp_funcs *funcs) |
| { |
| - enum mtk_ddp_comp_type type; |
| - struct device_node *larb_node; |
| - struct platform_device *larb_pdev; |
| + struct platform_device *comp_pdev; |
| #if IS_REACHABLE(CONFIG_MTK_CMDQ) |
| struct resource res; |
| struct cmdq_client_reg cmdq_reg; |
| @@ -443,8 +513,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, |
| if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) |
| return -EINVAL; |
| |
| - type = mtk_ddp_matches[comp_id].type; |
| - |
| comp->id = comp_id; |
| comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; |
| |
| @@ -468,30 +536,12 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, |
| if (IS_ERR(comp->clk)) |
| return PTR_ERR(comp->clk); |
| |
| - /* Only DMA capable components need the LARB property */ |
| - comp->larb_dev = NULL; |
| - if (type != MTK_DISP_OVL && |
| - type != MTK_DISP_OVL_2L && |
| - type != MTK_DISP_RDMA && |
| - type != MTK_DISP_WDMA) |
| - return 0; |
| - |
| - larb_node = of_parse_phandle(node, "mediatek,larb", 0); |
| - if (!larb_node) { |
| - dev_err(dev, |
| - "Missing mediadek,larb phandle in %pOF node\n", node); |
| - return -EINVAL; |
| - } |
| - |
| - larb_pdev = of_find_device_by_node(larb_node); |
| - if (!larb_pdev) { |
| - dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); |
| - of_node_put(larb_node); |
| + comp_pdev = of_find_device_by_node(node); |
| + if (!comp_pdev) { |
| + dev_err(dev, "Waiting for device %s\n", node->full_name); |
| return -EPROBE_DEFER; |
| } |
| - of_node_put(larb_node); |
| - |
| - comp->larb_dev = &larb_pdev->dev; |
| + comp->dev = &comp_pdev->dev; |
| |
| #if IS_REACHABLE(CONFIG_MTK_CMDQ) |
| if (of_address_to_resource(node, 0, &res) != 0) { |
| @@ -500,6 +550,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, |
| } |
| comp->regs_pa = res.start; |
| |
| + pr_err("%s comp_id %d regs 0x%px 0x%X\n", __func__, comp_id, comp->regs, comp->regs_pa); |
| + |
| ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); |
| if (ret) |
| dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |
| index debe36395fe721e2a57007daee484ad9b3d4db7e..54459db415fac05eeb2235df5f83146f57fda73b 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |
| @@ -28,6 +28,7 @@ enum mtk_ddp_comp_type { |
| MTK_DISP_UFOE, |
| MTK_DSI, |
| MTK_DPI, |
| + MTK_DISP_POSTMASK, |
| MTK_DISP_PWM, |
| MTK_DISP_MUTEX, |
| MTK_DISP_OD, |
| @@ -55,13 +56,16 @@ enum mtk_ddp_comp_id { |
| DDP_COMPONENT_OVL0, |
| DDP_COMPONENT_OVL_2L0, |
| DDP_COMPONENT_OVL_2L1, |
| + DDP_COMPONENT_OVL_2L2, |
| DDP_COMPONENT_OVL1, |
| + DDP_COMPONENT_POSTMASK0, |
| DDP_COMPONENT_PWM0, |
| DDP_COMPONENT_PWM1, |
| DDP_COMPONENT_PWM2, |
| DDP_COMPONENT_RDMA0, |
| DDP_COMPONENT_RDMA1, |
| DDP_COMPONENT_RDMA2, |
| + DDP_COMPONENT_RDMA4, |
| DDP_COMPONENT_UFOE, |
| DDP_COMPONENT_WDMA0, |
| DDP_COMPONENT_WDMA1, |
| @@ -76,8 +80,11 @@ struct mtk_ddp_comp_funcs { |
| unsigned int bpc, struct cmdq_pkt *cmdq_pkt); |
| void (*start)(struct mtk_ddp_comp *comp); |
| void (*stop)(struct mtk_ddp_comp *comp); |
| + void (*bypass_shadow)(struct mtk_ddp_comp *comp); |
| void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc); |
| void (*disable_vblank)(struct mtk_ddp_comp *comp); |
| + void (*prepare)(struct mtk_ddp_comp *comp); |
| + void (*unprepare)(struct mtk_ddp_comp *comp); |
| unsigned int (*supported_rotations)(struct mtk_ddp_comp *comp); |
| unsigned int (*layer_nr)(struct mtk_ddp_comp *comp); |
| int (*layer_check)(struct mtk_ddp_comp *comp, |
| @@ -98,7 +105,7 @@ struct mtk_ddp_comp { |
| struct clk *clk; |
| void __iomem *regs; |
| int irq; |
| - struct device *larb_dev; |
| + struct device *dev; |
| enum mtk_ddp_comp_id id; |
| const struct mtk_ddp_comp_funcs *funcs; |
| resource_size_t regs_pa; |
| @@ -114,6 +121,18 @@ static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp, |
| comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt); |
| } |
| |
| +static inline void mtk_ddp_comp_prepare(struct mtk_ddp_comp *comp) |
| +{ |
| + if (comp->funcs && comp->funcs->prepare) |
| + comp->funcs->prepare(comp); |
| +} |
| + |
| +static inline void mtk_ddp_comp_unprepare(struct mtk_ddp_comp *comp) |
| +{ |
| + if (comp->funcs && comp->funcs->unprepare) |
| + comp->funcs->unprepare(comp); |
| +} |
| + |
| static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp) |
| { |
| if (comp->funcs && comp->funcs->start) |
| @@ -200,6 +219,12 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, |
| comp->funcs->ctm_set(comp, state); |
| } |
| |
| +static inline void mtk_ddp_comp_bypass_shadow(struct mtk_ddp_comp *comp) |
| +{ |
| + if (comp->funcs && comp->funcs->bypass_shadow) |
| + comp->funcs->bypass_shadow(comp); |
| +} |
| + |
| int mtk_ddp_comp_get_id(struct device_node *node, |
| enum mtk_ddp_comp_type comp_type); |
| int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c |
| index a5dc770769c497c831f93a5a749c4a347807cc86..013725dfce70b32657a2000e5103c4333205674c 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c |
| @@ -7,6 +7,8 @@ |
| #include <linux/component.h> |
| #include <linux/iommu.h> |
| #include <linux/module.h> |
| +#include <linux/clk.h> |
| +#include <linux/of.h> |
| #include <linux/of_address.h> |
| #include <linux/of_platform.h> |
| #include <linux/pm_runtime.h> |
| @@ -107,6 +109,44 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { |
| DDP_COMPONENT_DPI0, |
| }; |
| |
| +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { |
| + DDP_COMPONENT_OVL0, |
| + DDP_COMPONENT_OVL_2L0, |
| + DDP_COMPONENT_RDMA0, |
| + DDP_COMPONENT_COLOR0, |
| + DDP_COMPONENT_CCORR, |
| + DDP_COMPONENT_AAL0, |
| + DDP_COMPONENT_GAMMA, |
| + DDP_COMPONENT_DITHER, |
| + DDP_COMPONENT_DSI0, |
| +}; |
| + |
| +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { |
| + DDP_COMPONENT_OVL_2L1, |
| + DDP_COMPONENT_RDMA1, |
| + DDP_COMPONENT_DPI0, |
| +}; |
| + |
| +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { |
| + DDP_COMPONENT_OVL_2L0, |
| + DDP_COMPONENT_OVL0, |
| + DDP_COMPONENT_RDMA0, |
| + DDP_COMPONENT_COLOR0, |
| + DDP_COMPONENT_CCORR, |
| + DDP_COMPONENT_AAL0, |
| + DDP_COMPONENT_GAMMA, |
| + DDP_COMPONENT_POSTMASK0, |
| + DDP_COMPONENT_DITHER, |
| + DDP_COMPONENT_DSI0, |
| +}; |
| + |
| +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { |
| + DDP_COMPONENT_OVL_2L2, |
| + DDP_COMPONENT_RDMA4, |
| + DDP_COMPONENT_DPI0, |
| +}; |
| + |
| + |
| static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { |
| .main_path = mt2701_mtk_ddp_main, |
| .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), |
| @@ -131,6 +171,20 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { |
| .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), |
| }; |
| |
| +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { |
| + .main_path = mt8183_mtk_ddp_main, |
| + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), |
| + .ext_path = mt8183_mtk_ddp_ext, |
| + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), |
| +}; |
| + |
| +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { |
| + .main_path = mt8192_mtk_ddp_main, |
| + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), |
| + .ext_path = mt8192_mtk_ddp_ext, |
| + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), |
| +}; |
| + |
| static int mtk_drm_kms_init(struct drm_device *drm) |
| { |
| struct mtk_drm_private *private = drm->dev_private; |
| @@ -305,6 +359,7 @@ static struct drm_driver mtk_drm_driver = { |
| |
| .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| + .gem_prime_export = drm_gem_prime_export, |
| .gem_prime_import = mtk_drm_gem_prime_import, |
| .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table, |
| .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, |
| @@ -384,42 +439,78 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { |
| .data = (void *)MTK_DISP_OVL }, |
| { .compatible = "mediatek,mt8173-disp-ovl", |
| .data = (void *)MTK_DISP_OVL }, |
| + { .compatible = "mediatek,mt8183-disp-ovl", |
| + .data = (void *)MTK_DISP_OVL }, |
| + { .compatible = "mediatek,mt8183-disp-ovl-2l", |
| + .data = (void *)MTK_DISP_OVL_2L }, |
| + { .compatible = "mediatek,mt8192-disp-ovl", |
| + .data = (void *)MTK_DISP_OVL }, |
| + { .compatible = "mediatek,mt8192-disp-ovl-2l", |
| + .data = (void *)MTK_DISP_OVL_2L }, |
| { .compatible = "mediatek,mt2701-disp-rdma", |
| .data = (void *)MTK_DISP_RDMA }, |
| { .compatible = "mediatek,mt8173-disp-rdma", |
| .data = (void *)MTK_DISP_RDMA }, |
| + { .compatible = "mediatek,mt8183-disp-rdma", |
| + .data = (void *)MTK_DISP_RDMA }, |
| + { .compatible = "mediatek,mt8192-disp-rdma", |
| + .data = (void *)MTK_DISP_RDMA }, |
| { .compatible = "mediatek,mt8173-disp-wdma", |
| .data = (void *)MTK_DISP_WDMA }, |
| + { .compatible = "mediatek,mt8183-disp-ccorr", |
| + .data = (void *)MTK_DISP_CCORR }, |
| + { .compatible = "mediatek,mt8192-disp-ccorr", |
| + .data = (void *)MTK_DISP_CCORR }, |
| { .compatible = "mediatek,mt2701-disp-color", |
| .data = (void *)MTK_DISP_COLOR }, |
| { .compatible = "mediatek,mt8173-disp-color", |
| .data = (void *)MTK_DISP_COLOR }, |
| + { .compatible = "mediatek,mt8192-disp-color", |
| + .data = (void *)MTK_DISP_COLOR }, |
| { .compatible = "mediatek,mt8173-disp-aal", |
| .data = (void *)MTK_DISP_AAL}, |
| + { .compatible = "mediatek,mt8192-disp-aal", |
| + .data = (void *)MTK_DISP_AAL}, |
| { .compatible = "mediatek,mt8173-disp-gamma", |
| .data = (void *)MTK_DISP_GAMMA, }, |
| + { .compatible = "mediatek,mt8192-disp-gamma", |
| + .data = (void *)MTK_DISP_GAMMA}, |
| + { .compatible = "mediatek,mt8183-disp-dither", |
| + .data = (void *)MTK_DISP_DITHER }, |
| + { .compatible = "mediatek,mt8192-disp-dither", |
| + .data = (void *)MTK_DISP_DITHER }, |
| { .compatible = "mediatek,mt8173-disp-ufoe", |
| .data = (void *)MTK_DISP_UFOE }, |
| { .compatible = "mediatek,mt2701-dsi", |
| .data = (void *)MTK_DSI }, |
| { .compatible = "mediatek,mt8173-dsi", |
| .data = (void *)MTK_DSI }, |
| + { .compatible = "mediatek,mt8183-dsi", |
| + .data = (void *)MTK_DSI }, |
| { .compatible = "mediatek,mt2701-dpi", |
| .data = (void *)MTK_DPI }, |
| { .compatible = "mediatek,mt8173-dpi", |
| .data = (void *)MTK_DPI }, |
| + { .compatible = "mediatek,mt8183-dpi", |
| + .data = (void *)MTK_DPI }, |
| { .compatible = "mediatek,mt2701-disp-mutex", |
| .data = (void *)MTK_DISP_MUTEX }, |
| { .compatible = "mediatek,mt2712-disp-mutex", |
| .data = (void *)MTK_DISP_MUTEX }, |
| { .compatible = "mediatek,mt8173-disp-mutex", |
| .data = (void *)MTK_DISP_MUTEX }, |
| + { .compatible = "mediatek,mt8183-disp-mutex", |
| + .data = (void *)MTK_DISP_MUTEX }, |
| + { .compatible = "mediatek,mt8192-disp-mutex", |
| + .data = (void *)MTK_DISP_MUTEX }, |
| { .compatible = "mediatek,mt2701-disp-pwm", |
| .data = (void *)MTK_DISP_BLS }, |
| { .compatible = "mediatek,mt8173-disp-pwm", |
| .data = (void *)MTK_DISP_PWM }, |
| { .compatible = "mediatek,mt8173-disp-od", |
| .data = (void *)MTK_DISP_OD }, |
| + { .compatible = "mediatek,mt8192-disp-postmask", |
| + .data = (void *)MTK_DISP_POSTMASK }, |
| { } |
| }; |
| |
| @@ -430,6 +521,10 @@ static const struct of_device_id mtk_drm_of_ids[] = { |
| .data = &mt2712_mmsys_driver_data}, |
| { .compatible = "mediatek,mt8173-mmsys", |
| .data = &mt8173_mmsys_driver_data}, |
| + { .compatible = "mediatek,mt8183-mmsys", |
| + .data = &mt8183_mmsys_driver_data}, |
| + { .compatible = "mediatek,mt8192-mmsys", |
| + .data = &mt8192_mmsys_driver_data}, |
| { } |
| }; |
| |
| @@ -444,6 +539,8 @@ static int mtk_drm_probe(struct platform_device *pdev) |
| int ret; |
| int i; |
| |
| + pr_info("%s\n", __func__); |
| + |
| private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); |
| if (!private) |
| return -ENOMEM; |
| @@ -543,6 +640,8 @@ static int mtk_drm_probe(struct platform_device *pdev) |
| if (ret) |
| goto err_pm; |
| |
| + pr_info("%s done\n", __func__); |
| + |
| return 0; |
| |
| err_pm: |
| @@ -619,6 +718,8 @@ static struct platform_driver * const mtk_drm_drivers[] = { |
| |
| static int __init mtk_drm_init(void) |
| { |
| + pr_info("info %s\n", __func__); |
| + |
| return platform_register_drivers(mtk_drm_drivers, |
| ARRAY_SIZE(mtk_drm_drivers)); |
| } |
| diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c |
| old mode 100644 |
| new mode 100755 |
| index 9ea40d6c180fe89c7e980e8993f4eaffad6e7e7a..fa2cb6c2022aaea3b1477b4be51548cf4ec8df2a |
| --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c |
| @@ -4,6 +4,7 @@ |
| */ |
| |
| #include <linux/dma-buf.h> |
| +#include <linux/pm_runtime.h> |
| #include <drm/mediatek_drm.h> |
| |
| #include <drm/drm.h> |
| @@ -56,6 +57,12 @@ struct mtk_drm_gem_obj *mtk_drm_gem_create(struct drm_device *dev, |
| if (!alloc_kmap) |
| mtk_gem->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
| |
| + ret = pm_runtime_get_sync(priv->dma_dev); |
| + if (ret < 0) |
| + DRM_DEV_ERROR(priv->dma_dev, "Failed to enable power domain: %d\n", |
| + ret); |
| + pr_err("%s %s size %d ret %d\n", __func__, dev_name(priv->dma_dev), obj->size, ret); |
| + |
| mtk_gem->cookie = dma_alloc_attrs(priv->dma_dev, obj->size, |
| &mtk_gem->dma_addr, GFP_KERNEL, |
| mtk_gem->dma_attrs); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c |
| index cfa45d6abd7426bb4d4b19aeecd1660590dcd4a6..8c95893da65ff9b0047db39683c51a06f029584d 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_dsi.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c |
| @@ -469,6 +469,12 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) |
| writel(vm->vactive << 16 | vm->hactive, |
| dsi->regs + DSI_SIZE_CON); |
| |
| + pr_err("%s 0x%px %dx%d 0x%X\n", |
| + __func__, |
| + dsi->regs, |
| + vm->hactive, vm->vactive, |
| + readl(dsi->regs + DSI_SIZE_CON)); |
| + |
| horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); |
| |
| if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
| @@ -619,8 +625,12 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) |
| int ret; |
| u32 bit_per_pixel; |
| |
| - if (++dsi->refcount != 1) |
| + if (++dsi->refcount != 1) { |
| + pr_warn("%s aready power on %d\n", __func__, dsi->refcount); |
| return 0; |
| + } |
| + |
| + DRM_DEBUG_DRIVER("%s\n", __func__); |
| |
| switch (dsi->format) { |
| case MIPI_DSI_FMT_RGB565: |
| @@ -645,7 +655,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) |
| goto err_refcount; |
| } |
| |
| - phy_power_on(dsi->phy); |
| + ret = phy_power_on(dsi->phy); |
| + |
| + dev_err(dev, "phy_power_on %d\n", ret); |
| |
| ret = clk_prepare_enable(dsi->engine_clk); |
| if (ret < 0) { |
| @@ -665,6 +677,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) |
| writel(FORCE_COMMIT | BYPASS_SHADOW, |
| dsi->regs + DSI_SHADOW_DEBUG); |
| |
| + pr_err("%s 0x%px shadow 0x%X\n", |
| + __func__, |
| + dsi->regs, |
| + readl(dsi->regs + DSI_SHADOW_DEBUG)); |
| + |
| mtk_dsi_reset_engine(dsi); |
| mtk_dsi_phy_timconfig(dsi); |
| |
| @@ -682,6 +699,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) |
| |
| if (dsi->panel) { |
| if (drm_panel_prepare(dsi->panel)) { |
| + dump_stack(); |
| DRM_ERROR("failed to prepare the panel\n"); |
| goto err_disable_digital_clk; |
| } |
| @@ -741,8 +759,12 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) |
| { |
| int ret; |
| |
| - if (dsi->enabled) |
| + if (dsi->enabled) { |
| + pr_warn("%s aready enable %d\n", __func__, dsi->enabled); |
| return; |
| + } |
| + |
| + DRM_DEBUG_DRIVER("%s\n", __func__); |
| |
| ret = mtk_dsi_poweron(dsi); |
| if (ret < 0) { |
| @@ -823,6 +845,8 @@ static void mtk_dsi_encoder_enable(struct drm_encoder *encoder) |
| { |
| struct mtk_dsi *dsi = encoder_to_dsi(encoder); |
| |
| + DRM_DEBUG_DRIVER("%s\n", __func__); |
| + |
| mtk_output_dsi_enable(dsi); |
| } |
| |
| @@ -937,6 +961,8 @@ static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) |
| { |
| struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); |
| |
| + DRM_DEBUG_DRIVER("%s\n", __func__); |
| + |
| mtk_dsi_poweron(dsi); |
| } |
| |
| @@ -1224,6 +1250,8 @@ static int mtk_dsi_probe(struct platform_device *pdev) |
| goto err_unregister_host; |
| } |
| |
| + pr_err("%s regs 0x%px 0x%X\n", __func__, dsi->regs, regs->start); |
| + |
| dsi->phy = devm_phy_get(dev, "dphy"); |
| if (IS_ERR(dsi->phy)) { |
| ret = PTR_ERR(dsi->phy); |
| @@ -1252,11 +1280,11 @@ static int mtk_dsi_probe(struct platform_device *pdev) |
| goto err_unregister_host; |
| } |
| |
| - irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); |
| + //irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); |
| ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, |
| - IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); |
| + IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); |
| if (ret) { |
| - dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); |
| + dev_err(&pdev->dev, "failed to request mediatek dsi irqxxxxxxxxxxxxx\n"); |
| goto err_unregister_host; |
| } |
| |
| diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c |
| index e4d34484ecc82bd2d3874f8fb2219c33c4c768e3..ef645c28902fa83b68464446302261d87e756ceb 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c |
| @@ -41,6 +41,8 @@ int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
| |
| dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); |
| |
| + pr_err("%s \n", __func__); |
| + |
| mipi_tx->data_rate = rate; |
| |
| return 0; |
| @@ -59,6 +61,8 @@ static int mtk_mipi_tx_power_on(struct phy *phy) |
| struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
| int ret; |
| |
| + pr_err("%s \n", __func__); |
| + |
| /* Power up core and enable PLL */ |
| ret = clk_prepare_enable(mipi_tx->pll); |
| if (ret < 0) |
| @@ -73,6 +77,8 @@ static int mtk_mipi_tx_power_off(struct phy *phy) |
| { |
| struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
| |
| + pr_err("%s \n", __func__); |
| + |
| /* Enable pad tie low, disable DSI Lane LDO outputs */ |
| mipi_tx->driver_data->mipi_tx_disable_signal(phy); |
| |
| @@ -118,6 +124,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) |
| return ret; |
| } |
| |
| + pr_err("%s regs 0x%px 0x%X\n", __func__, mipi_tx->regs, mem->start); |
| + |
| ref_clk = devm_clk_get(dev, NULL); |
| if (IS_ERR(ref_clk)) { |
| ret = PTR_ERR(ref_clk); |
| diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |
| index 91f08a351fd0781e487278e60174bc4fd0f57bb5..d2c77d4ce94cc80c520cefd5833b710e66174786 100644 |
| --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |
| +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |
| @@ -47,6 +47,8 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) |
| |
| dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate); |
| |
| + pr_err("%s enable: %u bps\n", __func__, mipi_tx->data_rate); |
| + |
| if (mipi_tx->data_rate >= 2000000000) { |
| txdiv = 1; |
| txdiv0 = 0; |
| @@ -85,6 +87,8 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) |
| { |
| struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); |
| |
| + pr_err("%s \n", __func__); |
| + |
| mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); |
| |
| mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); |
| @@ -109,6 +113,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) |
| { |
| struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
| |
| + pr_err("%s \n", __func__); |
| + |
| /* BG_LPF_EN / BG_CORE_EN */ |
| writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, |
| mipi_tx->regs + MIPITX_LANE_CON); |
| @@ -130,6 +136,8 @@ static void mtk_mipi_tx_power_off_signal(struct phy *phy) |
| { |
| struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
| |
| + pr_err("%s \n", __func__); |
| + |
| /* Switch ON each Lane */ |
| mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); |
| mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); |
| diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig |
| index 6c04892625682f142a18a3463fd4ec8ac88cfc2d..1ad1654cf8064c749fd8127b775d168f0ebff1aa 100644 |
| --- a/drivers/gpu/drm/panel/Kconfig |
| +++ b/drivers/gpu/drm/panel/Kconfig |
| @@ -384,4 +384,14 @@ config DRM_PANEL_VISIONOX_RM69299 |
| Say Y here if you want to enable support for Visionox |
| RM69299 DSI Video Mode panel. |
| |
| +config DRM_PANEL_TRULY_TD4330_VDO |
| + tristate "TRULY FHD+ video mode panel" |
| + depends on OF |
| + depends on DRM_MIPI_DSI |
| + depends on BACKLIGHT_CLASS_DEVICE |
| + help |
| + Say Y here if you want to enable support for TRULY TD4330 VDO |
| + mode Full HD Plus panel. The panel has a 1080x2280 resolution |
| + and uses 24-bits RGB per pixel. It provides a MIPI DSI interface |
| + to host. |
| endmenu |
| diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile |
| index 526bbb79e28ee15e2f694be96f5dc8147ce3a904..f790e2a3de4c645300e7cdd9716e2594e0fdbb74 100644 |
| --- a/drivers/gpu/drm/panel/Makefile |
| +++ b/drivers/gpu/drm/panel/Makefile |
| @@ -41,3 +41,4 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o |
| obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o |
| obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o |
| obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o |
| +obj-$(CONFIG_DRM_PANEL_TRULY_TD4330_VDO) += panel-truly-td4330.o |
| diff --git a/drivers/gpu/drm/panel/panel-truly-td4330.c b/drivers/gpu/drm/panel/panel-truly-td4330.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..68da9bc72589610feeb526d6658d14f60ad5a677 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/panel/panel-truly-td4330.c |
| @@ -0,0 +1,509 @@ |
| +// SPDX-License-Identifier: GPL-2.0-only |
| +/* |
| + * Copyright (c) 2015 MediaTek Inc. |
| + */ |
| + |
| +#include <linux/backlight.h> |
| +#include <drm/drmP.h> |
| +#include <drm/drm_mipi_dsi.h> |
| +#include <drm/drm_panel.h> |
| + |
| +#include <linux/gpio/consumer.h> |
| +#include <linux/regulator/consumer.h> |
| + |
| +#include <video/mipi_display.h> |
| +#include <video/of_videomode.h> |
| +#include <video/videomode.h> |
| + |
| +#include <linux/backlight.h> |
| +#include <linux/module.h> |
| +#include <linux/of_platform.h> |
| +#include <linux/platform_device.h> |
| +#include <linux/regulator/consumer.h> |
| + |
| +struct td4330 { |
| + struct device *dev; |
| + struct drm_panel panel; |
| + struct backlight_device *backlight; |
| + struct gpio_desc *reset_gpio; |
| + |
| + bool prepared; |
| + bool enabled; |
| + bool lk_fastlogo; |
| + int error; |
| +}; |
| + |
| +#define td4330_dcs_write_seq(ctx, seq...) \ |
| +({\ |
| + const u8 d[] = { seq };\ |
| + BUILD_BUG_ON_MSG(ARRAY_SIZE(d) > 64, "DCS sequence too big for stack");\ |
| + td4330_dcs_write(ctx, d, ARRAY_SIZE(d));\ |
| +}) |
| + |
| +#define td4330_dcs_write_seq_static(ctx, seq...) \ |
| +({\ |
| + static const u8 d[] = { seq };\ |
| + td4330_dcs_write(ctx, d, ARRAY_SIZE(d));\ |
| +}) |
| + |
| +static inline struct td4330 *panel_to_td4330(struct drm_panel *panel) |
| +{ |
| + return container_of(panel, struct td4330, panel); |
| +} |
| + |
| +static void td4330_dcs_write(struct td4330 *ctx, const void *data, size_t len) |
| +{ |
| + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); |
| + ssize_t ret; |
| + |
| + if (ctx->error < 0) |
| + return; |
| + |
| + ret = mipi_dsi_dcs_write_buffer(dsi, data, len); |
| + if (ret < 0) { |
| + dev_err(ctx->dev, |
| + "error %d writing dcs seq: 0x%x data(0x%p)\n", |
| + ret, (unsigned int)len, data); |
| + ctx->error = ret; |
| + } |
| +} |
| + |
| +static void td4330_panel_init(struct td4330 *ctx) |
| +{ |
| + td4330_dcs_write_seq_static(ctx, 0xB0, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xB6, 0x30, 0x6B, 0x00, 0x06, 0x03, |
| + 0x0A, 0x13, 0x1A, 0x6C, 0x18, 0x19, 0x02); |
| + td4330_dcs_write_seq_static(ctx, 0xB7, 0x51, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xB8, 0x57, 0x3d, 0x19, 0xbe, 0x1e, |
| + 0x0a, 0x0a); |
| + td4330_dcs_write_seq_static(ctx, 0xB9, 0x6f, 0x3d, 0x28, 0xbe, 0x3c, |
| + 0x14, 0x0a); |
| + td4330_dcs_write_seq_static(ctx, 0xBA, 0xb5, 0x33, 0x41, 0xbe, 0x64, |
| + 0x23, 0x0a); |
| + td4330_dcs_write_seq_static(ctx, 0xBB, 0x44, 0x26, 0xC3, 0x1F, 0x19, |
| + 0x06, 0x03, 0xC0, 0x00, 0x00, 0x10); |
| + td4330_dcs_write_seq_static(ctx, 0xBC, 0x32, 0x4C, 0xC3, 0x52, 0x32, |
| + 0x1F, 0x03, 0xF2, 0x00, 0x00, 0x13); |
| + td4330_dcs_write_seq_static(ctx, 0xBD, 0x24, 0x68, 0xC3, 0xAA, 0x3F, |
| + 0x32, 0x03, 0xFF, 0x00, 0x00, 0x25); |
| + td4330_dcs_write_seq_static(ctx, 0xBE, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC0, 0x00, 0xDC, 0x00, 0xDC, 0x04, |
| + 0x08, 0xE8, 0x00, 0x04, 0x00, 0x03, 0x78); |
| + td4330_dcs_write_seq_static(ctx, 0xC1, 0x30, 0x00, 0x00, 0x11, 0x11, |
| + 0x00, 0x00, 0x00, 0x22, 0x00, 0x05, 0x20, 0xFA, 0x00, 0x08, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC2, 0x06, 0xE0, 0x6E, 0x01, 0x03, |
| + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, |
| + 0x00, 0x04, 0xA0, 0xC9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x48, 0xEB, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x00, |
| + 0x00, 0x04, 0x00, 0x08, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC4, 0x00, 0x4c, 0x00, 0x3f, 0x00, |
| + 0x83, 0x00, 0x00, 0x87, 0x86, 0x85, 0x84, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x61, 0x5d, 0x5f, 0x00, 0x5e, 0x60, 0x62, 0x00, |
| + 0x00, 0x00, 0x02, 0x00, 0x83, 0x00, 0x00, 0x87, 0x86, 0x85, |
| + 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x5d, 0x5f, 0x00, |
| + 0x5e, 0x60, 0x62, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, |
| + 0x0f, 0x0e, 0x00, 0x0f, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x0f, 0xee, 0x00, 0x0f, 0xee, 0x00, 0x00, 0xe0, |
| + 0x00, 0x00, 0xe0, 0x0e, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0xff, 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC5, 0x08, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC6, 0x02, 0x0a, 0x08, 0xfc, 0xff, |
| + 0xff, 0xff, 0x00, 0x00, 0x13, 0x01, 0xf0, 0x0c, 0x06, 0x01, |
| + 0x43, 0x43, 0x43, 0x00, 0x00, 0x00, 0x01, 0x77, 0x09, 0x28, |
| + 0x28, 0x06, 0x01, 0x43, 0x43, 0x43, 0x00, 0x00, 0x00, 0x01, |
| + 0x61, 0x00, 0x00, 0x00, 0x1c, 0x01, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, |
| + 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xC7, 0x00, 0x00, 0x00, 0xe0, 0x01, |
| + 0xE9, 0x02, 0x7e, 0x02, 0x05, 0x02, 0x90, 0x02, 0xf6, 0x02, |
| + 0x40, 0x02, 0x5C, 0x02, 0x77, 0x02, 0xC8, 0x02, 0x1b, 0x02, |
| + 0x5b, 0x02, 0xBd, 0x02, 0x27, 0x02, 0xc3, 0x03, 0x54, 0x03, |
| + 0xd8, 0x03, 0xff, 0x00, 0x00, 0x00, 0xe0, 0x01, 0xE9, 0x02, |
| + 0x7e, 0x02, 0x05, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x40, 0x02, |
| + 0x5C, 0x02, 0x77, 0x02, 0xC8, 0x02, 0x1b, 0x02, 0x5b, 0x02, |
| + 0xBd, 0x02, 0x27, 0x02, 0xc3, 0x03, 0x54, 0x03, 0xd8, 0x03, |
| + 0xff); |
| + td4330_dcs_write_seq_static(ctx, 0xC8, 0x41, 0x00, 0xff, 0xfa, 0x00, |
| + 0xff, 0x00, 0x00, 0xfe, 0xf6, 0xfe, 0xe9, 0x00, 0x00, 0xff, |
| + 0xf7, 0xfb, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, |
| + 0x00, 0xff, 0xfa, 0x00, 0xff, 0x00, 0xfe, 0xf6, 0xfe, 0xe9, |
| + 0x00, 0xff, 0xf7, 0xfb, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xff, |
| + 0x00, 0xff, 0xfa, 0x00, 0xff, 0x00, 0xfe, 0xf6, 0xfe, 0xe9, |
| + 0x00, 0xff, 0xf7, 0xfb, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xff); |
| + td4330_dcs_write_seq_static(ctx, 0xC9, 0x00, 0xff, 0xfa, 0x00, 0xff, |
| + 0x00, 0x00, 0xfe, 0xf6, 0xfe, 0xe9, 0x00, 0x00, 0xff, 0xf7, |
| + 0xfb, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xCA, 0x1c, 0xfc, 0xfc, 0xfc, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xCC, 0x00, 0x00, 0x4d, 0x8b, 0x55, |
| + 0x4d, 0x8b, 0xaa, 0x4d, 0x8b); |
| + td4330_dcs_write_seq_static(ctx, 0xCD, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xCE, 0x5d, 0x40, 0x49, 0x53, 0x59, |
| + 0x5e, 0x63, 0x68, 0x6e, 0x74, 0x7e, 0x8a, 0x98, 0xa8, 0xbb, |
| + 0xd0, 0xe7, 0xff, 0x04, 0x00, 0x04, 0x04, 0x42, 0x04, 0x69, |
| + 0x5a, 0x40, 0x11, 0xf4, 0x00, 0x00, 0x84, 0xfa, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xCF, 0x00, 0x00, 0x80, 0x46, 0x61, |
| + 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xD0, 0xf6, 0x95, 0x11, 0xb1, 0x55, |
| + 0xcf, 0x00, 0xf6, 0xd3, 0x11, 0xf0, 0x01, 0x12, 0xcf, 0x02, |
| + 0x20, 0x11); |
| + td4330_dcs_write_seq_static(ctx, 0xD1, 0xd3, 0xd3, 0x33, 0x33, 0x07, |
| + 0x03, 0x3b, 0x33, 0x77, 0x37, 0x77, 0x37, 0x35, 0x77, 0x07, |
| + 0x77, 0xf7, 0x33, 0x73, 0x07, 0x33, 0x33, 0x03, 0x33, 0x1b, |
| + 0x03, 0x32, 0x3d, 0x0a, 0x30, 0x13, 0x13, 0x20, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xD2, 0x00, 0x00, 0x07, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xD3, 0x03, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x0f, 0x00, 0x57, 0x00, 0x00, 0x32, 0x00, 0x00, |
| + 0x1a, 0x70, 0x01, 0x19, 0x80, 0x01, 0x01, 0xf0, 0x02, 0x00, |
| + 0xe0, 0x06, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, |
| + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, |
| + 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, |
| + 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, |
| + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, |
| + 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, |
| + 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, |
| + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, |
| + 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, |
| + 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, |
| + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, |
| + 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, |
| + 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff); |
| + // And,VCOM,reference,setting, |
| + td4330_dcs_write_seq_static(ctx, 0xE5, 0x03, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xD5, 0x02, 0x42, 0x02, 0x42, 0x02, |
| + 0xdc, 0x02, 0xdc); |
| + td4330_dcs_write_seq_static(ctx, 0xD6, 0xc0); |
| + td4330_dcs_write_seq_static(ctx, 0xD7, 0x21, 0x10, 0x52, 0x52, 0x00, |
| + 0xB6, 0x04, 0xFD, 0x00, 0xB6, 0x04, 0xFD, 0x00, 0x82, 0x80, |
| + 0x83, 0x84, 0x85, 0x83, 0x80, 0x84, 0x45, 0x85, 0x85, 0x85, |
| + 0x87, 0x04, 0x06, 0x02, 0x04, 0x04, 0x07, 0x10, 0x0C, 0x0B, |
| + 0x0A, 0x0A, 0x07, 0x06, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xDD, 0x30, 0x06, 0x23, 0x65); |
| + td4330_dcs_write_seq_static(ctx, 0xDE, 0x00, 0x00, 0x00, 0x0f, 0xff, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10); |
| + td4330_dcs_write_seq_static(ctx, 0xE3, 0xff); |
| + td4330_dcs_write_seq_static(ctx, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xE7, 0x50, 0x04, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xE8, 0x00, 0x01, 0x23, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xEA, 0x01, 0x02, 0x47, 0x80, 0x47, |
| + 0x00, 0x00, 0x00, 0x05, 0x00, 0x13, 0x60, 0x02, 0x47, 0x80, |
| + 0x47, 0x00, 0x00, 0x00, 0x00, 0x13, 0x60, 0x00, 0x11, 0x00, |
| + 0x30, 0x10, 0x21, 0x02); |
| + td4330_dcs_write_seq_static(ctx, 0xEB, 0x00, 0x00, 0x00, 0x00, 0x01, |
| + 0x00, 0x11); |
| + td4330_dcs_write_seq_static(ctx, 0xEC, 0x00, 0x00, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xED, 0x01, 0x01, 0x02, 0x02, 0x02, |
| + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, |
| + 0x00, 0x00, 0x10, 0x00, 0x18, 0x00, 0x18, 0x00, 0xB0, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0xDA, 0x10, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xEE, 0x03, 0x0F, 0x00, 0x00, 0x00, |
| + 0x00, 0x40, 0x1F, 0x00, 0x00, 0x0F, 0xF2, 0x3F, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x09, 0x01, 0x8C, 0xD8, |
| + 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, |
| + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0xEF, 0x00, 0x70, 0x4A, 0x08, 0xD0, |
| + 0x00, 0x00, 0x00, 0x00, 0x3C, 0x3C, 0x3C, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x70, 0x4A, 0x08, 0xD0, 0x00, 0x00, 0x00, |
| + 0x00, 0x3C, 0x3C, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xEC, |
| + 0x50, 0x10, 0x00, 0x10, 0x00, 0x0A, 0x0A, 0x00, 0x00, 0x00, |
| + 0x00, 0x10, 0x0F, 0x00, 0x03, 0x51, 0x00, 0x50, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| + 0x00, 0x03, 0x08, 0xEC); |
| + td4330_dcs_write_seq_static(ctx, 0xB0, 0x03); |
| + /* Unlock,Manufacture,Command,Access,Protect,of,group,M,and,A */ |
| + td4330_dcs_write_seq_static(ctx, 0xB0, 0x04); |
| + /* OTP/Flash,Load,setting */ |
| + td4330_dcs_write_seq_static(ctx, 0xD6, 0x00); |
| + /* CABC */ |
| + td4330_dcs_write_seq_static(ctx, 0x51, 0xff, 0xf0); |
| + td4330_dcs_write_seq_static(ctx, 0x53, 0x0c); |
| + td4330_dcs_write_seq_static(ctx, 0x55, 0x00);/* Write_CABC */ |
| + /* TE ON */ |
| + td4330_dcs_write_seq_static(ctx, 0x35, 0x00); |
| + td4330_dcs_write_seq_static(ctx, 0x35); |
| + td4330_dcs_write_seq_static(ctx, 0x29); |
| + msleep(120); |
| + td4330_dcs_write_seq_static(ctx, 0x11); |
| + msleep(100); |
| +} |
| + |
| +static int td4330_disable(struct drm_panel *panel) |
| +{ |
| + struct td4330 *ctx = panel_to_td4330(panel); |
| + |
| + if (!ctx->enabled) |
| + return 0; |
| + |
| + if (ctx->backlight) { |
| + ctx->backlight->props.power = FB_BLANK_POWERDOWN; |
| + backlight_update_status(ctx->backlight); |
| + } |
| + |
| + ctx->enabled = false; |
| + |
| + return 0; |
| +} |
| + |
| +static int td4330_unprepare(struct drm_panel *panel) |
| +{ |
| + struct td4330 *ctx = panel_to_td4330(panel); |
| + |
| + if (!ctx->prepared) |
| + return 0; |
| + |
| + td4330_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF); |
| + msleep(50); |
| + td4330_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE); |
| + msleep(120); |
| + |
| + gpiod_set_value(ctx->reset_gpio, 0); |
| + msleep(30); |
| + |
| + ctx->error = 0; |
| + ctx->prepared = false; |
| + |
| + return 0; |
| +} |
| + |
| +static int td4330_prepare(struct drm_panel *panel) |
| +{ |
| + struct td4330 *ctx = panel_to_td4330(panel); |
| + int ret; |
| + |
| + if (ctx->prepared) |
| + return 0; |
| + |
| + gpiod_set_value(ctx->reset_gpio, 1); |
| + msleep(100); |
| + |
| + td4330_panel_init(ctx); |
| + |
| + ret = ctx->error; |
| + if (ret < 0) |
| + td4330_unprepare(panel); |
| + |
| + ctx->prepared = true; |
| + |
| + return ret; |
| +} |
| + |
| +static int td4330_enable(struct drm_panel *panel) |
| +{ |
| + struct td4330 *ctx = panel_to_td4330(panel); |
| + |
| + if (ctx->enabled) |
| + return 0; |
| + |
| + if (ctx->backlight) { |
| + ctx->backlight->props.power = FB_BLANK_UNBLANK; |
| + backlight_update_status(ctx->backlight); |
| + } |
| + |
| + ctx->enabled = true; |
| + |
| + return 0; |
| +} |
| + |
| +static const struct drm_display_mode default_mode = { |
| + .clock = 174027, |
| + .hdisplay = 1080, |
| + .hsync_start = 1080 + 40, |
| + .hsync_end = 1080 + 40 + 20, |
| + .htotal = 1080 + 40 + 20 + 40, |
| + .vdisplay = 2280, |
| + .vsync_start = 2280 + 10, |
| + .vsync_end = 2280 + 10 + 2, |
| + .vtotal = 2280 + 10 + 2 + 16, |
| + .vrefresh = 60, |
| +}; |
| + |
| +struct panel_desc { |
| + const struct drm_display_mode *modes; |
| + unsigned int num_modes; |
| + |
| + unsigned int bpc; |
| + |
| + struct { |
| + unsigned int width; |
| + unsigned int height; |
| + } size; |
| + |
| + /** |
| + * @prepare: the time (in milliseconds) that it takes for the panel to |
| + * become ready and start receiving video data |
| + * @enable: the time (in milliseconds) that it takes for the panel to |
| + * display the first valid frame after starting to receive |
| + * video data |
| + * @disable: the time (in milliseconds) that it takes for the panel to |
| + * turn the display off (no content is visible) |
| + * @unprepare: the time (in milliseconds) that it takes for the panel |
| + * to power itself down completely |
| + */ |
| + struct { |
| + unsigned int prepare; |
| + unsigned int enable; |
| + unsigned int disable; |
| + unsigned int unprepare; |
| + } delay; |
| +}; |
| + |
| +static int td4330_get_modes(struct drm_panel *panel, struct drm_connector *connector) |
| +{ |
| + struct drm_display_mode *mode; |
| + |
| + mode = drm_mode_duplicate(panel->drm, &default_mode); |
| + if (!mode) { |
| + dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", |
| + default_mode.hdisplay, default_mode.vdisplay, |
| + default_mode.vrefresh); |
| + return -ENOMEM; |
| + } |
| + |
| + drm_mode_set_name(mode); |
| + drm_mode_probed_add(connector, mode); |
| + |
| + connector->display_info.width_mm = 64; |
| + connector->display_info.height_mm = 129; |
| + |
| + return 1; |
| +} |
| + |
| +static const struct drm_panel_funcs td4330_drm_funcs = { |
| + .disable = td4330_disable, |
| + .unprepare = td4330_unprepare, |
| + .prepare = td4330_prepare, |
| + .enable = td4330_enable, |
| + .get_modes = td4330_get_modes, |
| +}; |
| + |
| +static int td4330_probe(struct mipi_dsi_device *dsi) |
| +{ |
| + struct device *dev = &dsi->dev; |
| + struct td4330 *ctx; |
| + struct device_node *backlight; |
| + int ret; |
| + |
| + ctx = devm_kzalloc(dev, sizeof(struct td4330), GFP_KERNEL); |
| + if (!ctx) |
| + return -ENOMEM; |
| + |
| + mipi_dsi_set_drvdata(dsi, ctx); |
| + |
| + ctx->dev = dev; |
| + |
| + dsi->lanes = 4; |
| + dsi->format = MIPI_DSI_FMT_RGB888; |
| + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
| + | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET |
| + | MIPI_DSI_CLOCK_NON_CONTINUOUS; |
| + |
| + backlight = of_parse_phandle(dev->of_node, "backlight", 0); |
| + if (backlight) { |
| + ctx->backlight = of_find_backlight_by_node(backlight); |
| + of_node_put(backlight); |
| + |
| + if (!ctx->backlight) |
| + return -EPROBE_DEFER; |
| + } |
| + |
| + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); |
| + if (IS_ERR(ctx->reset_gpio)) { |
| + dev_err(dev, "cannot get reset-gpios %ld\n", |
| + PTR_ERR(ctx->reset_gpio)); |
| + return PTR_ERR(ctx->reset_gpio); |
| + } |
| + |
| + ctx->prepared = false; |
| + |
| + drm_panel_init(&ctx->panel, dev, &td4330_drm_funcs, |
| + DRM_MODE_CONNECTOR_DSI); |
| + |
| + ret = drm_panel_add(&ctx->panel); |
| + if (ret < 0) |
| + return ret; |
| + |
| + ret = mipi_dsi_attach(dsi); |
| + if (ret < 0) |
| + drm_panel_remove(&ctx->panel); |
| + |
| + return ret; |
| +} |
| + |
| +static int td4330_remove(struct mipi_dsi_device *dsi) |
| +{ |
| + struct td4330 *ctx = mipi_dsi_get_drvdata(dsi); |
| + |
| + mipi_dsi_detach(dsi); |
| + drm_panel_remove(&ctx->panel); |
| + |
| + return 0; |
| +} |
| + |
| +static const struct of_device_id td4330_of_match[] = { |
| + { .compatible = "td,td4330", }, |
| + { } |
| +}; |
| + |
| +MODULE_DEVICE_TABLE(of, td4330_of_match); |
| + |
| +static struct mipi_dsi_driver td4330_driver = { |
| + .probe = td4330_probe, |
| + .remove = td4330_remove, |
| + .driver = { |
| + .name = "panel-td4330", |
| + .owner = THIS_MODULE, |
| + .of_match_table = td4330_of_match, |
| + }, |
| +}; |
| + |
| +module_mipi_dsi_driver(td4330_driver); |
| + |
| +MODULE_AUTHOR("Huijuan Xie <huijuan.xie@mediatek.com>"); |
| +MODULE_DESCRIPTION("Truly TD-td4330 LCD Panel Driver"); |
| +MODULE_LICENSE("GPL v2"); |
| + |
| diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c |
| index 2152ec5f535c19316b0d7800afbf1bd3a44e5768..103048b7ee612edc5e4f13dcd906077faa608aa1 100644 |
| --- a/drivers/i2c/busses/i2c-mt65xx.c |
| +++ b/drivers/i2c/busses/i2c-mt65xx.c |
| @@ -49,6 +49,9 @@ |
| |
| #define I2C_DMA_CON_TX 0x0000 |
| #define I2C_DMA_CON_RX 0x0001 |
| +#define I2C_DMA_ASYNC_MODE 0x0004 |
| +#define I2C_DMA_SKIP_CONFIG 0x0010 |
| +#define I2C_DMA_DIR_CHANGE 0x0200 |
| #define I2C_DMA_START_EN 0x0001 |
| #define I2C_DMA_INT_FLAG_NONE 0x0000 |
| #define I2C_DMA_CLR_FLAG 0x0000 |
| @@ -192,6 +195,7 @@ struct mtk_i2c_compatible { |
| unsigned char timing_adjust: 1; |
| unsigned char dma_sync: 1; |
| unsigned char ltiming_adjust: 1; |
| + unsigned char apdma_sync: 1; |
| }; |
| |
| struct mtk_i2c { |
| @@ -248,6 +252,7 @@ static const struct mtk_i2c_compatible mt2712_compat = { |
| .timing_adjust = 1, |
| .dma_sync = 0, |
| .ltiming_adjust = 0, |
| + .apdma_sync = 0, |
| }; |
| |
| static const struct mtk_i2c_compatible mt6577_compat = { |
| @@ -261,6 +266,7 @@ static const struct mtk_i2c_compatible mt6577_compat = { |
| .timing_adjust = 0, |
| .dma_sync = 0, |
| .ltiming_adjust = 0, |
| + .apdma_sync = 0, |
| }; |
| |
| static const struct mtk_i2c_compatible mt6589_compat = { |
| @@ -274,6 +280,7 @@ static const struct mtk_i2c_compatible mt6589_compat = { |
| .timing_adjust = 0, |
| .dma_sync = 0, |
| .ltiming_adjust = 0, |
| + .apdma_sync = 0, |
| }; |
| |
| static const struct mtk_i2c_compatible mt7622_compat = { |
| @@ -287,6 +294,7 @@ static const struct mtk_i2c_compatible mt7622_compat = { |
| .timing_adjust = 0, |
| .dma_sync = 0, |
| .ltiming_adjust = 0, |
| + .apdma_sync = 0, |
| }; |
| |
| static const struct mtk_i2c_compatible mt8173_compat = { |
| @@ -299,6 +307,7 @@ static const struct mtk_i2c_compatible mt8173_compat = { |
| .timing_adjust = 0, |
| .dma_sync = 0, |
| .ltiming_adjust = 0, |
| + .apdma_sync = 0, |
| }; |
| |
| static const struct mtk_i2c_compatible mt8183_compat = { |
| @@ -312,6 +321,21 @@ static const struct mtk_i2c_compatible mt8183_compat = { |
| .timing_adjust = 1, |
| .dma_sync = 1, |
| .ltiming_adjust = 1, |
| + .apdma_sync = 0, |
| +}; |
| + |
| +static const struct mtk_i2c_compatible mt8192_compat = { |
| + .quirks = &mt8183_i2c_quirks, |
| + .regs = mt_i2c_regs_v2, |
| + .pmic_i2c = 0, |
| + .dcm = 0, |
| + .auto_restart = 1, |
| + .aux_len_reg = 1, |
| + .support_33bits = 1, |
| + .timing_adjust = 1, |
| + .dma_sync = 1, |
| + .ltiming_adjust = 1, |
| + .apdma_sync = 1, |
| }; |
| |
| static const struct of_device_id mtk_i2c_of_match[] = { |
| @@ -321,6 +345,7 @@ static const struct of_device_id mtk_i2c_of_match[] = { |
| { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, |
| { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, |
| { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, |
| + { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, |
| {} |
| }; |
| MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); |
| @@ -565,6 +590,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, |
| u16 start_reg; |
| u16 control_reg; |
| u16 restart_flag = 0; |
| + u32 dma_sync = 0; |
| u32 reg_4g_mode; |
| u8 *dma_rd_buf = NULL; |
| u8 *dma_wr_buf = NULL; |
| @@ -624,10 +650,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, |
| mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); |
| } |
| |
| + if (i2c->dev_comp->apdma_sync) { |
| + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; |
| + if (i2c->op == I2C_MASTER_WRRD) |
| + dma_sync |= I2C_DMA_DIR_CHANGE; |
| + } |
| + |
| /* Prepare buffer data to start transfer */ |
| if (i2c->op == I2C_MASTER_RD) { |
| writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); |
| - writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); |
| + writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); |
| |
| dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); |
| if (!dma_rd_buf) |
| @@ -650,7 +682,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, |
| writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); |
| } else if (i2c->op == I2C_MASTER_WR) { |
| writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); |
| - writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); |
| + writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); |
| |
| dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); |
| if (!dma_wr_buf) |
| @@ -673,7 +705,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, |
| writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); |
| } else { |
| writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); |
| - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); |
| + writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); |
| |
| dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); |
| if (!dma_wr_buf) |
| diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c |
| index 4272fe4e17f4c9b322be38580c750594503b40d0..b4702bba393469131174cb0cc6c028357a056842 100644 |
| --- a/drivers/iommu/io-pgtable-arm-v7s.c |
| +++ b/drivers/iommu/io-pgtable-arm-v7s.c |
| @@ -50,20 +50,24 @@ |
| */ |
| #define ARM_V7S_ADDR_BITS 32 |
| #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) |
| +/* MediaTek. 1st 14 bit; 2nd: 8bits */ |
| +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6) |
| #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) |
| #define ARM_V7S_TABLE_SHIFT 10 |
| |
| -#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl)) |
| -#define ARM_V7S_TABLE_SIZE(lvl) \ |
| - (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte)) |
| +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (!arm_v7s_is_mtk_enabled(cfg) ?\ |
| + (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl))) |
| + |
| +#define ARM_V7S_TABLE_SIZE(lvl, cfg) \ |
| + (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte)) |
| |
| #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl)) |
| #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl))) |
| #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT)) |
| -#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1) |
| -#define ARM_V7S_LVL_IDX(addr, lvl) ({ \ |
| +#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1) |
| +#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \ |
| int _l = lvl; \ |
| - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \ |
| + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ |
| }) |
| |
| /* |
| @@ -112,9 +116,10 @@ |
| #define ARM_V7S_TEX_MASK 0x7 |
| #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) |
| |
| -/* MediaTek extend the two bits for PA 32bit/33bit */ |
| +/* MediaTek extend the bits below for PA 32bit/33bit/34bit */ |
| #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) |
| #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) |
| +#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) |
| |
| /* *well, except for TEX on level 2 large pages, of course :( */ |
| #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 |
| @@ -194,6 +199,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, |
| pte |= ARM_V7S_ATTR_MTK_PA_BIT32; |
| if (paddr & BIT_ULL(33)) |
| pte |= ARM_V7S_ATTR_MTK_PA_BIT33; |
| + if (paddr & BIT_ULL(34)) |
| + pte |= ARM_V7S_ATTR_MTK_PA_BIT34; |
| return pte; |
| } |
| |
| @@ -218,6 +225,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, |
| paddr |= BIT_ULL(32); |
| if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) |
| paddr |= BIT_ULL(33); |
| + if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) |
| + paddr |= BIT_ULL(34); |
| return paddr; |
| } |
| |
| @@ -234,7 +243,7 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, |
| struct device *dev = cfg->iommu_dev; |
| phys_addr_t phys; |
| dma_addr_t dma; |
| - size_t size = ARM_V7S_TABLE_SIZE(lvl); |
| + size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg); |
| void *table = NULL; |
| |
| if (lvl == 1) |
| @@ -280,7 +289,7 @@ static void __arm_v7s_free_table(void *table, int lvl, |
| { |
| struct io_pgtable_cfg *cfg = &data->iop.cfg; |
| struct device *dev = cfg->iommu_dev; |
| - size_t size = ARM_V7S_TABLE_SIZE(lvl); |
| + size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg); |
| |
| if (!cfg->coherent_walk) |
| dma_unmap_single(dev, __arm_v7s_dma_addr(table), size, |
| @@ -424,7 +433,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, |
| arm_v7s_iopte *tblp; |
| size_t sz = ARM_V7S_BLOCK_SIZE(lvl); |
| |
| - tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl); |
| + tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg); |
| if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz, |
| sz, lvl, tblp) != sz)) |
| return -EINVAL; |
| @@ -477,7 +486,7 @@ static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova, |
| int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); |
| |
| /* Find our entry at the current level */ |
| - ptep += ARM_V7S_LVL_IDX(iova, lvl); |
| + ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg); |
| |
| /* If we can install a leaf entry at this level, then do so */ |
| if (num_entries) |
| @@ -550,7 +559,7 @@ static void arm_v7s_free_pgtable(struct io_pgtable *iop) |
| struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop); |
| int i; |
| |
| - for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) { |
| + for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) { |
| arm_v7s_iopte pte = data->pgd[i]; |
| |
| if (ARM_V7S_PTE_IS_TABLE(pte, 1)) |
| @@ -602,9 +611,9 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, |
| if (!tablep) |
| return 0; /* Bytes unmapped */ |
| |
| - num_ptes = ARM_V7S_PTES_PER_LVL(2); |
| + num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg); |
| num_entries = size >> ARM_V7S_LVL_SHIFT(2); |
| - unmap_idx = ARM_V7S_LVL_IDX(iova, 2); |
| + unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg); |
| |
| pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg); |
| if (num_entries > 1) |
| @@ -646,7 +655,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, |
| if (WARN_ON(lvl > 2)) |
| return 0; |
| |
| - idx = ARM_V7S_LVL_IDX(iova, lvl); |
| + idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg); |
| ptep += idx; |
| do { |
| pte[i] = READ_ONCE(ptep[i]); |
| @@ -717,7 +726,7 @@ static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, |
| { |
| struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); |
| |
| - if (WARN_ON(upper_32_bits(iova))) |
| + if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias))) |
| return 0; |
| |
| return __arm_v7s_unmap(data, gather, iova, size, 1, data->pgd); |
| @@ -732,7 +741,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, |
| u32 mask; |
| |
| do { |
| - ptep += ARM_V7S_LVL_IDX(iova, ++lvl); |
| + ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg); |
| pte = READ_ONCE(*ptep); |
| ptep = iopte_deref(pte, lvl, data); |
| } while (ARM_V7S_PTE_IS_TABLE(pte, lvl)); |
| @@ -751,10 +760,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, |
| { |
| struct arm_v7s_io_pgtable *data; |
| |
| - if (cfg->ias > ARM_V7S_ADDR_BITS) |
| + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) |
| return NULL; |
| |
| - if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) |
| + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) |
| return NULL; |
| |
| if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | |
| @@ -775,8 +784,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, |
| |
| spin_lock_init(&data->split_lock); |
| data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", |
| - ARM_V7S_TABLE_SIZE(2), |
| - ARM_V7S_TABLE_SIZE(2), |
| + ARM_V7S_TABLE_SIZE(2, cfg), |
| + ARM_V7S_TABLE_SIZE(2, cfg), |
| ARM_V7S_TABLE_SLAB_FLAGS, NULL); |
| if (!data->l2_tables) |
| goto out_free_data; |
| diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c |
| index 2be96f1cdbd270ba15cc1fe121ca3f96a93ad4d3..d40d754b44692e0e4b190e530e6272920389c8a5 100644 |
| --- a/drivers/iommu/mtk_iommu.c |
| +++ b/drivers/iommu/mtk_iommu.c |
| @@ -20,6 +20,7 @@ |
| #include <linux/of_irq.h> |
| #include <linux/of_platform.h> |
| #include <linux/platform_device.h> |
| +#include <linux/pm_runtime.h> |
| #include <linux/slab.h> |
| #include <linux/spinlock.h> |
| #include <asm/barrier.h> |
| @@ -37,13 +38,19 @@ |
| #define REG_MMU_INVLD_START_A 0x024 |
| #define REG_MMU_INVLD_END_A 0x028 |
| |
| +#define REG_MMU_INV_SEL_MT6779 0x02c |
| #define REG_MMU_INV_SEL 0x038 |
| #define F_INVLD_EN0 BIT(0) |
| #define F_INVLD_EN1 BIT(1) |
| |
| -#define REG_MMU_STANDARD_AXI_MODE 0x048 |
| +#define REG_MMU_MISC_CTRL 0x048 |
| +#define REG_MMU_STANDARD_AXI_MODE_MT6779 (BIT(3) | BIT(19)) |
| + |
| #define REG_MMU_DCM_DIS 0x050 |
| |
| +#define REG_MMU_WR_LEN 0x054 |
| +#define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21)) |
| + |
| #define REG_MMU_CTRL_REG 0x110 |
| #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
| #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
| @@ -88,22 +95,20 @@ |
| #define REG_MMU1_INVLD_PA 0x148 |
| #define REG_MMU0_INT_ID 0x150 |
| #define REG_MMU1_INT_ID 0x154 |
| +#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
| +#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) |
| #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
| #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) |
| +#define F_MMU_INT_ID_COMM_APU_ID(a) ((a) & 0x3) |
| +#define F_MMU_INT_ID_SUB_APU_ID(a) (((a) >> 2) & 0x3) |
| |
| -#define MTK_PROTECT_PA_ALIGN 128 |
| - |
| -/* |
| - * Get the local arbiter ID and the portid within the larb arbiter |
| - * from mtk_m4u_id which is defined by MTK_M4U_ID. |
| - */ |
| -#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) |
| -#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) |
| +#define MTK_PROTECT_PA_ALIGN 256 |
| |
| struct mtk_iommu_domain { |
| struct io_pgtable_cfg cfg; |
| struct io_pgtable_ops *iop; |
| |
| + struct mtk_iommu_data *data; |
| struct iommu_domain domain; |
| }; |
| |
| @@ -134,25 +139,34 @@ static const struct iommu_ops mtk_iommu_ops; |
| #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
| |
| static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
| +static LIST_HEAD(iommu_vpulist); /* List the iommu_vpu HW */ |
| |
| -#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) |
| +#define for_each_m4u(data, head) list_for_each_entry(data, head, list) |
| |
| -/* |
| - * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain |
| - * for the performance. |
| - * |
| - * Here always return the mtk_iommu_data of the first probed M4U where the |
| - * iommu domain information is recorded. |
| - */ |
| -static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) |
| -{ |
| - struct mtk_iommu_data *data; |
| +struct mtk_iommu_iova_region { |
| + dma_addr_t iova_base; |
| + size_t size; |
| +}; |
| + |
| +static const struct mtk_iommu_iova_region single_domain[] = { |
| + {.iova_base = 0, .size = SZ_4G}, |
| +}; |
| |
| - for_each_m4u(data) |
| - return data; |
| +static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { |
| + { .iova_base = 0x0, .size = SZ_4G}, /* disp : 0 ~ 4G */ |
| + { .iova_base = SZ_4G, .size = SZ_4G}, /* vdec : 4G ~ 8G */ |
| + { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */ |
| + { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ |
| + { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ |
| +}; |
| |
| - return NULL; |
| -} |
| +static const struct mtk_iommu_iova_region mt8192_multi_dom_vpu[] = { |
| + { .iova_base = 0x70000000ULL, .size = 0x12600000}, /* APU CODE */ |
| + { .iova_base = 0x10000000ULL, .size = 0x10000000}, /* APU DATA */ |
| + { .iova_base = 0x04000000ULL, .size = 0x400000}, /* APU VLM */ |
| +}; |
| + |
| +static struct mtk_iommu_data *tmp_domain_alloc_data; /* Only for domain_alloc. */ |
| |
| static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
| { |
| @@ -162,10 +176,11 @@ static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
| static void mtk_iommu_tlb_flush_all(void *cookie) |
| { |
| struct mtk_iommu_data *data = cookie; |
| + struct list_head *head = data->plat_data->hw_list; |
| |
| - for_each_m4u(data) { |
| + for_each_m4u(data, head) { |
| writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
| - data->base + REG_MMU_INV_SEL); |
| + data->base + data->plat_data->inv_sel_reg); |
| writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); |
| wmb(); /* Make sure the tlb flush all done */ |
| } |
| @@ -175,14 +190,15 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
| size_t granule, void *cookie) |
| { |
| struct mtk_iommu_data *data = cookie; |
| + struct list_head *head = data->plat_data->hw_list; |
| unsigned long flags; |
| int ret; |
| u32 tmp; |
| |
| - for_each_m4u(data) { |
| + for_each_m4u(data, head) { |
| spin_lock_irqsave(&data->tlb_lock, flags); |
| writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
| - data->base + REG_MMU_INV_SEL); |
| + data->base + data->plat_data->inv_sel_reg); |
| |
| writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); |
| writel_relaxed(iova + size - 1, |
| @@ -226,7 +242,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
| struct mtk_iommu_data *data = dev_id; |
| struct mtk_iommu_domain *dom = data->m4u_dom; |
| u32 int_state, regval, fault_iova, fault_pa; |
| - unsigned int fault_larb, fault_port; |
| + unsigned int fault_larb, fault_port, sub_comm = 0; |
| bool layer, write; |
| |
| /* Read error info from registers */ |
| @@ -242,17 +258,30 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
| } |
| layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
| write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; |
| - fault_larb = F_MMU_INT_ID_LARB_ID(regval); |
| fault_port = F_MMU_INT_ID_PORT_ID(regval); |
| + if (data->plat_data->has_sub_comm[data->m4u_id]) { |
| + /* m4u1 is VPU in mt6779.*/ |
| + if (data->m4u_id && data->plat_data->m4u_plat == M4U_MT6779) { |
| + fault_larb = F_MMU_INT_ID_COMM_APU_ID(regval); |
| + sub_comm = F_MMU_INT_ID_SUB_APU_ID(regval); |
| + fault_port = 0; /* for mt6779 APU ID is irregular */ |
| + } else { |
| + fault_larb = F_MMU_INT_ID_COMM_ID(regval); |
| + sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); |
| + } |
| + } else { |
| + fault_larb = F_MMU_INT_ID_LARB_ID(regval); |
| + } |
| |
| - fault_larb = data->plat_data->larbid_remap[fault_larb]; |
| + fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb]; |
| |
| if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
| write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { |
| dev_err_ratelimited( |
| data->dev, |
| - "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", |
| - int_state, fault_iova, fault_pa, fault_larb, fault_port, |
| + "fault type=0x%x iova=0x%x pa=0x%x larb=%d sub_comm=%d port=%d regval=0x%x layer=%d %s\n", |
| + int_state, fault_iova, fault_pa, fault_larb, |
| + sub_comm, fault_port, regval, |
| layer, write ? "write" : "read"); |
| } |
| |
| @@ -270,14 +299,19 @@ static void mtk_iommu_config(struct mtk_iommu_data *data, |
| struct device *dev, bool enable) |
| { |
| struct mtk_smi_larb_iommu *larb_mmu; |
| - unsigned int larbid, portid; |
| + unsigned int larbid, portid, domid; |
| struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
| + const struct mtk_iommu_iova_region *region; |
| int i; |
| |
| for (i = 0; i < fwspec->num_ids; ++i) { |
| larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); |
| portid = MTK_M4U_TO_PORT(fwspec->ids[i]); |
| + domid = MTK_M4U_TO_DOM(fwspec->ids[i]); |
| + |
| larb_mmu = &data->larb_imu[larbid]; |
| + region = data->plat_data->iova_region + domid; |
| + larb_mmu->bank[portid] = upper_32_bits(region->iova_base); |
| |
| dev_dbg(dev, "%s iommu port: %d\n", |
| enable ? "enable" : "disable", portid); |
| @@ -291,7 +325,15 @@ static void mtk_iommu_config(struct mtk_iommu_data *data, |
| |
| static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
| { |
| - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
| + struct mtk_iommu_data *data = dom->data; |
| + |
| + /* Use the exist domain as there is one m4u pgtable here. */ |
| + if (data->m4u_dom) { |
| + dom->iop = data->m4u_dom->iop; |
| + dom->cfg = data->m4u_dom->cfg; |
| + dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; |
| + return 0; |
| + } |
| |
| dom->cfg = (struct io_pgtable_cfg) { |
| .quirks = IO_PGTABLE_QUIRK_ARM_NS | |
| @@ -299,8 +341,8 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
| IO_PGTABLE_QUIRK_TLBI_ON_MAP | |
| IO_PGTABLE_QUIRK_ARM_MTK_EXT, |
| .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
| - .ias = 32, |
| - .oas = 34, |
| + .ias = 34, |
| + .oas = 35, |
| .tlb = &mtk_iommu_flush_ops, |
| .iommu_dev = data->dev, |
| }; |
| @@ -318,6 +360,8 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
| |
| static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) |
| { |
| + struct mtk_iommu_data *data = tmp_domain_alloc_data; |
| + const struct mtk_iommu_iova_region *region; |
| struct mtk_iommu_domain *dom; |
| |
| if (type != IOMMU_DOMAIN_DMA) |
| @@ -330,12 +374,16 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) |
| if (iommu_get_dma_cookie(&dom->domain)) |
| goto free_dom; |
| |
| + dom->data = data; |
| if (mtk_iommu_domain_finalise(dom)) |
| goto put_dma_cookie; |
| |
| - dom->domain.geometry.aperture_start = 0; |
| - dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); |
| + region = data->plat_data->iova_region + data->cur_domid; |
| + dom->domain.geometry.aperture_start = region->iova_base; |
| + dom->domain.geometry.aperture_end = region->iova_base + |
| + region->size - 1; |
| dom->domain.geometry.force_aperture = true; |
| + tmp_domain_alloc_data = NULL; /* Avoid others call this global. */ |
| |
| return &dom->domain; |
| |
| @@ -390,14 +438,22 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, |
| phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
| { |
| struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
| - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
| + struct mtk_iommu_data *data = dom->data; |
| + int ret; |
| |
| /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
| if (data->enable_4GB) |
| paddr |= BIT_ULL(32); |
| |
| + ret = pm_runtime_get_sync(data->dev); |
| + if (ret < 0) { |
| + dev_err(data->dev, "pm runtime get fail %d in map.\n", ret); |
| + return ret; |
| + } |
| /* Synchronize with the tlb_lock */ |
| - return dom->iop->map(dom->iop, iova, paddr, size, prot); |
| + ret = dom->iop->map(dom->iop, iova, paddr, size, prot); |
| + pm_runtime_put_sync(data->dev); |
| + return ret; |
| } |
| |
| static size_t mtk_iommu_unmap(struct iommu_domain *domain, |
| @@ -405,33 +461,54 @@ static size_t mtk_iommu_unmap(struct iommu_domain *domain, |
| struct iommu_iotlb_gather *gather) |
| { |
| struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
| + struct mtk_iommu_data *data = dom->data; |
| + size_t sz; |
| + int ret; |
| + |
| + ret = pm_runtime_get_sync(data->dev); |
| + if (ret < 0) { |
| + dev_err(data->dev, "pm runtime get fail %d in unmap.\n", ret); |
| + return ret; |
| + } |
| + sz = dom->iop->unmap(dom->iop, iova, size, gather); |
| + pm_runtime_put_sync(data->dev); |
| |
| - return dom->iop->unmap(dom->iop, iova, size, gather); |
| + return sz; |
| } |
| |
| static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
| { |
| - mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data()); |
| + struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
| + struct mtk_iommu_data *data = dom->data; |
| + int ret; |
| + |
| + ret = pm_runtime_get_sync(data->dev); |
| + if (ret < 0) { |
| + dev_err(data->dev, "pm runtime get fail %d in tlb all.\n", ret); |
| + return; |
| + } |
| + mtk_iommu_tlb_flush_all(data); |
| + pm_runtime_put_sync(data->dev); |
| } |
| |
| static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, |
| struct iommu_iotlb_gather *gather) |
| { |
| - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
| + struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
| size_t length = gather->end - gather->start; |
| |
| if (gather->start == ULONG_MAX) |
| return; |
| |
| mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, |
| - data); |
| + dom->data); |
| } |
| |
| static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
| dma_addr_t iova) |
| { |
| struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
| - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
| + struct mtk_iommu_data *data = dom->data; |
| phys_addr_t pa; |
| |
| pa = dom->iop->iova_to_phys(dom->iop, iova); |
| @@ -445,41 +522,80 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
| { |
| struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
| struct mtk_iommu_data *data; |
| + struct device_link *link; |
| + struct device *larbdev; |
| + unsigned int larbid; |
| |
| if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
| return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
| |
| data = dev_iommu_priv_get(dev); |
| |
| + /* Link the consumer device with the smi-larb device(supplier) */ |
| + larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); |
| + larbdev = data->larb_imu[larbid].dev; |
| + if (larbdev) { |
| + link = device_link_add(dev, larbdev, |
| + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); |
| + if (!link) |
| + dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); |
| + } |
| + |
| return &data->iommu; |
| } |
| |
| static void mtk_iommu_release_device(struct device *dev) |
| { |
| struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
| + struct mtk_iommu_data *data; |
| + struct device *larbdev; |
| + unsigned int larbid; |
| |
| if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
| return; |
| |
| + data = dev_iommu_priv_get(dev); |
| + |
| + larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); |
| + larbdev = data->larb_imu[larbid].dev; |
| + if (larbdev) |
| + device_link_remove(dev, larbdev); |
| + |
| iommu_fwspec_free(dev); |
| } |
| |
| static struct iommu_group *mtk_iommu_device_group(struct device *dev) |
| { |
| - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
| + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
| + struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; |
| + struct list_head *hw_list = c_data->plat_data->hw_list; |
| + struct iommu_group *group; |
| + int domid; |
| |
| + /* If 2 M4U share a domain, Put the corresponding info in first data. */ |
| + data = list_first_entry(hw_list, typeof(*data), list); |
| if (!data) |
| return ERR_PTR(-ENODEV); |
| |
| - /* All the client devices are in the same m4u iommu-group */ |
| - if (!data->m4u_group) { |
| - data->m4u_group = iommu_group_alloc(); |
| - if (IS_ERR(data->m4u_group)) |
| + domid = MTK_M4U_TO_DOM(fwspec->ids[0]); |
| + if (domid >= data->plat_data->iova_region_cnt) { |
| + dev_err(data->dev, "domain id(%d/%d) is error.\n", |
| + domid, data->plat_data->iova_region_cnt); |
| + return ERR_PTR(-EINVAL); |
| + } |
| + |
| + group = data->m4u_group[domid]; |
| + if (!group) { |
| + group = iommu_group_alloc(); |
| + if (IS_ERR(group)) |
| dev_err(dev, "Failed to allocate M4U IOMMU group\n"); |
| + data->m4u_group[domid] = group; |
| } else { |
| - iommu_group_ref_get(data->m4u_group); |
| + iommu_group_ref_get(group); |
| } |
| - return data->m4u_group; |
| + data->cur_domid = domid; |
| + tmp_domain_alloc_data = data; |
| + return group; |
| } |
| |
| static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) |
| @@ -504,6 +620,43 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) |
| return iommu_fwspec_add_ids(dev, args->args, 1); |
| } |
| |
| +static void mtk_iommu_get_resv_regions(struct device *dev, |
| + struct list_head *head) |
| +{ |
| + struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
| + const struct mtk_iommu_iova_region *resv, *curdom; |
| + struct iommu_resv_region *region; |
| + int prot = IOMMU_WRITE | IOMMU_READ; |
| + unsigned int i; |
| + |
| + curdom = data->plat_data->iova_region + data->cur_domid; |
| + for (i = 0; i < data->plat_data->iova_region_cnt; i++) { |
| + resv = data->plat_data->iova_region + i; |
| + |
| + if (resv->iova_base <= curdom->iova_base || |
| + resv->iova_base + resv->size >= |
| + curdom->iova_base + curdom->size) |
| + continue; |
| + |
| + /* Only reserve when the region is in the current domain */ |
| + region = iommu_alloc_resv_region(resv->iova_base, resv->size, |
| + prot, IOMMU_RESV_RESERVED); |
| + if (!region) |
| + return; |
| + |
| + list_add_tail(®ion->list, head); |
| + } |
| +} |
| + |
| +static void mtk_iommu_put_resv_regions(struct device *dev, |
| + struct list_head *head) |
| +{ |
| + struct iommu_resv_region *entry, *next; |
| + |
| + list_for_each_entry_safe(entry, next, head, list) |
| + kfree(entry); |
| +} |
| + |
| static const struct iommu_ops mtk_iommu_ops = { |
| .domain_alloc = mtk_iommu_domain_alloc, |
| .domain_free = mtk_iommu_domain_free, |
| @@ -518,6 +671,8 @@ static const struct iommu_ops mtk_iommu_ops = { |
| .release_device = mtk_iommu_release_device, |
| .device_group = mtk_iommu_device_group, |
| .of_xlate = mtk_iommu_of_xlate, |
| + .get_resv_regions = mtk_iommu_get_resv_regions, |
| + .put_resv_regions = mtk_iommu_put_resv_regions, |
| .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, |
| }; |
| |
| @@ -526,17 +681,22 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) |
| u32 regval; |
| int ret; |
| |
| - ret = clk_prepare_enable(data->bclk); |
| - if (ret) { |
| - dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); |
| - return ret; |
| + /* bclk will be enabled in pm callback in power-domain case. */ |
| + if (!data->dev->pm_domain) { |
| + ret = clk_prepare_enable(data->bclk); |
| + if (ret) { |
| + dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", |
| + ret); |
| + return ret; |
| + } |
| } |
| |
| + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); |
| if (data->plat_data->m4u_plat == M4U_MT8173) |
| - regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
| + regval |= F_MMU_PREFETCH_RT_REPLACE_MOD | |
| F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; |
| else |
| - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; |
| + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; |
| writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
| |
| regval = F_L2_MULIT_HIT_EN | |
| @@ -572,9 +732,22 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) |
| writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); |
| } |
| writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
| + if (data->plat_data->has_wr_len) { |
| + /* write command throttling mode */ |
| + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); |
| + regval &= ~F_MMU_WR_THROT_DIS; |
| + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); |
| + } |
| |
| - if (data->plat_data->reset_axi) |
| - writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); |
| + if (data->plat_data->has_misc_ctrl[data->m4u_id]) { |
| + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); |
| + /* non-standard AXI mode */ |
| + regval &= ~REG_MMU_STANDARD_AXI_MODE_MT6779; |
| + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); |
| + } else if (data->plat_data->reset_axi) { |
| + /* The register is called STANDARD_AXI_MODE in this case */ |
| + writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); |
| + } |
| |
| if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, |
| dev_name(data->dev), (void *)data)) { |
| @@ -601,12 +774,14 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| struct component_match *match = NULL; |
| void *protect; |
| int i, larb_nr, ret; |
| + bool is_vpu; |
| |
| data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
| if (!data) |
| return -ENOMEM; |
| data->dev = dev; |
| data->plat_data = of_device_get_match_data(dev); |
| + is_vpu = data->plat_data->is_vpu; |
| |
| /* Protect memory. HW will access here while translation fault.*/ |
| protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); |
| @@ -637,12 +812,13 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| |
| larb_nr = of_count_phandle_with_args(dev->of_node, |
| "mediatek,larbs", NULL); |
| - if (larb_nr < 0) |
| + if (larb_nr < 0 && !is_vpu) |
| return larb_nr; |
| |
| - for (i = 0; i < larb_nr; i++) { |
| + for (i = 0; i < larb_nr && !is_vpu; i++) { |
| struct device_node *larbnode; |
| struct platform_device *plarbdev; |
| + bool larbdev_is_bound = false; |
| u32 id; |
| |
| larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); |
| @@ -659,18 +835,32 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| id = i; |
| |
| plarbdev = of_find_device_by_node(larbnode); |
| - if (!plarbdev) { |
| + if (plarbdev) { |
| + device_lock(&plarbdev->dev); |
| + larbdev_is_bound = device_is_bound(&plarbdev->dev); |
| + device_unlock(&plarbdev->dev); |
| + } |
| + if (!plarbdev || !larbdev_is_bound) { |
| of_node_put(larbnode); |
| return -EPROBE_DEFER; |
| } |
| data->larb_imu[id].dev = &plarbdev->dev; |
| |
| + if (data->plat_data->m4u1_mask == (1 << id)) |
| + data->m4u_id = 1; |
| + |
| component_match_add_release(dev, &match, release_of, |
| compare_of, larbnode); |
| } |
| |
| platform_set_drvdata(pdev, data); |
| |
| + pm_runtime_enable(dev); |
| + |
| + ret = pm_runtime_get_sync(dev); |
| + if (ret < 0) |
| + return ret; |
| + |
| ret = mtk_iommu_hw_init(data); |
| if (ret) |
| return ret; |
| @@ -688,28 +878,18 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| return ret; |
| |
| spin_lock_init(&data->tlb_lock); |
| - list_add_tail(&data->list, &m4ulist); |
| + list_add_tail(&data->list, data->plat_data->hw_list); |
| |
| if (!iommu_present(&platform_bus_type)) |
| bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); |
| |
| - return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
| -} |
| - |
| -static int mtk_iommu_remove(struct platform_device *pdev) |
| -{ |
| - struct mtk_iommu_data *data = platform_get_drvdata(pdev); |
| - |
| - iommu_device_sysfs_remove(&data->iommu); |
| - iommu_device_unregister(&data->iommu); |
| - |
| - if (iommu_present(&platform_bus_type)) |
| - bus_set_iommu(&platform_bus_type, NULL); |
| - |
| - clk_disable_unprepare(data->bclk); |
| - devm_free_irq(&pdev->dev, data->irq, data); |
| - component_master_del(&pdev->dev, &mtk_iommu_com_ops); |
| - return 0; |
| + /* |
| + * PM put here to make sure the pm ref cnt. |
| + * the consumer will power get when iommu is needed. |
| + */ |
| + pm_runtime_put_sync(dev); |
| + return is_vpu ? 0 : |
| + component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
| } |
| |
| static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
| @@ -718,8 +898,8 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
| struct mtk_iommu_suspend_reg *reg = &data->reg; |
| void __iomem *base = data->base; |
| |
| - reg->standard_axi_mode = readl_relaxed(base + |
| - REG_MMU_STANDARD_AXI_MODE); |
| + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); |
| + reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
| reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
| reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); |
| reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); |
| @@ -743,8 +923,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) |
| dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); |
| return ret; |
| } |
| - writel_relaxed(reg->standard_axi_mode, |
| - base + REG_MMU_STANDARD_AXI_MODE); |
| + |
| + /* Avoid first resume to affect the register below default value. */ |
| + if (!m4u_dom) |
| + return 0; |
| + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); |
| + writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
| writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
| writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); |
| writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); |
| @@ -758,6 +942,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) |
| } |
| |
| static const struct dev_pm_ops mtk_iommu_pm_ops = { |
| + SET_RUNTIME_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume, NULL) |
| SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) |
| }; |
| |
| @@ -766,49 +951,88 @@ static const struct mtk_iommu_plat_data mt2712_data = { |
| .has_4gb_mode = true, |
| .has_bclk = true, |
| .has_vld_pa_rng = true, |
| - .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, |
| + .hw_list = &m4ulist, |
| + .larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, |
| + .inv_sel_reg = REG_MMU_INV_SEL, |
| + .iova_region = single_domain, |
| + .iova_region_cnt = ARRAY_SIZE(single_domain), |
| +}; |
| + |
| +static const struct mtk_iommu_plat_data mt6779_data = { |
| + .m4u_plat = M4U_MT6779, |
| + .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, |
| + /* vp6a, vp6b, mdla/core2, mdla/edmc*/ |
| + .larbid_remap[1] = {2, 0, 3, 1}, |
| + .has_sub_comm = {true, true}, |
| + .has_wr_len = true, |
| + .has_misc_ctrl = {true, false}, |
| + .hw_list = &m4ulist, |
| + .inv_sel_reg = REG_MMU_INV_SEL_MT6779, |
| + .m4u1_mask = BIT(6), |
| + .iova_region = single_domain, |
| + .iova_region_cnt = ARRAY_SIZE(single_domain), |
| }; |
| |
| static const struct mtk_iommu_plat_data mt8173_data = { |
| .m4u_plat = M4U_MT8173, |
| .has_4gb_mode = true, |
| .has_bclk = true, |
| + .hw_list = &m4ulist, |
| .reset_axi = true, |
| - .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ |
| + .larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ |
| + .inv_sel_reg = REG_MMU_INV_SEL, |
| + .iova_region = single_domain, |
| + .iova_region_cnt = ARRAY_SIZE(single_domain), |
| }; |
| |
| static const struct mtk_iommu_plat_data mt8183_data = { |
| .m4u_plat = M4U_MT8183, |
| .reset_axi = true, |
| - .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, |
| + .hw_list = &m4ulist, |
| + .larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1}, |
| + .inv_sel_reg = REG_MMU_INV_SEL, |
| + .iova_region = single_domain, |
| + .iova_region_cnt = ARRAY_SIZE(single_domain), |
| +}; |
| + |
| +static const struct mtk_iommu_plat_data mt8192_data = { |
| + .m4u_plat = M4U_MT8192, |
| + .hw_list = &m4ulist, |
| + .larbid_remap[0] = {0, 0xff, 4, 7, 2, 9, 14, 17}, |
| + .larbid_remap[1] = {0, 1, 2}, |
| + .has_sub_comm = {true, true}, |
| + .has_wr_len = true, |
| + .has_misc_ctrl = {true, false}, |
| + .inv_sel_reg = REG_MMU_INV_SEL_MT6779, |
| + .m4u1_mask = BIT(21), |
| + .iova_region = mt8192_multi_dom, |
| + .iova_region_cnt = ARRAY_SIZE(mt8192_multi_dom), |
| +}; |
| + |
| +static const struct mtk_iommu_plat_data mt8192_data_vpu = { |
| + .m4u_plat = M4U_MT8192, |
| + .hw_list = &iommu_vpulist, |
| + .is_vpu = true, |
| + .iova_region = mt8192_multi_dom_vpu, |
| + .iova_region_cnt = ARRAY_SIZE(mt8192_multi_dom_vpu), |
| }; |
| |
| static const struct of_device_id mtk_iommu_of_ids[] = { |
| { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
| + { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
| { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
| { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
| + { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, |
| + { .compatible = "mediatek,mt8192-m4u-vpu", .data = &mt8192_data_vpu}, |
| {} |
| }; |
| |
| static struct platform_driver mtk_iommu_driver = { |
| .probe = mtk_iommu_probe, |
| - .remove = mtk_iommu_remove, |
| .driver = { |
| .name = "mtk-iommu", |
| .of_match_table = of_match_ptr(mtk_iommu_of_ids), |
| .pm = &mtk_iommu_pm_ops, |
| } |
| }; |
| - |
| -static int __init mtk_iommu_init(void) |
| -{ |
| - int ret; |
| - |
| - ret = platform_driver_register(&mtk_iommu_driver); |
| - if (ret != 0) |
| - pr_err("Failed to register MTK IOMMU driver\n"); |
| - |
| - return ret; |
| -} |
| - |
| -subsys_initcall(mtk_iommu_init) |
| +builtin_platform_driver(mtk_iommu_driver); |
| diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h |
| index ea949a324e33847403a8ce3e7e9800e5bc21e3f6..a456a91d3b5c05ca7efdd0d719c25a9ffd0ad50e 100644 |
| --- a/drivers/iommu/mtk_iommu.h |
| +++ b/drivers/iommu/mtk_iommu.h |
| @@ -16,33 +16,49 @@ |
| #include <linux/list.h> |
| #include <linux/spinlock.h> |
| #include <soc/mediatek/smi.h> |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| |
| struct mtk_iommu_suspend_reg { |
| - u32 standard_axi_mode; |
| + u32 misc_ctrl; |
| u32 dcm_dis; |
| u32 ctrl_reg; |
| u32 int_control0; |
| u32 int_main_control; |
| u32 ivrp_paddr; |
| u32 vld_pa_rng; |
| + u32 wr_len; |
| }; |
| |
| enum mtk_iommu_plat { |
| M4U_MT2701, |
| M4U_MT2712, |
| + M4U_MT6779, |
| M4U_MT8173, |
| M4U_MT8183, |
| + M4U_MT8192, |
| }; |
| |
| +struct mtk_iommu_iova_region; |
| + |
| struct mtk_iommu_plat_data { |
| enum mtk_iommu_plat m4u_plat; |
| bool has_4gb_mode; |
| |
| /* HW will use the EMI clock if there isn't the "bclk". */ |
| bool has_bclk; |
| + bool has_sub_comm[2]; |
| bool has_vld_pa_rng; |
| + bool has_wr_len; |
| + bool has_misc_ctrl[2]; |
| + struct list_head *hw_list; |
| + bool is_vpu; |
| bool reset_axi; |
| - unsigned char larbid_remap[MTK_LARB_NR_MAX]; |
| + u32 m4u1_mask; |
| + u32 inv_sel_reg; |
| + unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; |
| + |
| + const unsigned int iova_region_cnt; |
| + const struct mtk_iommu_iova_region *iova_region; |
| }; |
| |
| struct mtk_iommu_domain; |
| @@ -55,13 +71,15 @@ struct mtk_iommu_data { |
| phys_addr_t protect_base; /* protect memory base */ |
| struct mtk_iommu_suspend_reg reg; |
| struct mtk_iommu_domain *m4u_dom; |
| - struct iommu_group *m4u_group; |
| + struct iommu_group *m4u_group[MTK_M4U_DOM_NR_MAX]; |
| bool enable_4GB; |
| spinlock_t tlb_lock; /* lock for tlb range flush */ |
| |
| + u32 m4u_id; |
| struct iommu_device iommu; |
| const struct mtk_iommu_plat_data *plat_data; |
| |
| + unsigned int cur_domid; |
| struct list_head list; |
| struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; |
| }; |
| diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c |
| index 5c35ebc946912c3b8778c2e51081d1621cda99dd..cd16061ed0f9de997b853174150b85fe42bea59a 100644 |
| --- a/drivers/iommu/mtk_iommu_v1.c |
| +++ b/drivers/iommu/mtk_iommu_v1.c |
| @@ -422,7 +422,9 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
| struct of_phandle_args iommu_spec; |
| struct of_phandle_iterator it; |
| struct mtk_iommu_data *data; |
| - int err; |
| + struct device_link *link; |
| + struct device *larbdev; |
| + int larbid, err; |
| |
| of_for_each_phandle(&it, err, dev->of_node, "iommus", |
| "#iommu-cells", -1) { |
| @@ -444,6 +446,14 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
| |
| data = dev_iommu_priv_get(dev); |
| |
| + /* Link the consumer device with the smi-larb device(supplier) */ |
| + larbid = mt2701_m4u_to_larb(fwspec->ids[0]); |
| + larbdev = data->larb_imu[larbid].dev; |
| + link = device_link_add(dev, larbdev, |
| + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); |
| + if (!link) |
| + dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); |
| + |
| return &data->iommu; |
| } |
| |
| @@ -464,10 +474,17 @@ static void mtk_iommu_probe_finalize(struct device *dev) |
| static void mtk_iommu_release_device(struct device *dev) |
| { |
| struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
| + struct device *larbdev; |
| + unsigned int larbid; |
| |
| if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
| return; |
| |
| + |
| + larbid = mt2701_m4u_to_larb(fwspec->ids[0]); |
| + larbdev = data->larb_imu[larbid].dev; |
| + device_link_remove(dev, larbdev); |
| + |
| iommu_fwspec_free(dev); |
| } |
| |
| @@ -590,10 +607,15 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| |
| plarbdev = of_find_device_by_node(larb_spec.np); |
| if (!plarbdev) { |
| + bool larbdev_is_bound; |
| + |
| plarbdev = of_platform_device_create( |
| larb_spec.np, NULL, |
| platform_bus_type.dev_root); |
| - if (!plarbdev) { |
| + device_lock(&plarbdev->dev); |
| + larbdev_is_bound = device_is_bound(&plarbdev->dev); |
| + device_unlock(&plarbdev->dev); |
| + if (!plarbdev || !larbdev_is_bound) { |
| of_node_put(larb_spec.np); |
| return -EPROBE_DEFER; |
| } |
| @@ -628,22 +650,6 @@ static int mtk_iommu_probe(struct platform_device *pdev) |
| return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
| } |
| |
| -static int mtk_iommu_remove(struct platform_device *pdev) |
| -{ |
| - struct mtk_iommu_data *data = platform_get_drvdata(pdev); |
| - |
| - iommu_device_sysfs_remove(&data->iommu); |
| - iommu_device_unregister(&data->iommu); |
| - |
| - if (iommu_present(&platform_bus_type)) |
| - bus_set_iommu(&platform_bus_type, NULL); |
| - |
| - clk_disable_unprepare(data->bclk); |
| - devm_free_irq(&pdev->dev, data->irq, data); |
| - component_master_del(&pdev->dev, &mtk_iommu_com_ops); |
| - return 0; |
| -} |
| - |
| static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
| { |
| struct mtk_iommu_data *data = dev_get_drvdata(dev); |
| @@ -680,16 +686,10 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { |
| |
| static struct platform_driver mtk_iommu_driver = { |
| .probe = mtk_iommu_probe, |
| - .remove = mtk_iommu_remove, |
| .driver = { |
| .name = "mtk-iommu-v1", |
| .of_match_table = mtk_iommu_of_ids, |
| .pm = &mtk_iommu_pm_ops, |
| } |
| }; |
| - |
| -static int __init m4u_init(void) |
| -{ |
| - return platform_driver_register(&mtk_iommu_driver); |
| -} |
| -subsys_initcall(m4u_init); |
| +builtin_platform_driver(mtk_iommu_driver); |
| diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c |
| index a113e811faabea34387d0d15ac1e4b74315ec29c..ca2c62c618d74de185d6ba1e6ce75115509a31e7 100644 |
| --- a/drivers/memory/mtk-smi.c |
| +++ b/drivers/memory/mtk-smi.c |
| @@ -14,6 +14,7 @@ |
| #include <linux/platform_device.h> |
| #include <linux/pm_runtime.h> |
| #include <soc/mediatek/smi.h> |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| #include <dt-bindings/memory/mt2701-larb-port.h> |
| |
| /* mt8173 */ |
| @@ -40,6 +41,8 @@ |
| /* mt2712 */ |
| #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) |
| #define F_MMU_EN BIT(0) |
| +#define BANK_SEL(a) ((((a) & 0x3) << 8) || (((a) & 0x3) << 10) ||\ |
| + (((a) & 0x3) << 12) || (((a) & 0x3) << 14)) |
| |
| /* SMI COMMON */ |
| #define SMI_BUS_SEL 0x220 |
| @@ -84,6 +87,7 @@ struct mtk_smi_larb { /* larb: local arbiter */ |
| const struct mtk_smi_larb_gen *larb_gen; |
| int larbid; |
| u32 *mmu; |
| + u32 *bank; |
| }; |
| |
| static int mtk_smi_clk_enable(const struct mtk_smi *smi) |
| @@ -150,6 +154,7 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) |
| if (dev == larb_mmu[i].dev) { |
| larb->larbid = i; |
| larb->mmu = &larb_mmu[i].mmu; |
| + larb->bank = &larb_mmu[i].bank[0]; |
| return 0; |
| } |
| } |
| @@ -168,6 +173,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) |
| for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { |
| reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); |
| reg |= F_MMU_EN; |
| + reg |= BANK_SEL(larb->bank[i]); |
| writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); |
| } |
| } |
| @@ -246,6 +252,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { |
| /* IPU0 | IPU1 | CCU */ |
| }; |
| |
| +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { |
| + .has_gals = true, |
| + .config_port = mtk_smi_larb_config_port_gen2_general, |
| + .larb_direct_to_common_mask = BIT(6) | BIT(10) | BIT(12)| BIT(15) | |
| + BIT(21), |
| +}; |
| + |
| static const struct of_device_id mtk_smi_larb_of_ids[] = { |
| { |
| .compatible = "mediatek,mt8173-smi-larb", |
| @@ -263,6 +276,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { |
| .compatible = "mediatek,mt8183-smi-larb", |
| .data = &mtk_smi_larb_mt8183 |
| }, |
| + { |
| + .compatible = "mediatek,mt8192-smi-larb", |
| + .data = &mtk_smi_larb_mt8192 |
| + }, |
| {} |
| }; |
| |
| @@ -395,6 +412,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { |
| F_MMU1_LARB(7), |
| }; |
| |
| +static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { |
| + .gen = MTK_SMI_GEN2, |
| + .has_gals = true, |
| + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | |
| + F_MMU1_LARB(6), |
| +}; |
| + |
| static const struct of_device_id mtk_smi_common_of_ids[] = { |
| { |
| .compatible = "mediatek,mt8173-smi-common", |
| @@ -412,6 +436,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { |
| .compatible = "mediatek,mt8183-smi-common", |
| .data = &mtk_smi_common_mt8183, |
| }, |
| + { |
| + .compatible = "mediatek,mt8192-smi-common", |
| + .data = &mtk_smi_common_mt8192, |
| + }, |
| {} |
| }; |
| |
| diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c |
| index db734f2831ff07080709e7c33aea5050fbe205e2..db82273446ce6f9b54924de5536b3124d2ca0128 100644 |
| --- a/drivers/mfd/mt6358-irq.c |
| +++ b/drivers/mfd/mt6358-irq.c |
| @@ -5,6 +5,8 @@ |
| #include <linux/interrupt.h> |
| #include <linux/mfd/mt6358/core.h> |
| #include <linux/mfd/mt6358/registers.h> |
| +#include <linux/mfd/mt6359/core.h> |
| +#include <linux/mfd/mt6359/registers.h> |
| #include <linux/mfd/mt6397/core.h> |
| #include <linux/module.h> |
| #include <linux/of.h> |
| @@ -13,6 +15,8 @@ |
| #include <linux/platform_device.h> |
| #include <linux/regmap.h> |
| |
| +#define MTK_PMIC_REG_WIDTH 16 |
| + |
| static struct irq_top_t mt6358_ints[] = { |
| MT6358_TOP_GEN(BUCK), |
| MT6358_TOP_GEN(LDO), |
| @@ -24,6 +28,31 @@ static struct irq_top_t mt6358_ints[] = { |
| MT6358_TOP_GEN(MISC), |
| }; |
| |
| +static struct irq_top_t mt6359_ints[] = { |
| + MT6359_TOP_GEN(BUCK), |
| + MT6359_TOP_GEN(LDO), |
| + MT6359_TOP_GEN(PSC), |
| + MT6359_TOP_GEN(SCK), |
| + MT6359_TOP_GEN(BM), |
| + MT6359_TOP_GEN(HK), |
| + MT6359_TOP_GEN(AUD), |
| + MT6359_TOP_GEN(MISC), |
| +}; |
| + |
| +static struct pmic_irq_data mt6358_irqd = { |
| + .num_top = ARRAY_SIZE(mt6358_ints), |
| + .num_pmic_irqs = MT6358_IRQ_NR, |
| + .top_int_status_reg = MT6358_TOP_INT_STATUS0, |
| + .pmic_ints = mt6358_ints, |
| +}; |
| + |
| +static struct pmic_irq_data mt6359_irqd = { |
| + .num_top = ARRAY_SIZE(mt6359_ints), |
| + .num_pmic_irqs = MT6359_IRQ_NR, |
| + .top_int_status_reg = MT6359_TOP_INT_STATUS0, |
| + .pmic_ints = mt6359_ints, |
| +}; |
| + |
| static void pmic_irq_enable(struct irq_data *data) |
| { |
| unsigned int hwirq = irqd_to_hwirq(data); |
| @@ -62,15 +91,15 @@ static void pmic_irq_sync_unlock(struct irq_data *data) |
| /* Find out the IRQ group */ |
| top_gp = 0; |
| while ((top_gp + 1) < irqd->num_top && |
| - i >= mt6358_ints[top_gp + 1].hwirq_base) |
| + i >= irqd->pmic_ints[top_gp + 1].hwirq_base) |
| top_gp++; |
| |
| /* Find the IRQ registers */ |
| - gp_offset = i - mt6358_ints[top_gp].hwirq_base; |
| - int_regs = gp_offset / MT6358_REG_WIDTH; |
| - shift = gp_offset % MT6358_REG_WIDTH; |
| - en_reg = mt6358_ints[top_gp].en_reg + |
| - (mt6358_ints[top_gp].en_reg_shift * int_regs); |
| + gp_offset = i - irqd->pmic_ints[top_gp].hwirq_base; |
| + int_regs = gp_offset / MTK_PMIC_REG_WIDTH; |
| + shift = gp_offset % MTK_PMIC_REG_WIDTH; |
| + en_reg = irqd->pmic_ints[top_gp].en_reg + |
| + (irqd->pmic_ints[top_gp].en_reg_shift * int_regs); |
| |
| regmap_update_bits(chip->regmap, en_reg, BIT(shift), |
| irqd->enable_hwirq[i] << shift); |
| @@ -95,10 +124,11 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip, |
| unsigned int irq_status, sta_reg, status; |
| unsigned int hwirq, virq; |
| int i, j, ret; |
| + struct pmic_irq_data *irqd = chip->irq_data; |
| |
| - for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) { |
| - sta_reg = mt6358_ints[top_gp].sta_reg + |
| - mt6358_ints[top_gp].sta_reg_shift * i; |
| + for (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) { |
| + sta_reg = irqd->pmic_ints[top_gp].sta_reg + |
| + irqd->pmic_ints[top_gp].sta_reg_shift * i; |
| |
| ret = regmap_read(chip->regmap, sta_reg, &irq_status); |
| if (ret) { |
| @@ -114,8 +144,8 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip, |
| do { |
| j = __ffs(status); |
| |
| - hwirq = mt6358_ints[top_gp].hwirq_base + |
| - MT6358_REG_WIDTH * i + j; |
| + hwirq = irqd->pmic_ints[top_gp].hwirq_base + |
| + MTK_PMIC_REG_WIDTH * i + j; |
| |
| virq = irq_find_mapping(chip->irq_domain, hwirq); |
| if (virq) |
| @@ -131,12 +161,12 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip, |
| static irqreturn_t mt6358_irq_handler(int irq, void *data) |
| { |
| struct mt6397_chip *chip = data; |
| - struct pmic_irq_data *mt6358_irq_data = chip->irq_data; |
| + struct pmic_irq_data *irqd = chip->irq_data; |
| unsigned int bit, i, top_irq_status = 0; |
| int ret; |
| |
| ret = regmap_read(chip->regmap, |
| - mt6358_irq_data->top_int_status_reg, |
| + irqd->top_int_status_reg, |
| &top_irq_status); |
| if (ret) { |
| dev_err(chip->dev, |
| @@ -144,8 +174,8 @@ static irqreturn_t mt6358_irq_handler(int irq, void *data) |
| return IRQ_NONE; |
| } |
| |
| - for (i = 0; i < mt6358_irq_data->num_top; i++) { |
| - bit = BIT(mt6358_ints[i].top_offset); |
| + for (i = 0; i < irqd->num_top; i++) { |
| + bit = BIT(irqd->pmic_ints[i].top_offset); |
| if (top_irq_status & bit) { |
| mt6358_irq_sp_handler(chip, i); |
| top_irq_status &= ~bit; |
| @@ -180,17 +210,22 @@ int mt6358_irq_init(struct mt6397_chip *chip) |
| int i, j, ret; |
| struct pmic_irq_data *irqd; |
| |
| - irqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL); |
| - if (!irqd) |
| - return -ENOMEM; |
| + switch (chip->chip_id) { |
| + case MT6358_CHIP_ID: |
| + chip->irq_data = &mt6358_irqd; |
| + break; |
| |
| - chip->irq_data = irqd; |
| + case MT6359_CHIP_ID: |
| + chip->irq_data = &mt6359_irqd; |
| + break; |
| |
| - mutex_init(&chip->irqlock); |
| - irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0; |
| - irqd->num_pmic_irqs = MT6358_IRQ_NR; |
| - irqd->num_top = ARRAY_SIZE(mt6358_ints); |
| + default: |
| + dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id); |
| + return -ENODEV; |
| + } |
| |
| + mutex_init(&chip->irqlock); |
| + irqd = chip->irq_data; |
| irqd->enable_hwirq = devm_kcalloc(chip->dev, |
| irqd->num_pmic_irqs, |
| sizeof(*irqd->enable_hwirq), |
| @@ -207,10 +242,10 @@ int mt6358_irq_init(struct mt6397_chip *chip) |
| |
| /* Disable all interrupts for initializing */ |
| for (i = 0; i < irqd->num_top; i++) { |
| - for (j = 0; j < mt6358_ints[i].num_int_regs; j++) |
| + for (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++) |
| regmap_write(chip->regmap, |
| - mt6358_ints[i].en_reg + |
| - mt6358_ints[i].en_reg_shift * j, 0); |
| + irqd->pmic_ints[i].en_reg + |
| + irqd->pmic_ints[i].en_reg_shift * j, 0); |
| } |
| |
| chip->irq_domain = irq_domain_add_linear(chip->dev->of_node, |
| diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c |
| index f6cd8a66060286a7192eb162fd2d3f574f5a43cd..f35f51b4d96712974eab721b6478f5b97fd9d357 100644 |
| --- a/drivers/mfd/mt6397-core.c |
| +++ b/drivers/mfd/mt6397-core.c |
| @@ -13,9 +13,11 @@ |
| #include <linux/mfd/core.h> |
| #include <linux/mfd/mt6323/core.h> |
| #include <linux/mfd/mt6358/core.h> |
| +#include <linux/mfd/mt6359/core.h> |
| #include <linux/mfd/mt6397/core.h> |
| #include <linux/mfd/mt6323/registers.h> |
| #include <linux/mfd/mt6358/registers.h> |
| +#include <linux/mfd/mt6359/registers.h> |
| #include <linux/mfd/mt6397/registers.h> |
| |
| #define MT6323_RTC_BASE 0x8000 |
| @@ -99,6 +101,13 @@ static const struct mfd_cell mt6358_devs[] = { |
| }, |
| }; |
| |
| +static const struct mfd_cell mt6359_devs[] = { |
| + { |
| + .name = "mt6359-regulator", |
| + .of_compatible = "mediatek,mt6359-regulator" |
| + }, |
| +}; |
| + |
| static const struct mfd_cell mt6397_devs[] = { |
| { |
| .name = "mt6397-rtc", |
| @@ -149,6 +158,14 @@ static const struct chip_data mt6358_core = { |
| .irq_init = mt6358_irq_init, |
| }; |
| |
| +static const struct chip_data mt6359_core = { |
| + .cid_addr = MT6359_SWCID, |
| + .cid_shift = 8, |
| + .cells = mt6359_devs, |
| + .cell_size = ARRAY_SIZE(mt6359_devs), |
| + .irq_init = mt6358_irq_init, |
| +}; |
| + |
| static const struct chip_data mt6397_core = { |
| .cid_addr = MT6397_CID, |
| .cid_shift = 0, |
| @@ -218,6 +235,9 @@ static const struct of_device_id mt6397_of_match[] = { |
| }, { |
| .compatible = "mediatek,mt6358", |
| .data = &mt6358_core, |
| + }, { |
| + .compatible = "mediatek,mt6359", |
| + .data = &mt6359_core, |
| }, { |
| .compatible = "mediatek,mt6397", |
| .data = &mt6397_core, |
| diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c |
| old mode 100644 |
| new mode 100755 |
| index 5c6f61ff01928b8145d71ad9162604112c8deea7..f60fadf260c2ff4b58b158a75c619a210a89faa7 |
| --- a/drivers/mmc/host/mtk-sd.c |
| +++ b/drivers/mmc/host/mtk-sd.c |
| @@ -475,6 +475,18 @@ static const struct mtk_mmc_compatible mt8183_compat = { |
| .support_64g = true, |
| }; |
| |
| +static const struct mtk_mmc_compatible mt8192_compat = { |
| + .clk_div_bits = 12, |
| + .recheck_sdio_irq = false, |
| + .hs400_tune = false, |
| + .pad_tune_reg = MSDC_PAD_TUNE0, |
| + .async_fifo = true, |
| + .data_tune = true, |
| + .busy_check = true, |
| + .stop_clk_fix = true, |
| + .enhance_rx = false, |
| + .support_64g = true, |
| +}; |
| static const struct mtk_mmc_compatible mt2701_compat = { |
| .clk_div_bits = 12, |
| .recheck_sdio_irq = false, |
| @@ -542,6 +554,7 @@ static const struct of_device_id msdc_of_ids[] = { |
| { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, |
| { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, |
| { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, |
| + { .compatible = "mediatek,mt8192-mmc", .data = &mt8192_compat}, |
| { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, |
| { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, |
| { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, |
| diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c |
| old mode 100644 |
| new mode 100755 |
| index 626a7c352dfdf8ca5e238ada09a51fab5d3061b4..f66d20c482b0b4a9e9bf00cd05bad02a1b8d3362 |
| --- a/drivers/pci/controller/pcie-mediatek.c |
| +++ b/drivers/pci/controller/pcie-mediatek.c |
| @@ -13,6 +13,7 @@ |
| #include <linux/irq.h> |
| #include <linux/irqchip/chained_irq.h> |
| #include <linux/irqdomain.h> |
| +#include <linux/interrupt.h> |
| #include <linux/kernel.h> |
| #include <linux/msi.h> |
| #include <linux/module.h> |
| @@ -79,6 +80,7 @@ |
| #define PCIE_INT_MASK 0x420 |
| #define INTX_MASK GENMASK(19, 16) |
| #define INTX_SHIFT 16 |
| +#define INTX_NUM 4 |
| #define PCIE_INT_STATUS 0x424 |
| #define MSI_STATUS BIT(23) |
| #define PCIE_IMSI_STATUS 0x42c |
| @@ -137,13 +139,144 @@ |
| #define PCIE_LINK_STATUS_V2 0x804 |
| #define PCIE_PORT_LINKUP_V2 BIT(10) |
| |
| +/* PCIe V3 CfgWr/CfgRd registers */ |
| +#define PCIE_CFGNUM 0x140 |
| +#define CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) |
| +#define CFG_BUS(busno) (((busno) << 8) & GENMASK(15, 8)) |
| +#define CFG_BYTE_EN GENMASK(19, 16) |
| +#define CFG_FORCE_BYTE_EN 0 |
| + |
| +#define CFG_HEADER(devfn, busno) \ |
| + (CFG_DEVFN(devfn) | CFG_BUS(busno) | CFG_BYTE_EN | CFG_FORCE_BYTE_EN) |
| + |
| +/* PCI Interrupt registers */ |
| +#define PCIE_INT_MASK_V3 0x180 |
| +#define MSI_MASK_V3 BIT(8) |
| +#define L2_ENTRY_WAKE_MASK_V3 BIT(23) |
| +#define INTA_MASK_V3 BIT(24) |
| +#define INTB_MASK_V3 BIT(25) |
| +#define INTC_MASK_V3 BIT(26) |
| +#define INTD_MASK_V3 BIT(27) |
| +#define INTX_MASK_V3 (INTA_MASK_V3 | \ |
| + INTB_MASK_V3 | INTC_MASK_V3 | INTD_MASK_V3) |
| +#define MTK_PCIE_INTX_SHIFT_V3 24 |
| +#define LTR_HP_EVENT_MASK_V3 BIT(28) |
| +#define PM_EVENT_MASK_V3 BIT(30) |
| + |
| +#define PCIE_INT_STATUS_V3 0x184 |
| +#define MSI_STATUS_V3 BIT(8) |
| +#define L2_ENTRY_WAKE_STATUS_V3 BIT(23) |
| +#define INTA_STATUS_V3 BIT(24) |
| +#define INTB_STATUS_V3 BIT(25) |
| +#define INTC_STATUS_V3 BIT(26) |
| +#define INTD_STATUS_V3 BIT(27) |
| +#define LTR_HP_EVENT_STATUS_V3 BIT(28) |
| +#define AER_EVENT_STATUS_V3 BIT(29) |
| +#define PM_EVENT_STATUS_V3 BIT(30) |
| + |
| +/* PCI settings */ |
| +#define PCIE_IF_TIMEOUT 0x344 |
| +#define PTX_TIMEOUT_DISABLE BIT(7) |
| +#define PCIE_MISC_CTRL 0x348 |
| +#define PCIE_SETTING 0x80 |
| +#define PCIE_RC_MODE BIT(0) |
| + |
| +/* PCI MAC registers */ |
| +#define PCIE_IDS2 0x9c |
| +#define PCI_CLASS(class) (class << 8) |
| +#define PCIE_IREG_PEX_SPC 0xd4 |
| +#define SLOT_REG_IMPL BIT(12) |
| +#define PCIE_PEX_LINK 0xc8 |
| +#define ASPM_L1_TIMER_RECOUNT BIT(21) |
| +#define PCIE_RST_CTRL_V3 0x148 |
| +#define PCIE_MAC_RSTB_V3 BIT(0) |
| +#define PCIE_PHY_RSTB_V3 BIT(1) |
| +#define PCIE_BRG_RSTB_V3 BIT(2) |
| +#define PCIE_PE_RSTB_V3 BIT(3) |
| + |
| +#define PCIE_ICMD_PM 0x198 |
| +#define Turn_Off_Link BIT(4) |
| + |
| +#define PCIE_LINK_STATUS_V3 0x150 |
| +#define PCIE_PORT_LINKUP_V3 BIT(4) |
| + |
| +#define PCIE_DATA_LINK_STATUS_V3 0x154 |
| +#define PCIE_DATA_LINKUP_V3 BIT(8) |
| + |
| +#define PCIE_INT_STATUS_V3 0x184 |
| +#define MSI_GRP_STATUS(x) BIT(8 + (x)) |
| + |
| +#define PCIE_MSI_GRP_EN 0x190 |
| +#define MSI_GRP_ENABLE(x) BIT(x) |
| + |
| +#define PCIE_MSI_ADDR_GRP(x) (0xC00 + 0x10 * (x)) |
| +#define PCIE_MSI_STATUS_GRP(x) (0xC04 + 0x10 * (x)) |
| +#define PCIE_MSI_ENABLE_GRP(x) (0xC08 + 0x10 * (x)) |
| + |
| +#define MSI_ENABLE 0x190 |
| +#define MSI_VECTOR 0xC00 |
| +#define MSI_VECTOR_MASK (~0x3fff) |
| +#define IMSI_STATUS 0xC04 |
| +#define MSI_INT_MASK 0xC08 |
| +#define MSI_IRQS 32 |
| +#define PCIE_PORT_MSI_BIT 32 |
| +#define MAX_MSI_IRQS (MSI_IRQS + 1) |
| +#define INTX_IRQ_NUM 5 |
| + |
| +#define AXI_SLV0_T0_BASE 0x800 |
| +#define AXI_SLV0_T0_PAR_SRC_LSB (AXI_SLV0_T0_BASE + 0x00) |
| +#define AXI_SLV0_T0_SRC_MSB (AXI_SLV0_T0_BASE + 0x04) |
| +#define AXI_SLV0_T0_TRSL_LSB (AXI_SLV0_T0_BASE + 0x08) |
| +#define AXI_SLV0_T0_TRSL_MSB (AXI_SLV0_T0_BASE + 0x0c) |
| +#define AXI_SLV0_T0_TRSL_PAR (AXI_SLV0_T0_BASE + 0x10) |
| +#define ATR_IMPL BIT(0) |
| + |
| +#define AXI_SLV0_T1_BASE 0x820 |
| +#define AXI_SLV0_T1_PAR_SRC_LSB (AXI_SLV0_T1_BASE + 0x00) |
| +#define AXI_SLV0_T1_SRC_MSB (AXI_SLV0_T1_BASE + 0x04) |
| +#define AXI_SLV0_T1_TRSL_LSB (AXI_SLV0_T1_BASE + 0x08) |
| +#define AXI_SLV0_T1_TRSL_MSB (AXI_SLV0_T1_BASE + 0x0c) |
| +#define AXI_SLV0_T1_TRSL_PAR (AXI_SLV0_T1_BASE + 0x10) |
| + |
| +#define ATR_SIZE(size) ((size & 0x3f) << 1) |
| +#define ATR_SRC_ADDR_L(base) (base & GENMASK(31, 12)) |
| +#define ATR_ID(id) (id & 0xf) |
| +#define ATR_PARAM(param) ((param & 0xfff) << 16) |
| + |
| +#define CFG_OFFSET_ADDR 0x1000 |
| + |
| +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 |
| + |
| struct mtk_pcie_port; |
| |
| +/** |
| + * struct mtk_pcie_irq_info - interrupts related register information |
| + * @int_status: interrupt status register |
| + * @int_mask: interrupt mask register |
| + * @msi_status: MSI status register |
| + * @msi_addr: MSI address register |
| + * @intx_shift: INTx offset bit on interrupt status register |
| + * @msi_mask_bit: MSI mask bit on interrupt mask register |
| + * @intx_mask_bit: INTx mask bit on interrupt mask register |
| + * @enable_msi_group: pointer to MSI group select functions |
| + */ |
| +struct mtk_pcie_irq_info { |
| + u32 int_status; |
| + u32 int_mask; |
| + u32 msi_status; |
| + u32 msi_addr; |
| + int intx_shift; |
| + int msi_mask_bit; |
| + int intx_mask_bit; |
| + void (*enable_msi_group)(struct mtk_pcie_port *port, int group); |
| +}; |
| + |
| /** |
| * struct mtk_pcie_soc - differentiate between host generations |
| * @need_fix_class_id: whether this host's class ID needed to be fixed or not |
| * @need_fix_device_id: whether this host's device ID needed to be fixed or not |
| * @device_id: device ID which this host need to be fixed |
| + * @pm_support: whether the host's MTCMOS will be off when suspend |
| * @ops: pointer to configuration access functions |
| * @startup: pointer to controller setting functions |
| * @setup_irq: pointer to initialize IRQ functions |
| @@ -152,9 +285,11 @@ struct mtk_pcie_soc { |
| bool need_fix_class_id; |
| bool need_fix_device_id; |
| unsigned int device_id; |
| + bool pm_support; |
| struct pci_ops *ops; |
| int (*startup)(struct mtk_pcie_port *port); |
| int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); |
| + struct mtk_pcie_irq_info *irq_info; |
| }; |
| |
| /** |
| @@ -172,6 +307,7 @@ struct mtk_pcie_soc { |
| * @obff_ck: pointer to OBFF functional block operating clock |
| * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock |
| * @phy: pointer to PHY control block |
| + * @lane: lane count |
| * @slot: port slot |
| * @irq: GIC irq |
| * @irq_domain: legacy INTx IRQ domain |
| @@ -192,6 +328,7 @@ struct mtk_pcie_port { |
| struct clk *obff_ck; |
| struct clk *pipe_ck; |
| struct phy *phy; |
| + u32 lane; |
| u32 slot; |
| int irq; |
| struct irq_domain *irq_domain; |
| @@ -206,20 +343,29 @@ struct mtk_pcie_port { |
| * @dev: pointer to PCIe device |
| * @base: IO mapped register base |
| * @free_ck: free-run reference clock |
| + * @io: IO resource |
| + * @pio: PIO resource |
| * @mem: non-prefetchable memory resource |
| + * @busn: bus range |
| + * @offset: IO / Memory offset |
| * @ports: pointer to PCIe port information |
| * @soc: pointer to SoC-dependent operations |
| - * @busnr: root bus number |
| */ |
| struct mtk_pcie { |
| struct device *dev; |
| void __iomem *base; |
| struct clk *free_ck; |
| |
| + struct resource io; |
| + struct resource pio; |
| struct resource mem; |
| + struct resource busn; |
| + struct { |
| + resource_size_t mem; |
| + resource_size_t io; |
| + } offset; |
| struct list_head ports; |
| const struct mtk_pcie_soc *soc; |
| - unsigned int busnr; |
| }; |
| |
| static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) |
| @@ -228,8 +374,10 @@ static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) |
| |
| clk_disable_unprepare(pcie->free_ck); |
| |
| - pm_runtime_put_sync(dev); |
| - pm_runtime_disable(dev); |
| + if (dev->pm_domain) { |
| + pm_runtime_put_sync(dev); |
| + pm_runtime_disable(dev); |
| + } |
| } |
| |
| static void mtk_pcie_port_free(struct mtk_pcie_port *port) |
| @@ -339,20 +487,22 @@ static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, |
| struct mtk_pcie *pcie = bus->sysdata; |
| struct mtk_pcie_port *port; |
| struct pci_dev *dev = NULL; |
| + struct pci_bus *pbus; |
| |
| - /* |
| - * Walk the bus hierarchy to get the devfn value |
| - * of the port in the root bus. |
| - */ |
| - while (bus && bus->number) { |
| - dev = bus->self; |
| - bus = dev->bus; |
| - devfn = dev->devfn; |
| - } |
| - |
| - list_for_each_entry(port, &pcie->ports, list) |
| - if (port->slot == PCI_SLOT(devfn)) |
| + list_for_each_entry(port, &pcie->ports, list) { |
| + if (bus->number == 0 && port->slot == PCI_SLOT(devfn)) { |
| return port; |
| + } else if (bus->number != 0) { |
| + pbus = bus; |
| + do { |
| + dev = pbus->self; |
| + if (port->slot == PCI_SLOT(dev->devfn)) |
| + return port; |
| + |
| + pbus = dev->bus; |
| + } while (dev->bus->number != 0); |
| + } |
| + } |
| |
| return NULL; |
| } |
| @@ -398,10 +548,11 @@ static struct pci_ops mtk_pcie_ops_v2 = { |
| static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
| { |
| struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
| + struct mtk_pcie_irq_info *irq_info = port->pcie->soc->irq_info; |
| phys_addr_t addr; |
| |
| /* MT2712/MT7622 only support 32-bit MSI addresses */ |
| - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); |
| + addr = readl(port->base + irq_info->msi_addr); |
| msg->address_hi = 0; |
| msg->address_lo = lower_32_bits(addr); |
| |
| @@ -414,15 +565,16 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
| static int mtk_msi_set_affinity(struct irq_data *irq_data, |
| const struct cpumask *mask, bool force) |
| { |
| - return -EINVAL; |
| + return -EINVAL; |
| } |
| |
| static void mtk_msi_ack_irq(struct irq_data *data) |
| { |
| struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
| + struct mtk_pcie_irq_info *irq_info = port->pcie->soc->irq_info; |
| u32 hwirq = data->hwirq; |
| |
| - writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); |
| + writel(1 << hwirq, port->base + irq_info->msi_status); |
| } |
| |
| static struct irq_chip mtk_msi_bottom_irq_chip = { |
| @@ -432,8 +584,9 @@ static struct irq_chip mtk_msi_bottom_irq_chip = { |
| .irq_ack = mtk_msi_ack_irq, |
| }; |
| |
| -static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| - unsigned int nr_irqs, void *args) |
| +static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, |
| + unsigned int virq, unsigned int nr_irqs, |
| + void *args) |
| { |
| struct mtk_pcie_port *port = domain->host_data; |
| unsigned long bit; |
| @@ -497,10 +650,11 @@ static struct msi_domain_info mtk_msi_domain_info = { |
| |
| static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) |
| { |
| - struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); |
| + struct fwnode_handle *fwnode; |
| |
| mutex_init(&port->lock); |
| |
| + fwnode = of_node_to_fwnode(port->pcie->dev->of_node); |
| port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, |
| &msi_domain_ops, port); |
| if (!port->inner_domain) { |
| @@ -508,7 +662,8 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) |
| return -ENOMEM; |
| } |
| |
| - port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, |
| + port->msi_domain = pci_msi_create_irq_domain(fwnode, |
| + &mtk_msi_domain_info, |
| port->inner_domain); |
| if (!port->msi_domain) { |
| dev_err(port->pcie->dev, "failed to create MSI domain\n"); |
| @@ -523,20 +678,28 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) |
| { |
| u32 val; |
| phys_addr_t msg_addr; |
| - |
| - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); |
| - val = lower_32_bits(msg_addr); |
| - writel(val, port->base + PCIE_IMSI_ADDR); |
| - |
| - val = readl(port->base + PCIE_INT_MASK); |
| - val &= ~MSI_MASK; |
| - writel(val, port->base + PCIE_INT_MASK); |
| + struct mtk_pcie_irq_info *irq_info = port->pcie->soc->irq_info; |
| + |
| + msg_addr = virt_to_phys(port->base); |
| + val = lower_32_bits(msg_addr) & MSI_VECTOR_MASK; |
| + writel(val, port->base + irq_info->msi_addr); |
| + |
| + if (irq_info->enable_msi_group) { |
| + irq_info->enable_msi_group(port, 0); |
| + } else { |
| + val = readl(port->base + irq_info->int_mask); |
| + val |= irq_info->msi_mask_bit; |
| + writel(val, port->base + irq_info->int_mask); |
| + } |
| } |
| |
| static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) |
| { |
| struct mtk_pcie_port *port, *tmp; |
| |
| + if (list_empty(&pcie->ports)) |
| + return; |
| + |
| list_for_each_entry_safe(port, tmp, &pcie->ports, list) { |
| irq_set_chained_handler_and_data(port->irq, NULL, NULL); |
| |
| @@ -581,9 +744,8 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, |
| return -ENODEV; |
| } |
| |
| - port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, |
| + port->irq_domain = irq_domain_add_linear(pcie_intc_node, INTX_NUM, |
| &intx_domain_ops, port); |
| - of_node_put(pcie_intc_node); |
| if (!port->irq_domain) { |
| dev_err(dev, "failed to get INTx IRQ domain\n"); |
| return -ENODEV; |
| @@ -601,42 +763,83 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, |
| static void mtk_pcie_intr_handler(struct irq_desc *desc) |
| { |
| struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); |
| + struct mtk_pcie_irq_info *irq_info = port->pcie->soc->irq_info; |
| struct irq_chip *irqchip = irq_desc_get_chip(desc); |
| unsigned long status; |
| - u32 virq; |
| - u32 bit = INTX_SHIFT; |
| + u32 virq, val, mask; |
| + u32 bit = irq_info->intx_shift; |
| |
| chained_irq_enter(irqchip, desc); |
| |
| - status = readl(port->base + PCIE_INT_STATUS); |
| - if (status & INTX_MASK) { |
| - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { |
| + val = readl(port->base + irq_info->int_status); |
| + mask = readl(port->base + irq_info->int_mask); |
| + status = val & mask; |
| + |
| + if (status & irq_info->intx_mask_bit) { |
| + for_each_set_bit_from(bit, &status, INTX_NUM + |
| + irq_info->intx_shift) { |
| /* Clear the INTx */ |
| - writel(1 << bit, port->base + PCIE_INT_STATUS); |
| + writel(1 << bit, port->base + irq_info->int_status); |
| virq = irq_find_mapping(port->irq_domain, |
| - bit - INTX_SHIFT); |
| + bit - irq_info->intx_shift); |
| generic_handle_irq(virq); |
| } |
| } |
| |
| if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| - if (status & MSI_STATUS){ |
| + if (status & irq_info->msi_mask_bit) { |
| unsigned long imsi_status; |
| |
| - while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { |
| - for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { |
| - virq = irq_find_mapping(port->inner_domain, bit); |
| + while ((imsi_status = readl(port->base + |
| + irq_info->msi_status))) { |
| + for_each_set_bit(bit, &imsi_status, |
| + MTK_MSI_IRQS_NUM) { |
| + virq = irq_find_mapping( |
| + port->inner_domain, bit); |
| generic_handle_irq(virq); |
| } |
| } |
| /* Clear MSI interrupt status */ |
| - writel(MSI_STATUS, port->base + PCIE_INT_STATUS); |
| + writel(irq_info->msi_mask_bit, port->base + |
| + irq_info->int_status); |
| } |
| } |
| |
| chained_irq_exit(irqchip, desc); |
| } |
| |
| +struct mtk_pcie_irq_info irq_info_v2 = { |
| + .int_status = PCIE_INT_STATUS, |
| + .msi_status = PCIE_IMSI_STATUS, |
| + .msi_addr = PCIE_IMSI_ADDR, |
| + .int_mask = PCIE_INT_MASK, |
| + .intx_shift = INTX_SHIFT, |
| + .intx_mask_bit = INTX_MASK, |
| + .msi_mask_bit = MSI_MASK, |
| +}; |
| + |
| +static void mtk_enable_msi_group(struct mtk_pcie_port *port, int group) |
| +{ |
| + int val; |
| + |
| + writel(MSI_GRP_ENABLE(group), port->base + PCIE_MSI_GRP_EN); |
| + |
| + val = readl(port->base + PCIE_INT_MASK_V3); |
| + writel(MSI_GRP_STATUS(group) | val, port->base + PCIE_INT_MASK_V3); |
| + writel(~0, port->base + PCIE_MSI_ENABLE_GRP(group)); |
| +} |
| + |
| +struct mtk_pcie_irq_info irq_info_v3 = { |
| + .int_status = PCIE_INT_STATUS_V3, |
| + .msi_status = IMSI_STATUS, |
| + .msi_addr = MSI_VECTOR, |
| + .int_mask = PCIE_INT_MASK_V3, |
| + .intx_shift = MTK_PCIE_INTX_SHIFT_V3, |
| + .intx_mask_bit = INTX_MASK_V3, |
| + .msi_mask_bit = MSI_MASK_V3, |
| + .enable_msi_group = mtk_enable_msi_group, |
| +}; |
| + |
| static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, |
| struct device_node *node) |
| { |
| @@ -732,6 +935,92 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) |
| return 0; |
| } |
| |
| +static void __iomem *mtk_pcie_map_bus_v3(struct pci_bus *bus, |
| + unsigned int devfn, int where) |
| +{ |
| + struct mtk_pcie_port *port; |
| + |
| + port = mtk_pcie_find_port(bus, devfn); |
| + if (!port) |
| + return NULL; |
| + |
| + writel(CFG_HEADER(devfn, bus->number), port->base + PCIE_CFGNUM); |
| + |
| + return port->base + CFG_OFFSET_ADDR + where; |
| +} |
| + |
| +static struct pci_ops mtk_pcie_ops_v3 = { |
| + .map_bus = mtk_pcie_map_bus_v3, |
| + .read = pci_generic_config_read, |
| + .write = pci_generic_config_write, |
| +}; |
| + |
| +static int mtk_pcie_startup_port_v3(struct mtk_pcie_port *port) |
| +{ |
| + int size, val, err; |
| + struct resource *mem = &port->pcie->mem; |
| + const struct mtk_pcie_soc *soc = port->pcie->soc; |
| + |
| + /* disable PCIe TX completion timeout */ |
| + val = readl(port->base + PCIE_IF_TIMEOUT); |
| + writel(val | PTX_TIMEOUT_DISABLE, port->base + PCIE_IF_TIMEOUT); |
| + |
| + /* disable hw trapping and set as RC mode */ |
| + writel(BIT(31), port->base + PCIE_MISC_CTRL); |
| + val = readl(port->base + PCIE_SETTING); |
| + writel(val | PCIE_RC_MODE, port->base + PCIE_SETTING); |
| + |
| + /* assert all reset signals */ |
| + val = readl(port->base + PCIE_RST_CTRL_V3); |
| + val |= PCIE_MAC_RSTB_V3 | PCIE_PHY_RSTB_V3 | PCIE_BRG_RSTB_V3| |
| + PCIE_PE_RSTB_V3; |
| + writel(val, port->base + PCIE_RST_CTRL_V3); |
| + usleep_range(500, 1000); |
| + |
| + /* de-assert reset signals*/ |
| + val &= ~(PCIE_MAC_RSTB_V3 | PCIE_PHY_RSTB_V3 | PCIE_BRG_RSTB_V3); |
| + writel(val, port->base + PCIE_RST_CTRL_V3); |
| + |
| + usleep_range(100 * 1000, 120 * 1000); |
| + |
| + /* de-assert pe reset signals*/ |
| + val &= ~PCIE_PE_RSTB_V3; |
| + writel(val, port->base + PCIE_RST_CTRL_V3); |
| + |
| + /* Set up vendor ID and class code */ |
| + if (soc->need_fix_class_id) { |
| + val = readl(port->base + PCIE_IDS2) & 0xff; |
| + writel(val | PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8), |
| + port->base + PCIE_IDS2); |
| + } |
| + |
| + /* 100ms timeout value should be enough for Gen1/2 training */ |
| + err = readl_poll_timeout(port->base + PCIE_DATA_LINK_STATUS_V3, val, |
| + !!(val & PCIE_DATA_LINKUP_V3), 20, |
| + 200 * USEC_PER_MSEC); |
| + if (err) |
| + return -ETIMEDOUT; |
| + |
| + /* set INT mask */ |
| + writel(INTX_MASK_V3, port->base + PCIE_INT_MASK_V3); |
| + |
| + if (IS_ENABLED(CONFIG_PCI_MSI)) |
| + mtk_pcie_enable_msi(port); |
| + |
| + /* Set AHB to PCIe translation windows */ |
| + size = fls(mem->end - mem->start) - 1; |
| + writel(ATR_SRC_ADDR_L(mem->start) | ATR_SIZE(size) | ATR_IMPL, |
| + port->base + AXI_SLV0_T0_PAR_SRC_LSB); |
| + writel(upper_32_bits(mem->start), port->base + AXI_SLV0_T0_SRC_MSB); |
| + |
| + writel(ATR_SRC_ADDR_L(mem->start), port->base + AXI_SLV0_T0_TRSL_LSB); |
| + writel(upper_32_bits(mem->start), port->base + AXI_SLV0_T0_TRSL_MSB); |
| + |
| + writel(ATR_ID(0) | ATR_PARAM(0), port->base + AXI_SLV0_T0_TRSL_PAR); |
| + |
| + return 0; |
| +} |
| + |
| static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, |
| unsigned int devfn, int where) |
| { |
| @@ -815,6 +1104,16 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port) |
| struct device *dev = pcie->dev; |
| int err; |
| |
| + dev_info(dev, "%s %d HACK SPM registers\n", __func__, port->slot); |
| + { |
| + void __iomem *spm = devm_ioremap(dev, 0x10006000, 0x1000); |
| + int val; |
| + val = readl(spm + 0xcc); |
| + dev_info(dev, "%s val=%08x\n", __func__, val); |
| + writel(0x0f800000 | val, spm + 0xcc); |
| + dev_info(dev, "%s val=%08x\n", __func__, readl(spm + 0xcc)); |
| + } |
| + |
| err = clk_prepare_enable(port->sys_ck); |
| if (err) { |
| dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); |
| @@ -851,8 +1150,11 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port) |
| goto err_pipe_clk; |
| } |
| |
| - reset_control_assert(port->reset); |
| - reset_control_deassert(port->reset); |
| + err = reset_control_reset(port->reset); |
| + if (err) { |
| + dev_info(dev, "failed to enable phy software reset\n"); |
| + goto err_phy_rst; |
| + } |
| |
| err = phy_init(port->phy); |
| if (err) { |
| @@ -866,8 +1168,10 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port) |
| goto err_phy_on; |
| } |
| |
| - if (!pcie->soc->startup(port)) |
| + if (!pcie->soc->startup(port)) { |
| + dev_info(dev, "Port%d link up success!\n", port->slot); |
| return; |
| + } |
| |
| dev_info(dev, "Port%d link down\n", port->slot); |
| |
| @@ -888,6 +1192,8 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port) |
| clk_disable_unprepare(port->sys_ck); |
| err_sys_clk: |
| mtk_pcie_port_free(port); |
| +err_phy_rst: |
| + reset_control_put(port->reset); |
| } |
| |
| static int mtk_pcie_parse_port(struct mtk_pcie *pcie, |
| @@ -905,6 +1211,12 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie, |
| if (!port) |
| return -ENOMEM; |
| |
| + err = of_property_read_u32(node, "num-lanes", &port->lane); |
| + if (err) { |
| + pr_notice("missing num-lanes property\n"); |
| + return err; |
| + } |
| + |
| snprintf(name, sizeof(name), "port%d", slot); |
| regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); |
| port->base = devm_ioremap_resource(dev, regs); |
| @@ -916,46 +1228,73 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie, |
| snprintf(name, sizeof(name), "sys_ck%d", slot); |
| port->sys_ck = devm_clk_get(dev, name); |
| if (IS_ERR(port->sys_ck)) { |
| - dev_err(dev, "failed to get sys_ck%d clock\n", slot); |
| - return PTR_ERR(port->sys_ck); |
| + if (PTR_ERR(port->sys_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->sys_ck = NULL; |
| } |
| |
| /* sys_ck might be divided into the following parts in some chips */ |
| snprintf(name, sizeof(name), "ahb_ck%d", slot); |
| - port->ahb_ck = devm_clk_get_optional(dev, name); |
| - if (IS_ERR(port->ahb_ck)) |
| - return PTR_ERR(port->ahb_ck); |
| + port->ahb_ck = devm_clk_get(dev, name); |
| + if (IS_ERR(port->ahb_ck)) { |
| + if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->ahb_ck = NULL; |
| + } |
| |
| snprintf(name, sizeof(name), "axi_ck%d", slot); |
| - port->axi_ck = devm_clk_get_optional(dev, name); |
| - if (IS_ERR(port->axi_ck)) |
| - return PTR_ERR(port->axi_ck); |
| + port->axi_ck = devm_clk_get(dev, name); |
| + if (IS_ERR(port->axi_ck)) { |
| + if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->axi_ck = NULL; |
| + } |
| |
| snprintf(name, sizeof(name), "aux_ck%d", slot); |
| - port->aux_ck = devm_clk_get_optional(dev, name); |
| - if (IS_ERR(port->aux_ck)) |
| - return PTR_ERR(port->aux_ck); |
| + port->aux_ck = devm_clk_get(dev, name); |
| + if (IS_ERR(port->aux_ck)) { |
| + if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->aux_ck = NULL; |
| + } |
| |
| snprintf(name, sizeof(name), "obff_ck%d", slot); |
| - port->obff_ck = devm_clk_get_optional(dev, name); |
| - if (IS_ERR(port->obff_ck)) |
| - return PTR_ERR(port->obff_ck); |
| + port->obff_ck = devm_clk_get(dev, name); |
| + if (IS_ERR(port->obff_ck)) { |
| + if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->obff_ck = NULL; |
| + } |
| |
| snprintf(name, sizeof(name), "pipe_ck%d", slot); |
| - port->pipe_ck = devm_clk_get_optional(dev, name); |
| - if (IS_ERR(port->pipe_ck)) |
| - return PTR_ERR(port->pipe_ck); |
| + port->pipe_ck = devm_clk_get(dev, name); |
| + if (IS_ERR(port->pipe_ck)) { |
| + if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER) |
| + return -EPROBE_DEFER; |
| + |
| + port->pipe_ck = NULL; |
| + } |
| + |
| + port->reset = devm_reset_control_get_optional(dev, "phy_rst"); |
| + if (IS_ERR(port->reset)) { |
| + if (PTR_ERR(port->reset) == -EPROBE_DEFER) { |
| + dev_info(dev, "cannot get phy_rst reset\n"); |
| + return -EPROBE_DEFER; |
| + } |
| |
| - snprintf(name, sizeof(name), "pcie-rst%d", slot); |
| - port->reset = devm_reset_control_get_optional_exclusive(dev, name); |
| - if (PTR_ERR(port->reset) == -EPROBE_DEFER) |
| - return PTR_ERR(port->reset); |
| + port->reset = NULL; |
| + } |
| |
| /* some platforms may use default PHY setting */ |
| snprintf(name, sizeof(name), "pcie-phy%d", slot); |
| port->phy = devm_phy_optional_get(dev, name); |
| if (IS_ERR(port->phy)) |
| - return PTR_ERR(port->phy); |
| + port->phy = NULL; |
| |
| port->slot = slot; |
| port->pcie = pcie; |
| @@ -997,8 +1336,10 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) |
| pcie->free_ck = NULL; |
| } |
| |
| - pm_runtime_enable(dev); |
| - pm_runtime_get_sync(dev); |
| + if (dev->pm_domain) { |
| + pm_runtime_enable(dev); |
| + pm_runtime_get_sync(dev); |
| + } |
| |
| /* enable top level clock */ |
| err = clk_prepare_enable(pcie->free_ck); |
| @@ -1010,8 +1351,10 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) |
| return 0; |
| |
| err_free_ck: |
| - pm_runtime_put_sync(dev); |
| - pm_runtime_disable(dev); |
| + if (dev->pm_domain) { |
| + pm_runtime_put_sync(dev); |
| + pm_runtime_disable(dev); |
| + } |
| |
| return err; |
| } |
| @@ -1020,43 +1363,55 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) |
| { |
| struct device *dev = pcie->dev; |
| struct device_node *node = dev->of_node, *child; |
| + struct of_pci_range_parser parser; |
| + struct of_pci_range range; |
| + struct resource res; |
| struct mtk_pcie_port *port, *tmp; |
| - struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); |
| - struct list_head *windows = &host->windows; |
| - struct resource_entry *win, *tmp_win; |
| - resource_size_t io_base; |
| int err; |
| |
| - err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, |
| - windows, &io_base); |
| - if (err) |
| - return err; |
| + if (of_pci_range_parser_init(&parser, node)) { |
| + pr_notice("missing \"ranges\" property\n"); |
| + return -EINVAL; |
| + } |
| |
| - err = devm_request_pci_bus_resources(dev, windows); |
| - if (err < 0) |
| - return err; |
| + for_each_of_pci_range(&parser, &range) { |
| + err = of_pci_range_to_resource(&range, node, &res); |
| + if (err < 0) |
| + return err; |
| |
| - /* Get the I/O and memory ranges from DT */ |
| - resource_list_for_each_entry_safe(win, tmp_win, windows) { |
| - switch (resource_type(win->res)) { |
| + switch (res.flags & IORESOURCE_TYPE_BITS) { |
| case IORESOURCE_IO: |
| - err = devm_pci_remap_iospace(dev, win->res, io_base); |
| - if (err) { |
| - dev_warn(dev, "error %d: failed to map resource %pR\n", |
| - err, win->res); |
| - resource_list_destroy_entry(win); |
| - } |
| + pcie->offset.io = res.start - range.pci_addr; |
| + |
| + memcpy(&pcie->pio, &res, sizeof(res)); |
| + pcie->pio.name = node->full_name; |
| + |
| + pcie->io.start = range.cpu_addr; |
| + pcie->io.end = range.cpu_addr + range.size - 1; |
| + pcie->io.flags = IORESOURCE_MEM; |
| + pcie->io.name = "I/O"; |
| + |
| + memcpy(&res, &pcie->io, sizeof(res)); |
| break; |
| + |
| case IORESOURCE_MEM: |
| - memcpy(&pcie->mem, win->res, sizeof(*win->res)); |
| + pcie->offset.mem = res.start - range.pci_addr; |
| + |
| + memcpy(&pcie->mem, &res, sizeof(res)); |
| pcie->mem.name = "non-prefetchable"; |
| break; |
| - case IORESOURCE_BUS: |
| - pcie->busnr = win->res->start; |
| - break; |
| } |
| } |
| |
| + err = of_pci_parse_bus_range(node, &pcie->busn); |
| + if (err < 0) { |
| + pr_notice("failed to parse bus ranges property: %d\n", err); |
| + pcie->busn.name = node->name; |
| + pcie->busn.start = 0; |
| + pcie->busn.end = 0xff; |
| + pcie->busn.flags = IORESOURCE_BUS; |
| + } |
| + |
| for_each_available_child_of_node(node, child) { |
| int slot; |
| |
| @@ -1088,6 +1443,54 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) |
| return 0; |
| } |
| |
| +static int mtk_pcie_request_resources(struct mtk_pcie *pcie) |
| +{ |
| + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); |
| + struct list_head *windows = &host->windows; |
| + struct device *dev = pcie->dev; |
| + int err; |
| + |
| + pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io); |
| + pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem); |
| + pci_add_resource(windows, &pcie->busn); |
| + |
| + err = devm_request_pci_bus_resources(dev, windows); |
| + if (err < 0) |
| + return err; |
| + |
| + pci_remap_iospace(&pcie->pio, pcie->io.start); |
| + |
| + return 0; |
| +} |
| + |
| +static int mtk_pcie_register_host(struct pci_host_bridge *host) |
| +{ |
| + struct mtk_pcie *pcie = pci_host_bridge_priv(host); |
| + struct pci_bus *child; |
| + int err; |
| + |
| + host->busnr = pcie->busn.start; |
| + host->dev.parent = pcie->dev; |
| + host->ops = pcie->soc->ops; |
| + host->map_irq = of_irq_parse_and_map_pci; |
| + host->swizzle_irq = pci_common_swizzle; |
| + host->sysdata = pcie; |
| + |
| + err = pci_scan_root_bus_bridge(host); |
| + if (err < 0) |
| + return err; |
| + |
| + pci_bus_size_bridges(host->bus); |
| + pci_bus_assign_resources(host->bus); |
| + |
| + list_for_each_entry(child, &host->bus->children, node) |
| + pcie_bus_configure_settings(child); |
| + |
| + pci_bus_add_devices(host->bus); |
| + |
| + return 0; |
| +} |
| + |
| static int mtk_pcie_probe(struct platform_device *pdev) |
| { |
| struct device *dev = &pdev->dev; |
| @@ -1110,14 +1513,11 @@ static int mtk_pcie_probe(struct platform_device *pdev) |
| if (err) |
| return err; |
| |
| - host->busnr = pcie->busnr; |
| - host->dev.parent = pcie->dev; |
| - host->ops = pcie->soc->ops; |
| - host->map_irq = of_irq_parse_and_map_pci; |
| - host->swizzle_irq = pci_common_swizzle; |
| - host->sysdata = pcie; |
| + err = mtk_pcie_request_resources(pcie); |
| + if (err) |
| + goto put_resources; |
| |
| - err = pci_host_probe(host); |
| + err = mtk_pcie_register_host(host); |
| if (err) |
| goto put_resources; |
| |
| @@ -1136,6 +1536,7 @@ static void mtk_pcie_free_resources(struct mtk_pcie *pcie) |
| struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); |
| struct list_head *windows = &host->windows; |
| |
| + pci_unmap_iospace(&pcie->pio); |
| pci_free_resource_list(windows); |
| } |
| |
| @@ -1148,19 +1549,23 @@ static int mtk_pcie_remove(struct platform_device *pdev) |
| pci_remove_root_bus(host->bus); |
| mtk_pcie_free_resources(pcie); |
| |
| - mtk_pcie_irq_teardown(pcie); |
| + if (IS_ENABLED(CONFIG_PCI_MSI)) |
| + mtk_pcie_irq_teardown(pcie); |
| |
| - mtk_pcie_put_resources(pcie); |
| + if (!list_empty(&pcie->ports)) |
| + mtk_pcie_put_resources(pcie); |
| |
| return 0; |
| } |
| |
| -static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) |
| +#ifdef CONFIG_PM_SLEEP |
| +static int mtk_pcie_suspend_noirq(struct device *dev) |
| { |
| struct mtk_pcie *pcie = dev_get_drvdata(dev); |
| + const struct mtk_pcie_soc *soc = pcie->soc; |
| struct mtk_pcie_port *port; |
| |
| - if (list_empty(&pcie->ports)) |
| + if (!soc->pm_support) |
| return 0; |
| |
| list_for_each_entry(port, &pcie->ports, list) { |
| @@ -1179,25 +1584,42 @@ static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) |
| return 0; |
| } |
| |
| -static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) |
| +static int mtk_pcie_resume_noirq(struct device *dev) |
| { |
| struct mtk_pcie *pcie = dev_get_drvdata(dev); |
| - struct mtk_pcie_port *port, *tmp; |
| + const struct mtk_pcie_soc *soc = pcie->soc; |
| + struct mtk_pcie_port *port; |
| + int ret; |
| |
| - if (list_empty(&pcie->ports)) |
| + if (!soc->pm_support) |
| return 0; |
| |
| - clk_prepare_enable(pcie->free_ck); |
| + list_for_each_entry(port, &pcie->ports, list) { |
| + phy_power_on(port->phy); |
| + clk_prepare_enable(port->sys_ck); |
| + clk_prepare_enable(port->ahb_ck); |
| + |
| + ret = soc->startup(port); |
| + if (ret) { |
| + pr_notice("Port%d link down\n", port->slot); |
| + phy_power_off(port->phy); |
| + clk_disable_unprepare(port->sys_ck); |
| + clk_disable_unprepare(port->ahb_ck); |
| + clk_disable_unprepare(port->pipe_ck); |
| + clk_disable_unprepare(port->obff_ck); |
| + clk_disable_unprepare(port->axi_ck); |
| + clk_disable_unprepare(port->aux_ck); |
| |
| - list_for_each_entry_safe(port, tmp, &pcie->ports, list) |
| - mtk_pcie_enable_port(port); |
| + return ret; |
| + } |
| |
| - /* In case of EP was removed while system suspend. */ |
| - if (list_empty(&pcie->ports)) |
| - clk_disable_unprepare(pcie->free_ck); |
| + if (IS_ENABLED(CONFIG_PCI_MSI)) |
| + mtk_pcie_enable_msi(port); |
| + } |
| |
| return 0; |
| } |
| +#endif |
| |
| static const struct dev_pm_ops mtk_pcie_pm_ops = { |
| SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, |
| @@ -1210,9 +1632,11 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { |
| }; |
| |
| static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { |
| + .pm_support = true, |
| .ops = &mtk_pcie_ops_v2, |
| .startup = mtk_pcie_startup_port_v2, |
| .setup_irq = mtk_pcie_setup_irq, |
| + .irq_info = &irq_info_v2, |
| }; |
| |
| static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { |
| @@ -1220,6 +1644,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { |
| .ops = &mtk_pcie_ops_v2, |
| .startup = mtk_pcie_startup_port_v2, |
| .setup_irq = mtk_pcie_setup_irq, |
| + .irq_info = &irq_info_v2, |
| }; |
| |
| static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { |
| @@ -1229,6 +1654,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { |
| .ops = &mtk_pcie_ops_v2, |
| .startup = mtk_pcie_startup_port_v2, |
| .setup_irq = mtk_pcie_setup_irq, |
| + .irq_info = &irq_info_v2, |
| +}; |
| + |
| +static const struct mtk_pcie_soc mtk_pcie_soc_v3 = { |
| + .need_fix_class_id = false, |
| + .ops = &mtk_pcie_ops_v3, |
| + .startup = mtk_pcie_startup_port_v3, |
| + .setup_irq = mtk_pcie_setup_irq, |
| + .irq_info = &irq_info_v3, |
| }; |
| |
| static const struct of_device_id mtk_pcie_ids[] = { |
| @@ -1237,6 +1671,7 @@ static const struct of_device_id mtk_pcie_ids[] = { |
| { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, |
| { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, |
| { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, |
| + { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_v3 }, |
| {}, |
| }; |
| |
| @@ -1250,5 +1685,6 @@ static struct platform_driver mtk_pcie_driver = { |
| .pm = &mtk_pcie_pm_ops, |
| }, |
| }; |
| + |
| module_platform_driver(mtk_pcie_driver); |
| MODULE_LICENSE("GPL v2"); |
| diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig |
| index 701f9af63f5e2e2125de3e0830f55727031c9091..7465c053546e8f3260e5fabf392c84208e677f44 100644 |
| --- a/drivers/pinctrl/mediatek/Kconfig |
| +++ b/drivers/pinctrl/mediatek/Kconfig |
| @@ -93,6 +93,13 @@ config PINCTRL_MT6797 |
| default ARM64 && ARCH_MEDIATEK |
| select PINCTRL_MTK_PARIS |
| |
| +config PINCTRL_MT6873 |
| + bool "Mediatek MT6873 pin control" |
| + depends on OF |
| + depends on ARM64 || COMPILE_TEST |
| + default ARM64 && ARCH_MEDIATEK |
| + select PINCTRL_MTK_PARIS |
| + |
| config PINCTRL_MT7622 |
| bool "MediaTek MT7622 pin control" |
| depends on OF |
| diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile |
| index a74325abd877a4c3c54736aa6d23e748ba1d75d1..6327031e4d543bcc8cbd33d6ed6c97599cec31cc 100644 |
| --- a/drivers/pinctrl/mediatek/Makefile |
| +++ b/drivers/pinctrl/mediatek/Makefile |
| @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o |
| obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o |
| obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o |
| obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o |
| +obj-$(CONFIG_PINCTRL_MT6873) += pinctrl-mt6873.o |
| obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o |
| obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o |
| obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o |
| diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6873.c b/drivers/pinctrl/mediatek/pinctrl-mt6873.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..a39fa1e5350d6ba04aac7039e1c5b6e5c598d50c |
| --- /dev/null |
| +++ b/drivers/pinctrl/mediatek/pinctrl-mt6873.c |
| @@ -0,0 +1,1413 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +/* |
| + * Copyright (C) 2019 MediaTek Inc. |
| + * Author: Andy Teng <andy.teng@mediatek.com> |
| + * |
| + */ |
| + |
| +#include "pinctrl-mtk-mt6873.h" |
| +#include "pinctrl-paris.h" |
| + |
| +/* MT6873 have multiple bases to program pin configuration listed as the below: |
| + * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000, |
| + * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000, |
| + * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000, |
| + * iocfg_tl:0x11F30000 |
| + * _i_based could be used to indicate what base the pin should be mapped into. |
| + */ |
| + |
| +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ |
| + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ |
| + 32, 0) |
| + |
| +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ |
| + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ |
| + 32, 1) |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_mode_range[] = { |
| + PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4), |
| + PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4), |
| + PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4), |
| + PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4), |
| + PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4), |
| + PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4), |
| + PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4), |
| + PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4), |
| + PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4), |
| + PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4), |
| + PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4), |
| + PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4), |
| + PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4), |
| + PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4), |
| + PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4), |
| + PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4), |
| + PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4), |
| + PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4), |
| + PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4), |
| + PIN_FIELD_BASE(200, 207, 0, 0x0490, 0x10, 0, 4), |
| + PIN_FIELD_BASE(208, 215, 0, 0x04A0, 0x10, 0, 4), |
| + PIN_FIELD_BASE(216, 219, 0, 0x04B0, 0x10, 0, 4), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_dir_range[] = { |
| + PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1), |
| + PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1), |
| + PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(160, 191, 0, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(192, 219, 0, 0x0060, 0x10, 0, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_di_range[] = { |
| + PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1), |
| + PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1), |
| + PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1), |
| + PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1), |
| + PIN_FIELD_BASE(160, 191, 0, 0x0250, 0x10, 0, 1), |
| + PIN_FIELD_BASE(192, 219, 0, 0x0260, 0x10, 0, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_do_range[] = { |
| + PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1), |
| + PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1), |
| + PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1), |
| + PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1), |
| + PIN_FIELD_BASE(160, 191, 0, 0x0150, 0x10, 0, 1), |
| + PIN_FIELD_BASE(192, 219, 0, 0x0160, 0x10, 0, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_smt_range[] = { |
| + PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(4, 4, 4, 0x00f0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(6, 6, 4, 0x00f0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(7, 7, 4, 0x00f0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(8, 8, 4, 0x00f0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(9, 9, 4, 0x00f0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(10, 10, 6, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(16, 16, 8, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(17, 17, 8, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 4, 1), |
| + PIN_FIELD_BASE(19, 19, 7, 0x0100, 0x10, 4, 1), |
| + PIN_FIELD_BASE(20, 20, 7, 0x0100, 0x10, 5, 1), |
| + PIN_FIELD_BASE(21, 21, 7, 0x0100, 0x10, 5, 1), |
| + PIN_FIELD_BASE(22, 22, 2, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(23, 23, 2, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(24, 24, 2, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(27, 27, 3, 0x00a0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(28, 28, 3, 0x00a0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(29, 29, 3, 0x00a0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(30, 30, 3, 0x00a0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(31, 31, 3, 0x00a0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(32, 32, 3, 0x00a0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(33, 33, 3, 0x00a0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(34, 34, 3, 0x00a0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(35, 35, 3, 0x00a0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(36, 36, 2, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(37, 37, 2, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(38, 38, 2, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(39, 39, 2, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(40, 40, 8, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(41, 41, 8, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(42, 42, 8, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(43, 43, 7, 0x0100, 0x10, 4, 1), |
| + PIN_FIELD_BASE(44, 44, 7, 0x0100, 0x10, 4, 1), |
| + PIN_FIELD_BASE(45, 45, 1, 0x00c0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(46, 46, 1, 0x00c0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(47, 47, 1, 0x00c0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(48, 48, 1, 0x00c0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(49, 49, 1, 0x00c0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(50, 50, 1, 0x00c0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(51, 51, 1, 0x00c0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(52, 52, 1, 0x00c0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(53, 53, 1, 0x00c0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(54, 54, 1, 0x00c0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(55, 55, 1, 0x00c0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(56, 56, 1, 0x00c0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(57, 57, 3, 0x00a0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(62, 62, 3, 0x00a0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(63, 63, 3, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 64, 3, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(65, 65, 3, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(66, 66, 3, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(67, 67, 3, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(68, 68, 3, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(69, 69, 3, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(70, 70, 3, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(71, 71, 3, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(72, 72, 3, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(73, 73, 3, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(74, 74, 3, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(75, 75, 3, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(76, 76, 3, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(77, 77, 3, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(82, 82, 3, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(83, 83, 3, 0x00a0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(89, 89, 2, 0x00c0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(90, 90, 2, 0x00c0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(91, 91, 2, 0x00c0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(92, 92, 2, 0x00c0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(93, 93, 2, 0x00c0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(94, 94, 2, 0x00c0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(95, 95, 2, 0x00c0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(96, 96, 2, 0x00c0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(97, 97, 2, 0x00c0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(98, 98, 2, 0x00c0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(101, 101, 2, 0x00c0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(102, 102, 2, 0x00c0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(103, 103, 2, 0x00c0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(104, 104, 2, 0x00c0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(105, 105, 2, 0x00c0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(106, 106, 2, 0x00c0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(107, 107, 2, 0x00c0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(108, 108, 2, 0x00c0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(109, 109, 2, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(110, 110, 2, 0x00c0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(111, 111, 2, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(112, 112, 2, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(113, 113, 2, 0x00c0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(114, 114, 2, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(115, 115, 2, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(116, 116, 2, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(117, 117, 2, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x00f0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x00f0, 0x10, 18, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x00f0, 0x10, 17, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x00f0, 0x10, 23, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x00f0, 0x10, 16, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x00f0, 0x10, 22, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x00f0, 0x10, 15, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x00f0, 0x10, 21, 1), |
| + PIN_FIELD_BASE(126, 126, 4, 0x00f0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(127, 127, 4, 0x00f0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(128, 128, 4, 0x00f0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(129, 129, 4, 0x00f0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(130, 130, 4, 0x00f0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(131, 131, 4, 0x00f0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(132, 132, 4, 0x00f0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(133, 133, 4, 0x00f0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(134, 134, 4, 0x00f0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(135, 135, 4, 0x00f0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(136, 136, 4, 0x00f0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(137, 137, 4, 0x00f0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(138, 138, 4, 0x00f0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x00f0, 0x10, 14, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x00f0, 0x10, 20, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x00f0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x00f0, 0x10, 19, 1), |
| + PIN_FIELD_BASE(143, 143, 1, 0x00c0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(144, 144, 1, 0x00c0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(145, 145, 1, 0x00c0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(146, 146, 1, 0x00c0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(147, 147, 1, 0x00c0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(148, 148, 1, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(149, 149, 1, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(150, 150, 1, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(151, 151, 1, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(152, 152, 7, 0x0100, 0x10, 6, 1), |
| + PIN_FIELD_BASE(153, 153, 7, 0x0100, 0x10, 6, 1), |
| + PIN_FIELD_BASE(154, 154, 7, 0x0100, 0x10, 6, 1), |
| + PIN_FIELD_BASE(155, 155, 7, 0x0100, 0x10, 6, 1), |
| + PIN_FIELD_BASE(156, 156, 7, 0x0100, 0x10, 7, 1), |
| + PIN_FIELD_BASE(157, 157, 7, 0x0100, 0x10, 7, 1), |
| + PIN_FIELD_BASE(158, 158, 7, 0x0100, 0x10, 7, 1), |
| + PIN_FIELD_BASE(159, 159, 7, 0x0100, 0x10, 7, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x0100, 0x10, 12, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x0100, 0x10, 13, 1), |
| + PIN_FIELD_BASE(162, 162, 7, 0x0100, 0x10, 0, 1), |
| + PIN_FIELD_BASE(163, 163, 7, 0x0100, 0x10, 1, 1), |
| + PIN_FIELD_BASE(164, 164, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(165, 165, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(166, 166, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(167, 167, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(168, 168, 7, 0x0100, 0x10, 2, 1), |
| + PIN_FIELD_BASE(169, 169, 7, 0x0100, 0x10, 3, 1), |
| + PIN_FIELD_BASE(170, 170, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(171, 171, 7, 0x0100, 0x10, 8, 1), |
| + PIN_FIELD_BASE(172, 172, 7, 0x0100, 0x10, 9, 1), |
| + PIN_FIELD_BASE(173, 173, 7, 0x0100, 0x10, 10, 1), |
| + PIN_FIELD_BASE(174, 174, 7, 0x0100, 0x10, 9, 1), |
| + PIN_FIELD_BASE(175, 175, 7, 0x0100, 0x10, 10, 1), |
| + PIN_FIELD_BASE(176, 176, 7, 0x0100, 0x10, 9, 1), |
| + PIN_FIELD_BASE(177, 177, 7, 0x0100, 0x10, 9, 1), |
| + PIN_FIELD_BASE(178, 178, 7, 0x0100, 0x10, 10, 1), |
| + PIN_FIELD_BASE(179, 179, 7, 0x0100, 0x10, 10, 1), |
| + PIN_FIELD_BASE(180, 180, 7, 0x0100, 0x10, 11, 1), |
| + PIN_FIELD_BASE(181, 181, 7, 0x0100, 0x10, 11, 1), |
| + PIN_FIELD_BASE(182, 182, 7, 0x0100, 0x10, 11, 1), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0090, 0x10, 1, 1), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0090, 0x10, 2, 1), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0090, 0x10, 4, 1), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0090, 0x10, 6, 1), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0090, 0x10, 8, 1), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0090, 0x10, 3, 1), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0090, 0x10, 7, 1), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0090, 0x10, 9, 1), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0090, 0x10, 10, 1), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0090, 0x10, 0, 1), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0090, 0x10, 5, 1), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0090, 0x10, 11, 1), |
| + PIN_FIELD_BASE(195, 195, 5, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(196, 196, 5, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(197, 197, 5, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(198, 198, 5, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(199, 199, 5, 0x0080, 0x10, 4, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0080, 0x10, 5, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0080, 0x10, 5, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0080, 0x10, 6, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0080, 0x10, 4, 1), |
| + PIN_FIELD_BASE(206, 206, 5, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(207, 207, 5, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(208, 208, 5, 0x0080, 0x10, 7, 1), |
| + PIN_FIELD_BASE(209, 209, 5, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(210, 210, 5, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(211, 211, 5, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(212, 212, 5, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(213, 213, 5, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(214, 214, 5, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(215, 215, 5, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(216, 216, 5, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(217, 217, 5, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(218, 218, 5, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(219, 219, 5, 0x0080, 0x10, 4, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_ies_range[] = { |
| + PIN_FIELD_BASE(0, 0, 4, 0x0070, 0x10, 9, 1), |
| + PIN_FIELD_BASE(1, 1, 4, 0x0070, 0x10, 10, 1), |
| + PIN_FIELD_BASE(2, 2, 4, 0x0070, 0x10, 11, 1), |
| + PIN_FIELD_BASE(3, 3, 4, 0x0070, 0x10, 12, 1), |
| + PIN_FIELD_BASE(4, 4, 4, 0x0070, 0x10, 13, 1), |
| + PIN_FIELD_BASE(5, 5, 4, 0x0070, 0x10, 14, 1), |
| + PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 15, 1), |
| + PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 16, 1), |
| + PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 17, 1), |
| + PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 18, 1), |
| + PIN_FIELD_BASE(10, 10, 6, 0x0010, 0x10, 0, 1), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0010, 0x10, 1, 1), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0010, 0x10, 2, 1), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0010, 0x10, 3, 1), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0010, 0x10, 4, 1), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 5, 1), |
| + PIN_FIELD_BASE(16, 16, 8, 0x0030, 0x10, 2, 1), |
| + PIN_FIELD_BASE(17, 17, 8, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(18, 18, 7, 0x0050, 0x10, 21, 1), |
| + PIN_FIELD_BASE(19, 19, 7, 0x0050, 0x10, 22, 1), |
| + PIN_FIELD_BASE(20, 20, 7, 0x0050, 0x10, 23, 1), |
| + PIN_FIELD_BASE(21, 21, 7, 0x0050, 0x10, 24, 1), |
| + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(26, 26, 3, 0x0040, 0x10, 5, 1), |
| + PIN_FIELD_BASE(27, 27, 3, 0x0040, 0x10, 6, 1), |
| + PIN_FIELD_BASE(28, 28, 3, 0x0040, 0x10, 7, 1), |
| + PIN_FIELD_BASE(29, 29, 3, 0x0040, 0x10, 8, 1), |
| + PIN_FIELD_BASE(30, 30, 3, 0x0040, 0x10, 9, 1), |
| + PIN_FIELD_BASE(31, 31, 3, 0x0030, 0x10, 27, 1), |
| + PIN_FIELD_BASE(32, 32, 3, 0x0030, 0x10, 24, 1), |
| + PIN_FIELD_BASE(33, 33, 3, 0x0030, 0x10, 26, 1), |
| + PIN_FIELD_BASE(34, 34, 3, 0x0030, 0x10, 23, 1), |
| + PIN_FIELD_BASE(35, 35, 3, 0x0030, 0x10, 25, 1), |
| + PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 20, 1), |
| + PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 21, 1), |
| + PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 22, 1), |
| + PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 23, 1), |
| + PIN_FIELD_BASE(40, 40, 8, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(41, 41, 8, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(42, 42, 8, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(43, 43, 7, 0x0050, 0x10, 25, 1), |
| + PIN_FIELD_BASE(44, 44, 7, 0x0050, 0x10, 26, 1), |
| + PIN_FIELD_BASE(45, 45, 1, 0x0030, 0x10, 18, 1), |
| + PIN_FIELD_BASE(46, 46, 1, 0x0030, 0x10, 20, 1), |
| + PIN_FIELD_BASE(47, 47, 1, 0x0030, 0x10, 19, 1), |
| + PIN_FIELD_BASE(48, 48, 1, 0x0030, 0x10, 16, 1), |
| + PIN_FIELD_BASE(49, 49, 1, 0x0030, 0x10, 17, 1), |
| + PIN_FIELD_BASE(50, 50, 1, 0x0030, 0x10, 15, 1), |
| + PIN_FIELD_BASE(51, 51, 1, 0x0030, 0x10, 9, 1), |
| + PIN_FIELD_BASE(52, 52, 1, 0x0030, 0x10, 10, 1), |
| + PIN_FIELD_BASE(53, 53, 1, 0x0030, 0x10, 14, 1), |
| + PIN_FIELD_BASE(54, 54, 1, 0x0030, 0x10, 11, 1), |
| + PIN_FIELD_BASE(55, 55, 1, 0x0030, 0x10, 13, 1), |
| + PIN_FIELD_BASE(56, 56, 1, 0x0030, 0x10, 12, 1), |
| + PIN_FIELD_BASE(57, 57, 3, 0x0040, 0x10, 1, 1), |
| + PIN_FIELD_BASE(58, 58, 3, 0x0040, 0x10, 2, 1), |
| + PIN_FIELD_BASE(59, 59, 3, 0x0040, 0x10, 3, 1), |
| + PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 4, 1), |
| + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 28, 1), |
| + PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 22, 1), |
| + PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 12, 1), |
| + PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 15, 1), |
| + PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 16, 1), |
| + PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 17, 1), |
| + PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 18, 1), |
| + PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 19, 1), |
| + PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 20, 1), |
| + PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 21, 1), |
| + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 2, 1), |
| + PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 6, 1), |
| + PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 7, 1), |
| + PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 8, 1), |
| + PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 9, 1), |
| + PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 10, 1), |
| + PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 11, 1), |
| + PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 13, 1), |
| + PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 14, 1), |
| + PIN_FIELD_BASE(85, 85, 3, 0x0030, 0x10, 31, 1), |
| + PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(87, 87, 3, 0x0030, 0x10, 29, 1), |
| + PIN_FIELD_BASE(88, 88, 3, 0x0030, 0x10, 30, 1), |
| + PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 24, 1), |
| + PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 25, 1), |
| + PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(92, 92, 2, 0x0060, 0x10, 1, 1), |
| + PIN_FIELD_BASE(93, 93, 2, 0x0060, 0x10, 3, 1), |
| + PIN_FIELD_BASE(94, 94, 2, 0x0060, 0x10, 2, 1), |
| + PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 4, 1), |
| + PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 31, 1), |
| + PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 26, 1), |
| + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 0, 1), |
| + PIN_FIELD_BASE(99, 99, 2, 0x0050, 0x10, 27, 1), |
| + PIN_FIELD_BASE(100, 100, 2, 0x0050, 0x10, 28, 1), |
| + PIN_FIELD_BASE(101, 101, 2, 0x0050, 0x10, 29, 1), |
| + PIN_FIELD_BASE(102, 102, 2, 0x0050, 0x10, 30, 1), |
| + PIN_FIELD_BASE(103, 103, 2, 0x0050, 0x10, 18, 1), |
| + PIN_FIELD_BASE(104, 104, 2, 0x0050, 0x10, 17, 1), |
| + PIN_FIELD_BASE(105, 105, 2, 0x0050, 0x10, 19, 1), |
| + PIN_FIELD_BASE(106, 106, 2, 0x0050, 0x10, 16, 1), |
| + PIN_FIELD_BASE(107, 107, 2, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(108, 108, 2, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(109, 109, 2, 0x0050, 0x10, 10, 1), |
| + PIN_FIELD_BASE(110, 110, 2, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(111, 111, 2, 0x0050, 0x10, 9, 1), |
| + PIN_FIELD_BASE(112, 112, 2, 0x0050, 0x10, 11, 1), |
| + PIN_FIELD_BASE(113, 113, 2, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(114, 114, 2, 0x0050, 0x10, 14, 1), |
| + PIN_FIELD_BASE(115, 115, 2, 0x0050, 0x10, 13, 1), |
| + PIN_FIELD_BASE(116, 116, 2, 0x0050, 0x10, 15, 1), |
| + PIN_FIELD_BASE(117, 117, 2, 0x0050, 0x10, 12, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x0070, 0x10, 23, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x0070, 0x10, 29, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x0070, 0x10, 28, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 27, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 26, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(126, 126, 4, 0x0070, 0x10, 19, 1), |
| + PIN_FIELD_BASE(127, 127, 4, 0x0070, 0x10, 20, 1), |
| + PIN_FIELD_BASE(128, 128, 4, 0x0070, 0x10, 21, 1), |
| + PIN_FIELD_BASE(129, 129, 4, 0x0070, 0x10, 22, 1), |
| + PIN_FIELD_BASE(130, 130, 4, 0x0070, 0x10, 6, 1), |
| + PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 7, 1), |
| + PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 8, 1), |
| + PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(134, 134, 4, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(135, 135, 4, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(136, 136, 4, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(137, 137, 4, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(138, 138, 4, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x0070, 0x10, 25, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x0070, 0x10, 31, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x0070, 0x10, 24, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x0070, 0x10, 30, 1), |
| + PIN_FIELD_BASE(143, 143, 1, 0x0030, 0x10, 6, 1), |
| + PIN_FIELD_BASE(144, 144, 1, 0x0030, 0x10, 7, 1), |
| + PIN_FIELD_BASE(145, 145, 1, 0x0030, 0x10, 8, 1), |
| + PIN_FIELD_BASE(146, 146, 1, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(147, 147, 1, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(148, 148, 1, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(149, 149, 1, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(150, 150, 1, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(151, 151, 1, 0x0030, 0x10, 2, 1), |
| + PIN_FIELD_BASE(152, 152, 7, 0x0050, 0x10, 30, 1), |
| + PIN_FIELD_BASE(153, 153, 7, 0x0050, 0x10, 29, 1), |
| + PIN_FIELD_BASE(154, 154, 7, 0x0050, 0x10, 27, 1), |
| + PIN_FIELD_BASE(155, 155, 7, 0x0050, 0x10, 28, 1), |
| + PIN_FIELD_BASE(156, 156, 7, 0x0060, 0x10, 1, 1), |
| + PIN_FIELD_BASE(157, 157, 7, 0x0060, 0x10, 2, 1), |
| + PIN_FIELD_BASE(158, 158, 7, 0x0060, 0x10, 3, 1), |
| + PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 4, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x0050, 0x10, 31, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x0060, 0x10, 0, 1), |
| + PIN_FIELD_BASE(162, 162, 7, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(163, 163, 7, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(164, 164, 7, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(165, 165, 7, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(166, 166, 7, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(167, 167, 7, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(168, 168, 7, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(169, 169, 7, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(170, 170, 7, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(171, 171, 7, 0x0050, 0x10, 9, 1), |
| + PIN_FIELD_BASE(172, 172, 7, 0x0050, 0x10, 13, 1), |
| + PIN_FIELD_BASE(173, 173, 7, 0x0050, 0x10, 14, 1), |
| + PIN_FIELD_BASE(174, 174, 7, 0x0050, 0x10, 12, 1), |
| + PIN_FIELD_BASE(175, 175, 7, 0x0050, 0x10, 15, 1), |
| + PIN_FIELD_BASE(176, 176, 7, 0x0050, 0x10, 10, 1), |
| + PIN_FIELD_BASE(177, 177, 7, 0x0050, 0x10, 11, 1), |
| + PIN_FIELD_BASE(178, 178, 7, 0x0050, 0x10, 16, 1), |
| + PIN_FIELD_BASE(179, 179, 7, 0x0050, 0x10, 17, 1), |
| + PIN_FIELD_BASE(180, 180, 7, 0x0050, 0x10, 18, 1), |
| + PIN_FIELD_BASE(181, 181, 7, 0x0050, 0x10, 19, 1), |
| + PIN_FIELD_BASE(182, 182, 7, 0x0050, 0x10, 20, 1), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0020, 0x10, 1, 1), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0020, 0x10, 2, 1), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0020, 0x10, 4, 1), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0020, 0x10, 6, 1), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0020, 0x10, 8, 1), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0020, 0x10, 3, 1), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0020, 0x10, 7, 1), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0020, 0x10, 9, 1), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0020, 0x10, 10, 1), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0020, 0x10, 0, 1), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0020, 0x10, 5, 1), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0020, 0x10, 11, 1), |
| + PIN_FIELD_BASE(195, 195, 5, 0x0030, 0x10, 16, 1), |
| + PIN_FIELD_BASE(196, 196, 5, 0x0030, 0x10, 6, 1), |
| + PIN_FIELD_BASE(197, 197, 5, 0x0030, 0x10, 8, 1), |
| + PIN_FIELD_BASE(198, 198, 5, 0x0030, 0x10, 7, 1), |
| + PIN_FIELD_BASE(199, 199, 5, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0030, 0x10, 6, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0030, 0x10, 8, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0030, 0x10, 15, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0030, 0x10, 17, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0030, 0x10, 7, 1), |
| + PIN_FIELD_BASE(206, 206, 5, 0x0030, 0x10, 18, 1), |
| + PIN_FIELD_BASE(207, 207, 5, 0x0030, 0x10, 19, 1), |
| + PIN_FIELD_BASE(208, 208, 5, 0x0030, 0x10, 20, 1), |
| + PIN_FIELD_BASE(209, 209, 5, 0x0030, 0x10, 12, 1), |
| + PIN_FIELD_BASE(210, 210, 5, 0x0030, 0x10, 11, 1), |
| + PIN_FIELD_BASE(211, 211, 5, 0x0030, 0x10, 13, 1), |
| + PIN_FIELD_BASE(212, 212, 5, 0x0030, 0x10, 10, 1), |
| + PIN_FIELD_BASE(213, 213, 5, 0x0030, 0x10, 14, 1), |
| + PIN_FIELD_BASE(214, 214, 5, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(215, 215, 5, 0x0030, 0x10, 9, 1), |
| + PIN_FIELD_BASE(216, 216, 5, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(217, 217, 5, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(218, 218, 5, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(219, 219, 5, 0x0030, 0x10, 2, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_pu_range[] = { |
| + PIN_FIELD_BASE(0, 0, 4, 0x00b0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(1, 1, 4, 0x00b0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(2, 2, 4, 0x00b0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(3, 3, 4, 0x00b0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(4, 4, 4, 0x00b0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(5, 5, 4, 0x00b0, 0x10, 14, 1), |
| + PIN_FIELD_BASE(6, 6, 4, 0x00b0, 0x10, 15, 1), |
| + PIN_FIELD_BASE(7, 7, 4, 0x00b0, 0x10, 16, 1), |
| + PIN_FIELD_BASE(8, 8, 4, 0x00b0, 0x10, 17, 1), |
| + PIN_FIELD_BASE(9, 9, 4, 0x00b0, 0x10, 18, 1), |
| + PIN_FIELD_BASE(16, 16, 8, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(17, 17, 8, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(18, 18, 7, 0x00a0, 0x10, 21, 1), |
| + PIN_FIELD_BASE(19, 19, 7, 0x00a0, 0x10, 22, 1), |
| + PIN_FIELD_BASE(20, 20, 7, 0x00a0, 0x10, 23, 1), |
| + PIN_FIELD_BASE(21, 21, 7, 0x00a0, 0x10, 24, 1), |
| + PIN_FIELD_BASE(22, 22, 2, 0x0090, 0x10, 3, 1), |
| + PIN_FIELD_BASE(23, 23, 2, 0x0090, 0x10, 4, 1), |
| + PIN_FIELD_BASE(24, 24, 2, 0x0090, 0x10, 5, 1), |
| + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 6, 1), |
| + PIN_FIELD_BASE(26, 26, 3, 0x0080, 0x10, 5, 1), |
| + PIN_FIELD_BASE(27, 27, 3, 0x0080, 0x10, 6, 1), |
| + PIN_FIELD_BASE(28, 28, 3, 0x0080, 0x10, 7, 1), |
| + PIN_FIELD_BASE(29, 29, 3, 0x0080, 0x10, 8, 1), |
| + PIN_FIELD_BASE(30, 30, 3, 0x0080, 0x10, 9, 1), |
| + PIN_FIELD_BASE(31, 31, 3, 0x0070, 0x10, 27, 1), |
| + PIN_FIELD_BASE(32, 32, 3, 0x0070, 0x10, 24, 1), |
| + PIN_FIELD_BASE(33, 33, 3, 0x0070, 0x10, 26, 1), |
| + PIN_FIELD_BASE(34, 34, 3, 0x0070, 0x10, 23, 1), |
| + PIN_FIELD_BASE(35, 35, 3, 0x0070, 0x10, 25, 1), |
| + PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 20, 1), |
| + PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 21, 1), |
| + PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 22, 1), |
| + PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 23, 1), |
| + PIN_FIELD_BASE(40, 40, 8, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(41, 41, 8, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(42, 42, 8, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 25, 1), |
| + PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 26, 1), |
| + PIN_FIELD_BASE(57, 57, 3, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(58, 58, 3, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(59, 59, 3, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 4, 1), |
| + PIN_FIELD_BASE(61, 61, 3, 0x0070, 0x10, 28, 1), |
| + PIN_FIELD_BASE(62, 62, 3, 0x0070, 0x10, 22, 1), |
| + PIN_FIELD_BASE(63, 63, 3, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 64, 3, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(65, 65, 3, 0x0070, 0x10, 12, 1), |
| + PIN_FIELD_BASE(66, 66, 3, 0x0070, 0x10, 15, 1), |
| + PIN_FIELD_BASE(67, 67, 3, 0x0070, 0x10, 16, 1), |
| + PIN_FIELD_BASE(68, 68, 3, 0x0070, 0x10, 17, 1), |
| + PIN_FIELD_BASE(69, 69, 3, 0x0070, 0x10, 18, 1), |
| + PIN_FIELD_BASE(70, 70, 3, 0x0070, 0x10, 19, 1), |
| + PIN_FIELD_BASE(71, 71, 3, 0x0070, 0x10, 20, 1), |
| + PIN_FIELD_BASE(72, 72, 3, 0x0070, 0x10, 21, 1), |
| + PIN_FIELD_BASE(73, 73, 3, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(74, 74, 3, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(75, 75, 3, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(76, 76, 3, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(77, 77, 3, 0x0070, 0x10, 6, 1), |
| + PIN_FIELD_BASE(78, 78, 3, 0x0070, 0x10, 7, 1), |
| + PIN_FIELD_BASE(79, 79, 3, 0x0070, 0x10, 8, 1), |
| + PIN_FIELD_BASE(80, 80, 3, 0x0070, 0x10, 9, 1), |
| + PIN_FIELD_BASE(81, 81, 3, 0x0070, 0x10, 10, 1), |
| + PIN_FIELD_BASE(82, 82, 3, 0x0070, 0x10, 11, 1), |
| + PIN_FIELD_BASE(83, 83, 3, 0x0070, 0x10, 13, 1), |
| + PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 14, 1), |
| + PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 31, 1), |
| + PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 29, 1), |
| + PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 30, 1), |
| + PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 24, 1), |
| + PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 25, 1), |
| + PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 0, 1), |
| + PIN_FIELD_BASE(92, 92, 2, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(93, 93, 2, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(94, 94, 2, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(95, 95, 2, 0x00a0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 31, 1), |
| + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 26, 1), |
| + PIN_FIELD_BASE(98, 98, 2, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 27, 1), |
| + PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 28, 1), |
| + PIN_FIELD_BASE(101, 101, 2, 0x0090, 0x10, 29, 1), |
| + PIN_FIELD_BASE(102, 102, 2, 0x0090, 0x10, 30, 1), |
| + PIN_FIELD_BASE(103, 103, 2, 0x0090, 0x10, 18, 1), |
| + PIN_FIELD_BASE(104, 104, 2, 0x0090, 0x10, 17, 1), |
| + PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 19, 1), |
| + PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 16, 1), |
| + PIN_FIELD_BASE(107, 107, 2, 0x0090, 0x10, 1, 1), |
| + PIN_FIELD_BASE(108, 108, 2, 0x0090, 0x10, 2, 1), |
| + PIN_FIELD_BASE(109, 109, 2, 0x0090, 0x10, 10, 1), |
| + PIN_FIELD_BASE(110, 110, 2, 0x0090, 0x10, 7, 1), |
| + PIN_FIELD_BASE(111, 111, 2, 0x0090, 0x10, 9, 1), |
| + PIN_FIELD_BASE(112, 112, 2, 0x0090, 0x10, 11, 1), |
| + PIN_FIELD_BASE(113, 113, 2, 0x0090, 0x10, 8, 1), |
| + PIN_FIELD_BASE(114, 114, 2, 0x0090, 0x10, 14, 1), |
| + PIN_FIELD_BASE(115, 115, 2, 0x0090, 0x10, 13, 1), |
| + PIN_FIELD_BASE(116, 116, 2, 0x0090, 0x10, 15, 1), |
| + PIN_FIELD_BASE(117, 117, 2, 0x0090, 0x10, 12, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x00b0, 0x10, 23, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x00b0, 0x10, 29, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x00b0, 0x10, 28, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x00b0, 0x10, 27, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x00b0, 0x10, 26, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(126, 126, 4, 0x00b0, 0x10, 19, 1), |
| + PIN_FIELD_BASE(127, 127, 4, 0x00b0, 0x10, 20, 1), |
| + PIN_FIELD_BASE(128, 128, 4, 0x00b0, 0x10, 21, 1), |
| + PIN_FIELD_BASE(129, 129, 4, 0x00b0, 0x10, 22, 1), |
| + PIN_FIELD_BASE(130, 130, 4, 0x00b0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(131, 131, 4, 0x00b0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(132, 132, 4, 0x00b0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(133, 133, 4, 0x00b0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(134, 134, 4, 0x00b0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(135, 135, 4, 0x00b0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(136, 136, 4, 0x00b0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(137, 137, 4, 0x00b0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(138, 138, 4, 0x00b0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x00b0, 0x10, 25, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x00b0, 0x10, 31, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x00b0, 0x10, 24, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x00b0, 0x10, 30, 1), |
| + PIN_FIELD_BASE(143, 143, 1, 0x0070, 0x10, 6, 1), |
| + PIN_FIELD_BASE(144, 144, 1, 0x0070, 0x10, 7, 1), |
| + PIN_FIELD_BASE(145, 145, 1, 0x0070, 0x10, 8, 1), |
| + PIN_FIELD_BASE(146, 146, 1, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(147, 147, 1, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(148, 148, 1, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(149, 149, 1, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(150, 150, 1, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(151, 151, 1, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(156, 156, 7, 0x00a0, 0x10, 29, 1), |
| + PIN_FIELD_BASE(157, 157, 7, 0x00a0, 0x10, 30, 1), |
| + PIN_FIELD_BASE(158, 158, 7, 0x00a0, 0x10, 31, 1), |
| + PIN_FIELD_BASE(159, 159, 7, 0x00b0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x00a0, 0x10, 27, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x00a0, 0x10, 28, 1), |
| + PIN_FIELD_BASE(162, 162, 7, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(163, 163, 7, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(164, 164, 7, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(165, 165, 7, 0x00a0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(166, 166, 7, 0x00a0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(167, 167, 7, 0x00a0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(168, 168, 7, 0x00a0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(169, 169, 7, 0x00a0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(170, 170, 7, 0x00a0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(171, 171, 7, 0x00a0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(172, 172, 7, 0x00a0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(173, 173, 7, 0x00a0, 0x10, 14, 1), |
| + PIN_FIELD_BASE(174, 174, 7, 0x00a0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(175, 175, 7, 0x00a0, 0x10, 15, 1), |
| + PIN_FIELD_BASE(176, 176, 7, 0x00a0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(177, 177, 7, 0x00a0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(178, 178, 7, 0x00a0, 0x10, 16, 1), |
| + PIN_FIELD_BASE(179, 179, 7, 0x00a0, 0x10, 17, 1), |
| + PIN_FIELD_BASE(180, 180, 7, 0x00a0, 0x10, 18, 1), |
| + PIN_FIELD_BASE(181, 181, 7, 0x00a0, 0x10, 19, 1), |
| + PIN_FIELD_BASE(182, 182, 7, 0x00a0, 0x10, 20, 1), |
| + PIN_FIELD_BASE(195, 195, 5, 0x0050, 0x10, 16, 1), |
| + PIN_FIELD_BASE(196, 196, 5, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(197, 197, 5, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(198, 198, 5, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(199, 199, 5, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0050, 0x10, 15, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0050, 0x10, 17, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(206, 206, 5, 0x0050, 0x10, 18, 1), |
| + PIN_FIELD_BASE(207, 207, 5, 0x0050, 0x10, 19, 1), |
| + PIN_FIELD_BASE(208, 208, 5, 0x0050, 0x10, 20, 1), |
| + PIN_FIELD_BASE(209, 209, 5, 0x0050, 0x10, 12, 1), |
| + PIN_FIELD_BASE(210, 210, 5, 0x0050, 0x10, 11, 1), |
| + PIN_FIELD_BASE(211, 211, 5, 0x0050, 0x10, 13, 1), |
| + PIN_FIELD_BASE(212, 212, 5, 0x0050, 0x10, 10, 1), |
| + PIN_FIELD_BASE(213, 213, 5, 0x0050, 0x10, 14, 1), |
| + PIN_FIELD_BASE(214, 214, 5, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(215, 215, 5, 0x0050, 0x10, 9, 1), |
| + PIN_FIELD_BASE(216, 216, 5, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(217, 217, 5, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(218, 218, 5, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(219, 219, 5, 0x0050, 0x10, 2, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_pd_range[] = { |
| + PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 9, 1), |
| + PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 10, 1), |
| + PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 11, 1), |
| + PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 12, 1), |
| + PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 13, 1), |
| + PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 14, 1), |
| + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 15, 1), |
| + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 16, 1), |
| + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 17, 1), |
| + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 18, 1), |
| + PIN_FIELD_BASE(16, 16, 8, 0x0040, 0x10, 2, 1), |
| + PIN_FIELD_BASE(17, 17, 8, 0x0040, 0x10, 3, 1), |
| + PIN_FIELD_BASE(18, 18, 7, 0x0070, 0x10, 21, 1), |
| + PIN_FIELD_BASE(19, 19, 7, 0x0070, 0x10, 22, 1), |
| + PIN_FIELD_BASE(20, 20, 7, 0x0070, 0x10, 23, 1), |
| + PIN_FIELD_BASE(21, 21, 7, 0x0070, 0x10, 24, 1), |
| + PIN_FIELD_BASE(22, 22, 2, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(23, 23, 2, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(24, 24, 2, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(25, 25, 2, 0x0070, 0x10, 6, 1), |
| + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 5, 1), |
| + PIN_FIELD_BASE(27, 27, 3, 0x0060, 0x10, 6, 1), |
| + PIN_FIELD_BASE(28, 28, 3, 0x0060, 0x10, 7, 1), |
| + PIN_FIELD_BASE(29, 29, 3, 0x0060, 0x10, 8, 1), |
| + PIN_FIELD_BASE(30, 30, 3, 0x0060, 0x10, 9, 1), |
| + PIN_FIELD_BASE(31, 31, 3, 0x0050, 0x10, 27, 1), |
| + PIN_FIELD_BASE(32, 32, 3, 0x0050, 0x10, 24, 1), |
| + PIN_FIELD_BASE(33, 33, 3, 0x0050, 0x10, 26, 1), |
| + PIN_FIELD_BASE(34, 34, 3, 0x0050, 0x10, 23, 1), |
| + PIN_FIELD_BASE(35, 35, 3, 0x0050, 0x10, 25, 1), |
| + PIN_FIELD_BASE(36, 36, 2, 0x0070, 0x10, 20, 1), |
| + PIN_FIELD_BASE(37, 37, 2, 0x0070, 0x10, 21, 1), |
| + PIN_FIELD_BASE(38, 38, 2, 0x0070, 0x10, 22, 1), |
| + PIN_FIELD_BASE(39, 39, 2, 0x0070, 0x10, 23, 1), |
| + PIN_FIELD_BASE(40, 40, 8, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(41, 41, 8, 0x0040, 0x10, 1, 1), |
| + PIN_FIELD_BASE(42, 42, 8, 0x0040, 0x10, 4, 1), |
| + PIN_FIELD_BASE(43, 43, 7, 0x0070, 0x10, 25, 1), |
| + PIN_FIELD_BASE(44, 44, 7, 0x0070, 0x10, 26, 1), |
| + PIN_FIELD_BASE(57, 57, 3, 0x0060, 0x10, 1, 1), |
| + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 2, 1), |
| + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 3, 1), |
| + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 4, 1), |
| + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 28, 1), |
| + PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 22, 1), |
| + PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 12, 1), |
| + PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 15, 1), |
| + PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 16, 1), |
| + PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 17, 1), |
| + PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 18, 1), |
| + PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 19, 1), |
| + PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 20, 1), |
| + PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 21, 1), |
| + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 9, 1), |
| + PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 10, 1), |
| + PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 11, 1), |
| + PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 13, 1), |
| + PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 14, 1), |
| + PIN_FIELD_BASE(85, 85, 3, 0x0050, 0x10, 31, 1), |
| + PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 0, 1), |
| + PIN_FIELD_BASE(87, 87, 3, 0x0050, 0x10, 29, 1), |
| + PIN_FIELD_BASE(88, 88, 3, 0x0050, 0x10, 30, 1), |
| + PIN_FIELD_BASE(89, 89, 2, 0x0070, 0x10, 24, 1), |
| + PIN_FIELD_BASE(90, 90, 2, 0x0070, 0x10, 25, 1), |
| + PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 4, 1), |
| + PIN_FIELD_BASE(94, 94, 2, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(95, 95, 2, 0x0080, 0x10, 5, 1), |
| + PIN_FIELD_BASE(96, 96, 2, 0x0070, 0x10, 31, 1), |
| + PIN_FIELD_BASE(97, 97, 2, 0x0070, 0x10, 26, 1), |
| + PIN_FIELD_BASE(98, 98, 2, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(99, 99, 2, 0x0070, 0x10, 27, 1), |
| + PIN_FIELD_BASE(100, 100, 2, 0x0070, 0x10, 28, 1), |
| + PIN_FIELD_BASE(101, 101, 2, 0x0070, 0x10, 29, 1), |
| + PIN_FIELD_BASE(102, 102, 2, 0x0070, 0x10, 30, 1), |
| + PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 18, 1), |
| + PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 17, 1), |
| + PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 19, 1), |
| + PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 16, 1), |
| + PIN_FIELD_BASE(107, 107, 2, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(108, 108, 2, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(109, 109, 2, 0x0070, 0x10, 10, 1), |
| + PIN_FIELD_BASE(110, 110, 2, 0x0070, 0x10, 7, 1), |
| + PIN_FIELD_BASE(111, 111, 2, 0x0070, 0x10, 9, 1), |
| + PIN_FIELD_BASE(112, 112, 2, 0x0070, 0x10, 11, 1), |
| + PIN_FIELD_BASE(113, 113, 2, 0x0070, 0x10, 8, 1), |
| + PIN_FIELD_BASE(114, 114, 2, 0x0070, 0x10, 14, 1), |
| + PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 13, 1), |
| + PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 15, 1), |
| + PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 12, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x0090, 0x10, 23, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x0090, 0x10, 29, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x0090, 0x10, 28, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x00a0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 27, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x00a0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 26, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x00a0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(126, 126, 4, 0x0090, 0x10, 19, 1), |
| + PIN_FIELD_BASE(127, 127, 4, 0x0090, 0x10, 20, 1), |
| + PIN_FIELD_BASE(128, 128, 4, 0x0090, 0x10, 21, 1), |
| + PIN_FIELD_BASE(129, 129, 4, 0x0090, 0x10, 22, 1), |
| + PIN_FIELD_BASE(130, 130, 4, 0x0090, 0x10, 6, 1), |
| + PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 7, 1), |
| + PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 8, 1), |
| + PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 3, 1), |
| + PIN_FIELD_BASE(134, 134, 4, 0x0090, 0x10, 4, 1), |
| + PIN_FIELD_BASE(135, 135, 4, 0x0090, 0x10, 5, 1), |
| + PIN_FIELD_BASE(136, 136, 4, 0x0090, 0x10, 0, 1), |
| + PIN_FIELD_BASE(137, 137, 4, 0x0090, 0x10, 1, 1), |
| + PIN_FIELD_BASE(138, 138, 4, 0x0090, 0x10, 2, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x0090, 0x10, 25, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x0090, 0x10, 31, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x0090, 0x10, 24, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x0090, 0x10, 30, 1), |
| + PIN_FIELD_BASE(143, 143, 1, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(144, 144, 1, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(145, 145, 1, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(146, 146, 1, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(147, 147, 1, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(148, 148, 1, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(149, 149, 1, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(150, 150, 1, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(151, 151, 1, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(156, 156, 7, 0x0070, 0x10, 29, 1), |
| + PIN_FIELD_BASE(157, 157, 7, 0x0070, 0x10, 30, 1), |
| + PIN_FIELD_BASE(158, 158, 7, 0x0070, 0x10, 31, 1), |
| + PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x0070, 0x10, 27, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x0070, 0x10, 28, 1), |
| + PIN_FIELD_BASE(162, 162, 7, 0x0070, 0x10, 0, 1), |
| + PIN_FIELD_BASE(163, 163, 7, 0x0070, 0x10, 1, 1), |
| + PIN_FIELD_BASE(164, 164, 7, 0x0070, 0x10, 2, 1), |
| + PIN_FIELD_BASE(165, 165, 7, 0x0070, 0x10, 3, 1), |
| + PIN_FIELD_BASE(166, 166, 7, 0x0070, 0x10, 4, 1), |
| + PIN_FIELD_BASE(167, 167, 7, 0x0070, 0x10, 5, 1), |
| + PIN_FIELD_BASE(168, 168, 7, 0x0070, 0x10, 6, 1), |
| + PIN_FIELD_BASE(169, 169, 7, 0x0070, 0x10, 7, 1), |
| + PIN_FIELD_BASE(170, 170, 7, 0x0070, 0x10, 8, 1), |
| + PIN_FIELD_BASE(171, 171, 7, 0x0070, 0x10, 9, 1), |
| + PIN_FIELD_BASE(172, 172, 7, 0x0070, 0x10, 13, 1), |
| + PIN_FIELD_BASE(173, 173, 7, 0x0070, 0x10, 14, 1), |
| + PIN_FIELD_BASE(174, 174, 7, 0x0070, 0x10, 12, 1), |
| + PIN_FIELD_BASE(175, 175, 7, 0x0070, 0x10, 15, 1), |
| + PIN_FIELD_BASE(176, 176, 7, 0x0070, 0x10, 10, 1), |
| + PIN_FIELD_BASE(177, 177, 7, 0x0070, 0x10, 11, 1), |
| + PIN_FIELD_BASE(178, 178, 7, 0x0070, 0x10, 16, 1), |
| + PIN_FIELD_BASE(179, 179, 7, 0x0070, 0x10, 17, 1), |
| + PIN_FIELD_BASE(180, 180, 7, 0x0070, 0x10, 18, 1), |
| + PIN_FIELD_BASE(181, 181, 7, 0x0070, 0x10, 19, 1), |
| + PIN_FIELD_BASE(182, 182, 7, 0x0070, 0x10, 20, 1), |
| + PIN_FIELD_BASE(195, 195, 5, 0x0040, 0x10, 16, 1), |
| + PIN_FIELD_BASE(196, 196, 5, 0x0040, 0x10, 6, 1), |
| + PIN_FIELD_BASE(197, 197, 5, 0x0040, 0x10, 8, 1), |
| + PIN_FIELD_BASE(198, 198, 5, 0x0040, 0x10, 7, 1), |
| + PIN_FIELD_BASE(199, 199, 5, 0x0040, 0x10, 3, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0040, 0x10, 6, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0040, 0x10, 8, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0040, 0x10, 15, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0040, 0x10, 17, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0040, 0x10, 5, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0040, 0x10, 7, 1), |
| + PIN_FIELD_BASE(206, 206, 5, 0x0040, 0x10, 18, 1), |
| + PIN_FIELD_BASE(207, 207, 5, 0x0040, 0x10, 19, 1), |
| + PIN_FIELD_BASE(208, 208, 5, 0x0040, 0x10, 20, 1), |
| + PIN_FIELD_BASE(209, 209, 5, 0x0040, 0x10, 12, 1), |
| + PIN_FIELD_BASE(210, 210, 5, 0x0040, 0x10, 11, 1), |
| + PIN_FIELD_BASE(211, 211, 5, 0x0040, 0x10, 13, 1), |
| + PIN_FIELD_BASE(212, 212, 5, 0x0040, 0x10, 10, 1), |
| + PIN_FIELD_BASE(213, 213, 5, 0x0040, 0x10, 14, 1), |
| + PIN_FIELD_BASE(214, 214, 5, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(215, 215, 5, 0x0040, 0x10, 9, 1), |
| + PIN_FIELD_BASE(216, 216, 5, 0x0040, 0x10, 4, 1), |
| + PIN_FIELD_BASE(217, 217, 5, 0x0040, 0x10, 5, 1), |
| + PIN_FIELD_BASE(218, 218, 5, 0x0040, 0x10, 1, 1), |
| + PIN_FIELD_BASE(219, 219, 5, 0x0040, 0x10, 2, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_drv_range[] = { |
| + PIN_FIELD_BASE(0, 0, 4, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(1, 1, 4, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(2, 2, 4, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(3, 3, 4, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(4, 4, 4, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(5, 5, 4, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(6, 6, 4, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(7, 7, 4, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(8, 8, 4, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(9, 9, 4, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(10, 10, 6, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(16, 16, 8, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(17, 17, 8, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(18, 18, 7, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(19, 19, 7, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(20, 20, 7, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(21, 21, 7, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(22, 22, 2, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(23, 23, 2, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(24, 24, 2, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(25, 25, 2, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(27, 27, 3, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(28, 28, 3, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(29, 29, 3, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(30, 30, 3, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(31, 31, 3, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(32, 32, 3, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(33, 33, 3, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(34, 34, 3, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(35, 35, 3, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(36, 36, 2, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(37, 37, 2, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(38, 38, 2, 0x0010, 0x10, 27, 3), |
| + PIN_FIELD_BASE(39, 39, 2, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(41, 41, 8, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(42, 42, 8, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(43, 43, 7, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(44, 44, 7, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(45, 45, 1, 0x0010, 0x10, 6, 2), |
| + PIN_FIELD_BASE(46, 46, 1, 0x0010, 0x10, 6, 2), |
| + PIN_FIELD_BASE(47, 47, 1, 0x0010, 0x10, 6, 2), |
| + PIN_FIELD_BASE(48, 48, 1, 0x0010, 0x10, 8, 2), |
| + PIN_FIELD_BASE(49, 49, 1, 0x0010, 0x10, 8, 2), |
| + PIN_FIELD_BASE(50, 50, 1, 0x0010, 0x10, 8, 2), |
| + PIN_FIELD_BASE(51, 51, 1, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(52, 52, 1, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(53, 53, 1, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(54, 54, 1, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(55, 55, 1, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(56, 56, 1, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(57, 57, 3, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(58, 58, 3, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(59, 59, 3, 0x0010, 0x10, 27, 3), |
| + PIN_FIELD_BASE(60, 60, 3, 0x0010, 0x10, 27, 3), |
| + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(62, 62, 3, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(63, 63, 3, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(64, 64, 3, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(65, 65, 3, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(66, 66, 3, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(67, 67, 3, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(68, 68, 3, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(69, 69, 3, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(70, 70, 3, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(71, 71, 3, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(72, 72, 3, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(73, 73, 3, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(74, 74, 3, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(75, 75, 3, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(76, 76, 3, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(77, 77, 3, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(78, 78, 3, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(79, 79, 3, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(80, 80, 3, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(82, 82, 3, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(83, 83, 3, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(85, 85, 3, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(86, 86, 3, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(87, 87, 3, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(88, 88, 3, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(89, 89, 2, 0x0020, 0x10, 3, 3), |
| + PIN_FIELD_BASE(90, 90, 2, 0x0020, 0x10, 6, 3), |
| + PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(93, 93, 2, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(95, 95, 2, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 24, 3), |
| + PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 9, 3), |
| + PIN_FIELD_BASE(98, 98, 2, 0x0020, 0x10, 27, 3), |
| + PIN_FIELD_BASE(99, 99, 2, 0x0020, 0x10, 12, 3), |
| + PIN_FIELD_BASE(100, 100, 2, 0x0020, 0x10, 15, 3), |
| + PIN_FIELD_BASE(101, 101, 2, 0x0020, 0x10, 18, 3), |
| + PIN_FIELD_BASE(102, 102, 2, 0x0020, 0x10, 21, 3), |
| + PIN_FIELD_BASE(103, 103, 2, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(104, 104, 2, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(105, 105, 2, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(106, 106, 2, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(107, 107, 2, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(108, 108, 2, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(109, 109, 2, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(110, 110, 2, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(111, 111, 2, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(112, 112, 2, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(113, 113, 2, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(114, 114, 2, 0x0010, 0x10, 15, 3), |
| + PIN_FIELD_BASE(115, 115, 2, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(116, 116, 2, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(117, 117, 2, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(118, 118, 4, 0x0020, 0x10, 3, 3), |
| + PIN_FIELD_BASE(119, 119, 4, 0x0020, 0x10, 21, 3), |
| + PIN_FIELD_BASE(120, 120, 4, 0x0020, 0x10, 18, 3), |
| + PIN_FIELD_BASE(121, 121, 4, 0x0030, 0x10, 6, 3), |
| + PIN_FIELD_BASE(122, 122, 4, 0x0020, 0x10, 15, 3), |
| + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 3, 3), |
| + PIN_FIELD_BASE(124, 124, 4, 0x0020, 0x10, 12, 3), |
| + PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 0, 3), |
| + PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 18, 3), |
| + PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 27, 3), |
| + PIN_FIELD_BASE(130, 130, 4, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(133, 133, 4, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(134, 134, 4, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(135, 135, 4, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(136, 136, 4, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(137, 137, 4, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(138, 138, 4, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(139, 139, 4, 0x0020, 0x10, 9, 3), |
| + PIN_FIELD_BASE(140, 140, 4, 0x0020, 0x10, 27, 3), |
| + PIN_FIELD_BASE(141, 141, 4, 0x0020, 0x10, 6, 3), |
| + PIN_FIELD_BASE(142, 142, 4, 0x0020, 0x10, 24, 3), |
| + PIN_FIELD_BASE(143, 143, 1, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(144, 144, 1, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(145, 145, 1, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(146, 146, 1, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(147, 147, 1, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(148, 148, 1, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(149, 149, 1, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(150, 150, 1, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(151, 151, 1, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(152, 152, 7, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(153, 153, 7, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(155, 155, 7, 0x0010, 0x10, 21, 3), |
| + PIN_FIELD_BASE(156, 156, 7, 0x0020, 0x10, 3, 3), |
| + PIN_FIELD_BASE(157, 157, 7, 0x0020, 0x10, 6, 3), |
| + PIN_FIELD_BASE(158, 158, 7, 0x0020, 0x10, 9, 3), |
| + PIN_FIELD_BASE(159, 159, 7, 0x0020, 0x10, 12, 3), |
| + PIN_FIELD_BASE(160, 160, 7, 0x0010, 0x10, 27, 3), |
| + PIN_FIELD_BASE(161, 161, 7, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(162, 162, 7, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(163, 163, 7, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(164, 164, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(165, 165, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(166, 166, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(167, 167, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(168, 168, 7, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(169, 169, 7, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(170, 170, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(171, 171, 7, 0x0010, 0x10, 24, 3), |
| + PIN_FIELD_BASE(172, 172, 7, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(173, 173, 7, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(174, 174, 7, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(175, 175, 7, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(176, 176, 7, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(177, 177, 7, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(178, 178, 7, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(179, 179, 7, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(180, 180, 7, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(181, 181, 7, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(182, 182, 7, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(195, 195, 5, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(196, 196, 5, 0x0000, 0x10, 18, 3), |
| + PIN_FIELD_BASE(197, 197, 5, 0x0000, 0x10, 24, 3), |
| + PIN_FIELD_BASE(198, 198, 5, 0x0000, 0x10, 21, 3), |
| + PIN_FIELD_BASE(199, 199, 5, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0000, 0x10, 9, 3), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0010, 0x10, 6, 3), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0000, 0x10, 6, 3), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(206, 206, 5, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(207, 207, 5, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(208, 208, 5, 0x0010, 0x10, 12, 3), |
| + PIN_FIELD_BASE(209, 209, 5, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(210, 210, 5, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(211, 211, 5, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(212, 212, 5, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(213, 213, 5, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(214, 214, 5, 0x0000, 0x10, 0, 3), |
| + PIN_FIELD_BASE(215, 215, 5, 0x0000, 0x10, 27, 3), |
| + PIN_FIELD_BASE(216, 216, 5, 0x0000, 0x10, 12, 3), |
| + PIN_FIELD_BASE(217, 217, 5, 0x0000, 0x10, 15, 3), |
| + PIN_FIELD_BASE(218, 218, 5, 0x0000, 0x10, 3, 3), |
| + PIN_FIELD_BASE(219, 219, 5, 0x0000, 0x10, 6, 3), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_pupd_range[] = { |
| + PIN_FIELD_BASE(10, 10, 6, 0x0020, 0x10, 0, 1), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0020, 0x10, 1, 1), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0020, 0x10, 2, 1), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 3, 1), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 4, 1), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 5, 1), |
| + PIN_FIELD_BASE(45, 45, 1, 0x0060, 0x10, 9, 1), |
| + PIN_FIELD_BASE(46, 46, 1, 0x0060, 0x10, 11, 1), |
| + PIN_FIELD_BASE(47, 47, 1, 0x0060, 0x10, 10, 1), |
| + PIN_FIELD_BASE(48, 48, 1, 0x0060, 0x10, 7, 1), |
| + PIN_FIELD_BASE(49, 49, 1, 0x0060, 0x10, 8, 1), |
| + PIN_FIELD_BASE(50, 50, 1, 0x0060, 0x10, 6, 1), |
| + PIN_FIELD_BASE(51, 51, 1, 0x0060, 0x10, 0, 1), |
| + PIN_FIELD_BASE(52, 52, 1, 0x0060, 0x10, 1, 1), |
| + PIN_FIELD_BASE(53, 53, 1, 0x0060, 0x10, 5, 1), |
| + PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1), |
| + PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1), |
| + PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1), |
| + PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1), |
| + PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1), |
| + PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1), |
| + PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0030, 0x10, 6, 1), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0030, 0x10, 8, 1), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0030, 0x10, 7, 1), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0030, 0x10, 9, 1), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0030, 0x10, 10, 1), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_r0_range[] = { |
| + PIN_FIELD_BASE(10, 10, 6, 0x0030, 0x10, 0, 1), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0030, 0x10, 1, 1), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0030, 0x10, 2, 1), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0030, 0x10, 3, 1), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0030, 0x10, 4, 1), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 5, 1), |
| + PIN_FIELD_BASE(45, 45, 1, 0x0080, 0x10, 9, 1), |
| + PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 11, 1), |
| + PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 10, 1), |
| + PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 7, 1), |
| + PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 8, 1), |
| + PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 6, 1), |
| + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 0, 1), |
| + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 1, 1), |
| + PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 5, 1), |
| + PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1), |
| + PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1), |
| + PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1), |
| + PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 6, 1), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 8, 1), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 3, 1), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 7, 1), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 9, 1), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 10, 1), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0030, 0x70, 2, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0030, 0x70, 6, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0030, 0x70, 0, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0030, 0x70, 2, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0020, 0x70, 0, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0020, 0x70, 4, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_r1_range[] = { |
| + PIN_FIELD_BASE(10, 10, 6, 0x0040, 0x10, 0, 1), |
| + PIN_FIELD_BASE(11, 11, 6, 0x0040, 0x10, 1, 1), |
| + PIN_FIELD_BASE(12, 12, 6, 0x0040, 0x10, 2, 1), |
| + PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 3, 1), |
| + PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 4, 1), |
| + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 5, 1), |
| + PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 9, 1), |
| + PIN_FIELD_BASE(46, 46, 1, 0x0090, 0x10, 11, 1), |
| + PIN_FIELD_BASE(47, 47, 1, 0x0090, 0x10, 10, 1), |
| + PIN_FIELD_BASE(48, 48, 1, 0x0090, 0x10, 7, 1), |
| + PIN_FIELD_BASE(49, 49, 1, 0x0090, 0x10, 8, 1), |
| + PIN_FIELD_BASE(50, 50, 1, 0x0090, 0x10, 6, 1), |
| + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 0, 1), |
| + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 1, 1), |
| + PIN_FIELD_BASE(53, 53, 1, 0x0090, 0x10, 5, 1), |
| + PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1), |
| + PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1), |
| + PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1), |
| + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1), |
| + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1), |
| + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1), |
| + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1), |
| + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1), |
| + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1), |
| + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1), |
| + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1), |
| + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1), |
| + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1), |
| + PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1), |
| + PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1), |
| + PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1), |
| + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1), |
| + PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1), |
| + PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1), |
| + PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1), |
| + PIN_FIELD_BASE(186, 186, 9, 0x0050, 0x10, 6, 1), |
| + PIN_FIELD_BASE(187, 187, 9, 0x0050, 0x10, 8, 1), |
| + PIN_FIELD_BASE(188, 188, 9, 0x0050, 0x10, 3, 1), |
| + PIN_FIELD_BASE(189, 189, 9, 0x0050, 0x10, 7, 1), |
| + PIN_FIELD_BASE(190, 190, 9, 0x0050, 0x10, 9, 1), |
| + PIN_FIELD_BASE(191, 191, 9, 0x0050, 0x10, 10, 1), |
| + PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1), |
| + PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1), |
| + PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0030, 0x70, 3, 1), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0030, 0x70, 7, 1), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0030, 0x70, 1, 1), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0030, 0x70, 3, 1), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0020, 0x70, 1, 1), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0020, 0x70, 5, 1), |
| +}; |
| + |
| +static const struct mtk_pin_field_calc mt6873_pin_eh_range[] = { |
| + PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 0, 5), |
| + PIN_FIELD_BASE(90, 90, 2, 0x0040, 0x10, 5, 5), |
| + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 3), |
| + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 3), |
| + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 3), |
| + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 3), |
| + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 3), |
| + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 3), |
| + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 3), |
| + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 3), |
| + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 3), |
| + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 3), |
| + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 3), |
| + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 3), |
| + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 3), |
| + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 3), |
| + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 3), |
| + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 3), |
| + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 3), |
| + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 3), |
| + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 3), |
| + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3), |
| +}; |
| + |
| +static const struct mtk_eh_pin_pinmux mt6873_eh_pin_pinmux_list[] = { |
| + /* pin number, pinmux number */ |
| + {89, 2}, |
| + {90, 2}, |
| + {118, 1}, |
| + {119, 1}, |
| + {120, 1}, |
| + {121, 1}, |
| + {122, 1}, |
| + {123, 1}, |
| + {124, 1}, |
| + {125, 1}, |
| + {139, 1}, |
| + {140, 1}, |
| + {141, 1}, |
| + {142, 1}, |
| + {160, 1}, |
| + {161, 1}, |
| + {200, 1}, |
| + {201, 1}, |
| + {202, 1}, |
| + {203, 1}, |
| + {204, 1}, |
| + {205, 1}, |
| +}; |
| + |
| +static const char * const mt6873_pinctrl_register_base_names[] = { |
| + "iocfg0", "iocfg_rm", "iocfg_bm", "iocfg_bl", "iocfg_br", |
| + "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", "iocfg_tl", |
| +}; |
| + |
| +static const struct mtk_eint_hw mt6873_eint_hw = { |
| + .port_mask = 7, |
| + .ports = 7, |
| + .ap_num = 224, |
| + .db_cnt = 32, |
| +}; |
| + |
| + |
| +static const struct mtk_pin_reg_calc mt6873_reg_cals[PINCTRL_PIN_REG_MAX] = { |
| + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6873_pin_mode_range), |
| + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6873_pin_dir_range), |
| + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6873_pin_di_range), |
| + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6873_pin_do_range), |
| + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6873_pin_dir_range), |
| + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6873_pin_smt_range), |
| + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6873_pin_ies_range), |
| + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6873_pin_pu_range), |
| + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6873_pin_pd_range), |
| + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6873_pin_drv_range), |
| + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6873_pin_pupd_range), |
| + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6873_pin_r0_range), |
| + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6873_pin_r1_range), |
| + [PINCTRL_PIN_REG_DRV_EH] = MTK_RANGE(mt6873_pin_eh_range), |
| +}; |
| + |
| +static const struct mtk_pin_soc mt6873_data = { |
| + .reg_cal = mt6873_reg_cals, |
| + .pins = mtk_pins_mt6873, |
| + .npins = ARRAY_SIZE(mtk_pins_mt6873), |
| + .ngrps = ARRAY_SIZE(mtk_pins_mt6873), |
| + .base_names = mt6873_pinctrl_register_base_names, |
| + .nbase_names = ARRAY_SIZE(mt6873_pinctrl_register_base_names), |
| + .eint_hw = &mt6873_eint_hw, |
| + .nfuncs = 8, |
| + .gpio_m = 0, |
| + .race_free_access = true, |
| + .eh_pin_pinmux = mt6873_eh_pin_pinmux_list, |
| + .neh_pins = ARRAY_SIZE(mt6873_eh_pin_pinmux_list), |
| + .bias_disable_set = mtk_pinconf_bias_disable_set, |
| + .bias_disable_get = mtk_pinconf_bias_disable_get, |
| + .bias_set = mtk_pinconf_bias_set, |
| + .bias_get = mtk_pinconf_bias_get, |
| + .drive_set = mtk_pinconf_drive_set_direct_val, |
| + .drive_get = mtk_pinconf_drive_get_direct_val, |
| + .adv_pull_get = mtk_pinconf_adv_pull_get, |
| + .adv_pull_set = mtk_pinconf_adv_pull_set, |
| +}; |
| + |
| +static const struct of_device_id mt6873_pinctrl_of_match[] = { |
| + { .compatible = "mediatek,mt6873-pinctrl", }, |
| + { } |
| +}; |
| + |
| +static int mt6873_pinctrl_probe(struct platform_device *pdev) |
| +{ |
| + return mtk_paris_pinctrl_probe(pdev, &mt6873_data); |
| +} |
| + |
| +static struct platform_driver mt6873_pinctrl_driver = { |
| + .driver = { |
| + .name = "mt6873-pinctrl", |
| + .of_match_table = mt6873_pinctrl_of_match, |
| + .pm = &mtk_paris_pinctrl_pm_ops, |
| + }, |
| + .probe = mt6873_pinctrl_probe, |
| +}; |
| + |
| +static int __init mt6873_pinctrl_init(void) |
| +{ |
| + return platform_driver_register(&mt6873_pinctrl_driver); |
| +} |
| +arch_initcall(mt6873_pinctrl_init); |
| diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |
| index 20e1c890e73b30cf512a25ec1547fe0fa0708882..4a3a3b3c06f2debd97fc955f11f436cf4b3ceb82 100644 |
| --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |
| +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |
| @@ -16,6 +16,21 @@ |
| #include "mtk-eint.h" |
| #include "pinctrl-mtk-common-v2.h" |
| |
| +/* Some SOC provide more control register other than value register. |
| + * In general, a value register need read-modify-write is at offset 0xXXXXXXXX0. |
| + * A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits |
| + * of SET register will set same bits in value register. |
| + * A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits |
| + * of CLR register will clr same bits in value register. |
| + * For GPIO mode control, MWR register is provided at offset 0xXXXXXXXC. |
| + * With MWR, the MSBit of GPIO mode contrl is for modification-enable, not for |
| + * GPIO mode selection. |
| + */ |
| + |
| +#define SET_OFFSET 0x4 |
| +#define CLR_OFFSET 0x8 |
| +#define MWR_OFFSET 0xC |
| + |
| /** |
| * struct mtk_drive_desc - the structure that holds the information |
| * of the driving current |
| @@ -62,6 +77,37 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) |
| mtk_w32(pctl, i, reg, val); |
| } |
| |
| +static void mtk_hw_set_value_race_free(struct mtk_pinctrl *pctl, |
| + struct mtk_pin_field *pf, u32 value) |
| +{ |
| + unsigned int set, clr; |
| + |
| + set = value & pf->mask; |
| + clr = (~set) & pf->mask; |
| + |
| + if (set) |
| + mtk_w32(pctl, pf->index, pf->offset + SET_OFFSET, |
| + set << pf->bitpos); |
| + if (clr) |
| + mtk_w32(pctl, pf->index, pf->offset + CLR_OFFSET, |
| + clr << pf->bitpos); |
| +} |
| + |
| +static void mtk_hw_set_mode_race_free(struct mtk_pinctrl *pctl, |
| + struct mtk_pin_field *pf, u32 value) |
| +{ |
| + unsigned int value_new; |
| + |
| + /* MSB of mask is modification-enable bit, set this bit */ |
| + value_new = 0x8 | value; |
| + if (value_new == value) |
| + dev_notice(pctl->dev, |
| + "invalid mode 0x%x, use it by ignoring MSBit!\n", |
| + value); |
| + mtk_w32(pctl, pf->index, pf->offset + MWR_OFFSET, |
| + value_new << pf->bitpos); |
| +} |
| + |
| static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, |
| const struct mtk_pin_desc *desc, |
| int field, struct mtk_pin_field *pfd) |
| @@ -182,10 +228,16 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| if (err) |
| return err; |
| |
| - if (!pf.next) |
| - mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, |
| - (value & pf.mask) << pf.bitpos); |
| - else |
| + if (!pf.next) { |
| + if (hw->soc->race_free_access) { |
| + if (field == PINCTRL_PIN_REG_MODE) |
| + mtk_hw_set_mode_race_free(hw, &pf, value); |
| + else |
| + mtk_hw_set_value_race_free(hw, &pf, value); |
| + } else |
| + mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, |
| + (value & pf.mask) << pf.bitpos); |
| + } else |
| mtk_hw_write_cross_field(hw, &pf, value); |
| |
| return 0; |
| @@ -210,6 +262,55 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| return 0; |
| } |
| |
| +/* The eh register determines the selection of the driving control |
| + * of the i2c pins. |
| + * eh = 0: select the normal driving register for non-i2c mode. |
| + * eh = 1: select the special driving register for i2c mode. |
| + */ |
| +int mtk_eh_ctrl(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| + u16 mode) |
| +{ |
| + const struct mtk_eh_pin_pinmux *p = hw->soc->eh_pin_pinmux; |
| + u32 eh_info_num = hw->soc->neh_pins; |
| + u32 val = 0, on = 0, found = 0, i = 0; |
| + int err; |
| + |
| + while (i < eh_info_num) { |
| + if (desc->number == p[i].pin) { |
| + found = 1; |
| + if (mode == p[i].pinmux) { |
| + on = 1; |
| + break; |
| + } |
| + } |
| + /* It is possible that one pin may have more than one pinmux |
| + * that shall enable eh. |
| + * Besides, we assume that hw->soc->eh_pin_pinmux is sorted |
| + * according to field 'pin'. |
| + * So when desc->number < p->pin, it mean no match will be |
| + * found and we can leave. |
| + */ |
| + if (desc->number < p[i].pin) |
| + break; |
| + |
| + i++; |
| + } |
| + |
| + /* If pin not found, just return */ |
| + if (!found) |
| + return 0; |
| + |
| + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, &val); |
| + if (err) |
| + return err; |
| + |
| + if (on) |
| + val |= on; |
| + else |
| + val &= 0xfffffffe; |
| + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, val); |
| +} |
| + |
| static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) |
| { |
| const struct mtk_pin_desc *desc; |
| @@ -226,6 +327,27 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) |
| return EINT_NA; |
| } |
| |
| +bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n) |
| +{ |
| + const struct mtk_pin_desc *desc; |
| + bool virt_gpio = false; |
| + |
| + if (gpio_n >= hw->soc->npins) |
| + return virt_gpio; |
| + |
| + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; |
| + |
| + if (desc->eint.eint_m == EINT_NA) |
| + return virt_gpio; |
| + |
| + if (desc->funcs && |
| + desc->funcs[desc->eint.eint_m].name == 0) |
| + virt_gpio = true; |
| + |
| + return virt_gpio; |
| +} |
| +EXPORT_SYMBOL_GPL(mtk_is_virt_gpio); |
| + |
| static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, |
| unsigned int *gpio_n, |
| struct gpio_chip **gpio_chip) |
| @@ -278,6 +400,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) |
| if (err) |
| return err; |
| |
| + if (mtk_is_virt_gpio(hw, gpio_n)) |
| + return 0; |
| + |
| desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; |
| |
| err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, |
| @@ -285,6 +410,11 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) |
| if (err) |
| return err; |
| |
| + if (hw->soc->eh_pin_pinmux) { |
| + err = mtk_eh_ctrl(hw, desc, desc->eint.eint_m); |
| + if (err) |
| + return err; |
| + } |
| err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); |
| if (err) |
| return err; |
| @@ -593,6 +723,27 @@ int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, |
| return 0; |
| } |
| |
| +/* Revision direct value */ |
| +int mtk_pinconf_drive_set_direct_val(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, u32 arg) |
| +{ |
| + int err; |
| + |
| + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); |
| + |
| + return err; |
| +} |
| + |
| +int mtk_pinconf_drive_get_direct_val(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, int *val) |
| +{ |
| + int err; |
| + |
| + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); |
| + |
| + return err; |
| +} |
| + |
| int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, |
| const struct mtk_pin_desc *desc, bool pullup, |
| u32 arg) |
| @@ -683,6 +834,14 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, |
| int e0 = !!(arg & 2); |
| int e1 = !!(arg & 4); |
| |
| + /* |
| + * Only one will be exist EH table or EN,E0,E1 table |
| + * Check EH table first |
| + */ |
| + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, arg); |
| + if (!err) |
| + return 0; |
| + |
| err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); |
| if (err) |
| return err; |
| @@ -707,6 +866,14 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, |
| u32 en, e0, e1; |
| int err; |
| |
| + /* |
| + * Only one will be exist EH table or EN,E0,E1 table |
| + * Check EH table first |
| + */ |
| + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, val); |
| + if (!err) |
| + return 0; |
| + |
| err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); |
| if (err) |
| return err; |
| diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |
| index 1b7da42aa1d53e4cfd5b7eefadd1f8b2ee13abea..fd269165caff73e5f6b1cd14c458e945bdc50532 100644 |
| --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |
| +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |
| @@ -63,6 +63,7 @@ enum { |
| PINCTRL_PIN_REG_IES, |
| PINCTRL_PIN_REG_PULLEN, |
| PINCTRL_PIN_REG_PULLSEL, |
| + PINCTRL_PIN_REG_DRV_EH, |
| PINCTRL_PIN_REG_DRV_EN, |
| PINCTRL_PIN_REG_DRV_E0, |
| PINCTRL_PIN_REG_DRV_E1, |
| @@ -161,6 +162,17 @@ struct mtk_eint_desc { |
| u16 eint_n; |
| }; |
| |
| +/** |
| + * struct mtk_eh_pin_pinmux - entry recording (pin, pinmux) whose |
| + * eh can be enabled |
| + * @pin: pin numbereint mux for this pin |
| + * @pinmux: pinmux number |
| + */ |
| +struct mtk_eh_pin_pinmux { |
| + u16 pin; |
| + u16 pinmux; |
| +}; |
| + |
| /** |
| * struct mtk_pin_desc - the structure that providing information |
| * for each pin of chips |
| @@ -203,8 +215,11 @@ struct mtk_pin_soc { |
| /* Specific parameters per SoC */ |
| u8 gpio_m; |
| bool ies_present; |
| + bool race_free_access; |
| const char * const *base_names; |
| unsigned int nbase_names; |
| + const struct mtk_eh_pin_pinmux *eh_pin_pinmux; |
| + unsigned int neh_pins; |
| |
| /* Specific pinconfig operations */ |
| int (*bias_disable_set)(struct mtk_pinctrl *hw, |
| @@ -255,6 +270,9 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| int field, int *value); |
| |
| +int mtk_eh_ctrl(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, |
| + u16 mode); |
| + |
| int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev); |
| |
| int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, |
| @@ -288,6 +306,11 @@ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, |
| int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, |
| const struct mtk_pin_desc *desc, int *val); |
| |
| +int mtk_pinconf_drive_set_direct_val(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, u32 arg); |
| +int mtk_pinconf_drive_get_direct_val(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, int *val); |
| + |
| int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, |
| const struct mtk_pin_desc *desc, bool pullup, |
| u32 arg); |
| @@ -299,4 +322,13 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, |
| int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, |
| const struct mtk_pin_desc *desc, u32 *val); |
| |
| +int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, |
| + u32 pullup, u32 enable); |
| + |
| +int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, |
| + const struct mtk_pin_desc *desc, |
| + u32 *pullup, u32 *enable); |
| + |
| +bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n); |
| #endif /* __PINCTRL_MTK_COMMON_V2_H */ |
| diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6873.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6873.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..0278cdb3792b45ad0c58ad28c1c389ddc6253aa3 |
| --- /dev/null |
| +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6873.h |
| @@ -0,0 +1,2276 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (C) 2019 MediaTek Inc. |
| + * Author: Andy Teng <andy.teng@mediatek.com> |
| + * |
| + */ |
| + |
| +#ifndef __PINCTRL_MTK_MT6873_H |
| +#define __PINCTRL_MTK_MT6873_H |
| + |
| +#include "pinctrl-paris.h" |
| + |
| +static const struct mtk_pin_desc mtk_pins_mt6873[] = { |
| + MTK_PIN( |
| + 0, "GPIO0", |
| + MTK_EINT_FUNCTION(0, 0), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO0"), |
| + MTK_FUNCTION(1, "SPI6_CLK"), |
| + MTK_FUNCTION(2, "I2S5_MCK"), |
| + MTK_FUNCTION(3, "PWM_0"), |
| + MTK_FUNCTION(4, "TDM_LRCK"), |
| + MTK_FUNCTION(5, "TP_GPIO0_AO"), |
| + MTK_FUNCTION(6, "MD_INT0") |
| + ), |
| + MTK_PIN( |
| + 1, "GPIO1", |
| + MTK_EINT_FUNCTION(0, 1), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO1"), |
| + MTK_FUNCTION(1, "SPI6_CSB"), |
| + MTK_FUNCTION(2, "I2S5_BCK"), |
| + MTK_FUNCTION(3, "PWM_1"), |
| + MTK_FUNCTION(4, "TDM_BCK"), |
| + MTK_FUNCTION(5, "TP_GPIO1_AO"), |
| + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), |
| + MTK_FUNCTION(7, "DBG_MON_A9") |
| + ), |
| + MTK_PIN( |
| + 2, "GPIO2", |
| + MTK_EINT_FUNCTION(0, 2), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO2"), |
| + MTK_FUNCTION(1, "SPI6_MI"), |
| + MTK_FUNCTION(2, "I2S5_LRCK"), |
| + MTK_FUNCTION(3, "PWM_2"), |
| + MTK_FUNCTION(4, "TDM_MCK"), |
| + MTK_FUNCTION(5, "TP_GPIO2_AO"), |
| + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), |
| + MTK_FUNCTION(7, "DBG_MON_A10") |
| + ), |
| + MTK_PIN( |
| + 3, "GPIO3", |
| + MTK_EINT_FUNCTION(0, 3), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO3"), |
| + MTK_FUNCTION(1, "SPI6_MO"), |
| + MTK_FUNCTION(2, "I2S5_DO"), |
| + MTK_FUNCTION(3, "PWM_3"), |
| + MTK_FUNCTION(4, "TDM_DATA0"), |
| + MTK_FUNCTION(5, "TP_GPIO3_AO"), |
| + MTK_FUNCTION(6, "CLKM0"), |
| + MTK_FUNCTION(7, "DBG_MON_A11") |
| + ), |
| + MTK_PIN( |
| + 4, "GPIO4", |
| + MTK_EINT_FUNCTION(0, 4), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO4"), |
| + MTK_FUNCTION(1, "SPI4_A_CLK"), |
| + MTK_FUNCTION(2, "I2S2_MCK"), |
| + MTK_FUNCTION(3, "DMIC1_CLK"), |
| + MTK_FUNCTION(4, "TDM_DATA1"), |
| + MTK_FUNCTION(5, "TP_GPIO4_AO"), |
| + MTK_FUNCTION(6, "PCM1_DI"), |
| + MTK_FUNCTION(7, "IDDIG") |
| + ), |
| + MTK_PIN( |
| + 5, "GPIO5", |
| + MTK_EINT_FUNCTION(0, 5), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO5"), |
| + MTK_FUNCTION(1, "SPI4_A_CSB"), |
| + MTK_FUNCTION(2, "I2S2_BCK"), |
| + MTK_FUNCTION(3, "DMIC1_DAT"), |
| + MTK_FUNCTION(4, "TDM_DATA2"), |
| + MTK_FUNCTION(5, "TP_GPIO5_AO"), |
| + MTK_FUNCTION(6, "PCM1_CLK"), |
| + MTK_FUNCTION(7, "USB_DRVVBUS") |
| + ), |
| + MTK_PIN( |
| + 6, "GPIO6", |
| + MTK_EINT_FUNCTION(0, 6), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO6"), |
| + MTK_FUNCTION(1, "SPI4_A_MI"), |
| + MTK_FUNCTION(2, "I2S2_LRCK"), |
| + MTK_FUNCTION(3, "DMIC_CLK"), |
| + MTK_FUNCTION(4, "TDM_DATA3"), |
| + MTK_FUNCTION(5, "TP_GPIO6_AO"), |
| + MTK_FUNCTION(6, "PCM1_SYNC") |
| + ), |
| + MTK_PIN( |
| + 7, "GPIO7", |
| + MTK_EINT_FUNCTION(0, 7), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO7"), |
| + MTK_FUNCTION(1, "SPI4_A_MO"), |
| + MTK_FUNCTION(2, "I2S2_DI"), |
| + MTK_FUNCTION(3, "DMIC_DAT"), |
| + MTK_FUNCTION(4, "WIFI_TXD"), |
| + MTK_FUNCTION(5, "TP_GPIO7_AO"), |
| + MTK_FUNCTION(6, "PCM1_DO0") |
| + ), |
| + MTK_PIN( |
| + 8, "GPIO8", |
| + MTK_EINT_FUNCTION(0, 8), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO8"), |
| + MTK_FUNCTION(1, "SRCLKENAI1"), |
| + MTK_FUNCTION(2, "I2S2_DI2"), |
| + MTK_FUNCTION(3, "KPCOL2"), |
| + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), |
| + MTK_FUNCTION(5, "CLKM1"), |
| + MTK_FUNCTION(6, "PCM1_DO1"), |
| + MTK_FUNCTION(7, "DBG_MON_A12") |
| + ), |
| + MTK_PIN( |
| + 9, "GPIO9", |
| + MTK_EINT_FUNCTION(0, 9), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO9"), |
| + MTK_FUNCTION(1, "SRCLKENAI0"), |
| + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), |
| + MTK_FUNCTION(3, "KPROW2"), |
| + MTK_FUNCTION(4, "CMMCLK4"), |
| + MTK_FUNCTION(5, "CLKM3"), |
| + MTK_FUNCTION(6, "PCM1_DO2"), |
| + MTK_FUNCTION(7, "DBG_MON_A13") |
| + ), |
| + MTK_PIN( |
| + 10, "GPIO10", |
| + MTK_EINT_FUNCTION(0, 10), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO10"), |
| + MTK_FUNCTION(1, "MSDC2_CLK"), |
| + MTK_FUNCTION(2, "SPI4_B_CLK"), |
| + MTK_FUNCTION(3, "I2S8_MCK"), |
| + MTK_FUNCTION(5, "MD_INT0"), |
| + MTK_FUNCTION(6, "TP_GPIO8_AO") |
| + ), |
| + MTK_PIN( |
| + 11, "GPIO11", |
| + MTK_EINT_FUNCTION(0, 11), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO11"), |
| + MTK_FUNCTION(1, "MSDC2_CMD"), |
| + MTK_FUNCTION(2, "SPI4_B_CSB"), |
| + MTK_FUNCTION(3, "I2S8_BCK"), |
| + MTK_FUNCTION(4, "PCIE_CLKREQ_N"), |
| + MTK_FUNCTION(5, "MD_INT1_C2K_UIM0_HOT_PLUG"), |
| + MTK_FUNCTION(6, "TP_GPIO9_AO") |
| + ), |
| + MTK_PIN( |
| + 12, "GPIO12", |
| + MTK_EINT_FUNCTION(0, 12), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO12"), |
| + MTK_FUNCTION(1, "MSDC2_DAT3"), |
| + MTK_FUNCTION(2, "SPI4_B_MI"), |
| + MTK_FUNCTION(3, "I2S8_LRCK"), |
| + MTK_FUNCTION(4, "DMIC1_CLK"), |
| + MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"), |
| + MTK_FUNCTION(6, "TP_GPIO10_AO") |
| + ), |
| + MTK_PIN( |
| + 13, "GPIO13", |
| + MTK_EINT_FUNCTION(0, 13), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO13"), |
| + MTK_FUNCTION(1, "MSDC2_DAT0"), |
| + MTK_FUNCTION(2, "SPI4_B_MO"), |
| + MTK_FUNCTION(3, "I2S8_DI"), |
| + MTK_FUNCTION(4, "DMIC1_DAT"), |
| + MTK_FUNCTION(5, "ANT_SEL10"), |
| + MTK_FUNCTION(6, "TP_GPIO11_AO") |
| + ), |
| + MTK_PIN( |
| + 14, "GPIO14", |
| + MTK_EINT_FUNCTION(0, 14), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO14"), |
| + MTK_FUNCTION(1, "MSDC2_DAT2"), |
| + MTK_FUNCTION(2, "IDDIG"), |
| + MTK_FUNCTION(3, "SCL_6306"), |
| + MTK_FUNCTION(4, "PCIE_PERESET_N"), |
| + MTK_FUNCTION(5, "ANT_SEL11"), |
| + MTK_FUNCTION(6, "TP_GPIO12_AO") |
| + ), |
| + MTK_PIN( |
| + 15, "GPIO15", |
| + MTK_EINT_FUNCTION(0, 15), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO15"), |
| + MTK_FUNCTION(1, "MSDC2_DAT1"), |
| + MTK_FUNCTION(2, "USB_DRVVBUS"), |
| + MTK_FUNCTION(3, "SDA_6306"), |
| + MTK_FUNCTION(4, "PCIE_WAKE_N"), |
| + MTK_FUNCTION(5, "ANT_SEL12"), |
| + MTK_FUNCTION(6, "TP_GPIO13_AO") |
| + ), |
| + MTK_PIN( |
| + 16, "GPIO16", |
| + MTK_EINT_FUNCTION(0, 16), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO16"), |
| + MTK_FUNCTION(1, "SRCLKENAI1"), |
| + MTK_FUNCTION(2, "IDDIG"), |
| + MTK_FUNCTION(3, "TP_GPIO14_AO"), |
| + MTK_FUNCTION(4, "KPCOL2"), |
| + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(6, "SPI7_A_MI"), |
| + MTK_FUNCTION(7, "DBG_MON_A0") |
| + ), |
| + MTK_PIN( |
| + 17, "GPIO17", |
| + MTK_EINT_FUNCTION(0, 17), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO17"), |
| + MTK_FUNCTION(1, "SRCLKENAI0"), |
| + MTK_FUNCTION(2, "USB_DRVVBUS"), |
| + MTK_FUNCTION(3, "TP_GPIO15_AO"), |
| + MTK_FUNCTION(4, "KPROW2"), |
| + MTK_FUNCTION(6, "SPI7_A_MO"), |
| + MTK_FUNCTION(7, "DBG_MON_A1") |
| + ), |
| + MTK_PIN( |
| + 18, "GPIO18", |
| + MTK_EINT_FUNCTION(0, 18), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO18"), |
| + MTK_FUNCTION(1, "SRCLKENAI0"), |
| + MTK_FUNCTION(2, "SPI4_C_MI"), |
| + MTK_FUNCTION(3, "SPI1_B_MI"), |
| + MTK_FUNCTION(4, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(5, "ANT_SEL10"), |
| + MTK_FUNCTION(6, "MD_INT0"), |
| + MTK_FUNCTION(7, "DBG_MON_B2") |
| + ), |
| + MTK_PIN( |
| + 19, "GPIO19", |
| + MTK_EINT_FUNCTION(0, 19), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO19"), |
| + MTK_FUNCTION(1, "SRCLKENAI1"), |
| + MTK_FUNCTION(2, "SPI4_C_MO"), |
| + MTK_FUNCTION(3, "SPI1_B_MO"), |
| + MTK_FUNCTION(5, "ANT_SEL11"), |
| + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), |
| + MTK_FUNCTION(7, "DBG_MON_B3") |
| + ), |
| + MTK_PIN( |
| + 20, "GPIO20", |
| + MTK_EINT_FUNCTION(0, 20), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO20"), |
| + MTK_FUNCTION(1, "SRCLKENAI0"), |
| + MTK_FUNCTION(2, "SPI4_C_CLK"), |
| + MTK_FUNCTION(3, "SPI1_B_CLK"), |
| + MTK_FUNCTION(4, "PWM_3"), |
| + MTK_FUNCTION(5, "ANT_SEL12"), |
| + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), |
| + MTK_FUNCTION(7, "DBG_MON_B4") |
| + ), |
| + MTK_PIN( |
| + 21, "GPIO21", |
| + MTK_EINT_FUNCTION(0, 21), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO21"), |
| + MTK_FUNCTION(2, "SPI4_C_CSB"), |
| + MTK_FUNCTION(3, "SPI1_B_CSB"), |
| + MTK_FUNCTION(6, "IDDIG"), |
| + MTK_FUNCTION(7, "DBG_MON_B5") |
| + ), |
| + MTK_PIN( |
| + 22, "GPIO22", |
| + MTK_EINT_FUNCTION(0, 22), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO22"), |
| + MTK_FUNCTION(2, "SPI0_C_CLK"), |
| + MTK_FUNCTION(3, "SPI7_B_CLK"), |
| + MTK_FUNCTION(4, "I2S7_BCK"), |
| + MTK_FUNCTION(5, "I2S9_BCK"), |
| + MTK_FUNCTION(6, "SCL_6306") |
| + ), |
| + MTK_PIN( |
| + 23, "GPIO23", |
| + MTK_EINT_FUNCTION(0, 23), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO23"), |
| + MTK_FUNCTION(2, "SPI0_C_CSB"), |
| + MTK_FUNCTION(3, "SPI7_B_CSB"), |
| + MTK_FUNCTION(4, "I2S7_LRCK"), |
| + MTK_FUNCTION(5, "I2S9_LRCK"), |
| + MTK_FUNCTION(6, "SDA_6306") |
| + ), |
| + MTK_PIN( |
| + 24, "GPIO24", |
| + MTK_EINT_FUNCTION(0, 24), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO24"), |
| + MTK_FUNCTION(1, "SRCLKENAI1"), |
| + MTK_FUNCTION(2, "SPI0_C_MI"), |
| + MTK_FUNCTION(3, "SPI7_B_MI"), |
| + MTK_FUNCTION(4, "I2S6_DI"), |
| + MTK_FUNCTION(5, "I2S8_DI"), |
| + MTK_FUNCTION(6, "SPINOR_CS") |
| + ), |
| + MTK_PIN( |
| + 25, "GPIO25", |
| + MTK_EINT_FUNCTION(0, 25), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO25"), |
| + MTK_FUNCTION(1, "SRCLKENAI0"), |
| + MTK_FUNCTION(2, "SPI0_C_MO"), |
| + MTK_FUNCTION(3, "SPI7_B_MO"), |
| + MTK_FUNCTION(4, "I2S7_DO"), |
| + MTK_FUNCTION(5, "I2S9_DO"), |
| + MTK_FUNCTION(6, "SPINOR_CK") |
| + ), |
| + MTK_PIN( |
| + 26, "GPIO26", |
| + MTK_EINT_FUNCTION(0, 26), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO26"), |
| + MTK_FUNCTION(1, "PWM_2"), |
| + MTK_FUNCTION(2, "CLKM0"), |
| + MTK_FUNCTION(3, "USB_DRVVBUS"), |
| + MTK_FUNCTION(4, "SPI5_C_MI"), |
| + MTK_FUNCTION(5, "I2S9_BCK") |
| + ), |
| + MTK_PIN( |
| + 27, "GPIO27", |
| + MTK_EINT_FUNCTION(0, 27), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO27"), |
| + MTK_FUNCTION(1, "PWM_3"), |
| + MTK_FUNCTION(2, "CLKM1"), |
| + MTK_FUNCTION(4, "SPI5_C_MO"), |
| + MTK_FUNCTION(5, "I2S9_LRCK"), |
| + MTK_FUNCTION(6, "SPINOR_IO0") |
| + ), |
| + MTK_PIN( |
| + 28, "GPIO28", |
| + MTK_EINT_FUNCTION(0, 28), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO28"), |
| + MTK_FUNCTION(1, "PWM_0"), |
| + MTK_FUNCTION(2, "CLKM2"), |
| + MTK_FUNCTION(4, "SPI5_C_CSB"), |
| + MTK_FUNCTION(5, "I2S9_MCK"), |
| + MTK_FUNCTION(6, "SPINOR_IO1") |
| + ), |
| + MTK_PIN( |
| + 29, "GPIO29", |
| + MTK_EINT_FUNCTION(0, 29), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO29"), |
| + MTK_FUNCTION(1, "PWM_1"), |
| + MTK_FUNCTION(2, "CLKM3"), |
| + MTK_FUNCTION(4, "SPI5_C_CLK"), |
| + MTK_FUNCTION(5, "I2S9_DO"), |
| + MTK_FUNCTION(6, "SPINOR_IO2") |
| + ), |
| + MTK_PIN( |
| + 30, "GPIO30", |
| + MTK_EINT_FUNCTION(0, 30), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO30"), |
| + MTK_FUNCTION(1, "PWM_2"), |
| + MTK_FUNCTION(2, "CLKM0"), |
| + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(4, "I2S7_MCK"), |
| + MTK_FUNCTION(5, "I2S9_MCK"), |
| + MTK_FUNCTION(6, "SPINOR_IO3") |
| + ), |
| + MTK_PIN( |
| + 31, "GPIO31", |
| + MTK_EINT_FUNCTION(0, 31), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO31"), |
| + MTK_FUNCTION(1, "I2S3_MCK"), |
| + MTK_FUNCTION(2, "I2S1_MCK"), |
| + MTK_FUNCTION(3, "I2S5_MCK"), |
| + MTK_FUNCTION(4, "SRCLKENAI0"), |
| + MTK_FUNCTION(5, "I2S0_MCK") |
| + ), |
| + MTK_PIN( |
| + 32, "GPIO32", |
| + MTK_EINT_FUNCTION(0, 32), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO32"), |
| + MTK_FUNCTION(1, "I2S3_BCK"), |
| + MTK_FUNCTION(2, "I2S1_BCK"), |
| + MTK_FUNCTION(3, "I2S5_BCK"), |
| + MTK_FUNCTION(4, "PCM0_CLK"), |
| + MTK_FUNCTION(5, "I2S0_BCK") |
| + ), |
| + MTK_PIN( |
| + 33, "GPIO33", |
| + MTK_EINT_FUNCTION(0, 33), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO33"), |
| + MTK_FUNCTION(1, "I2S3_LRCK"), |
| + MTK_FUNCTION(2, "I2S1_LRCK"), |
| + MTK_FUNCTION(3, "I2S5_LRCK"), |
| + MTK_FUNCTION(4, "PCM0_SYNC"), |
| + MTK_FUNCTION(5, "I2S0_LRCK") |
| + ), |
| + MTK_PIN( |
| + 34, "GPIO34", |
| + MTK_EINT_FUNCTION(0, 34), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO34"), |
| + MTK_FUNCTION(1, "I2S0_DI"), |
| + MTK_FUNCTION(2, "I2S2_DI"), |
| + MTK_FUNCTION(3, "I2S2_DI2"), |
| + MTK_FUNCTION(4, "PCM0_DI"), |
| + MTK_FUNCTION(5, "I2S0_DI") |
| + ), |
| + MTK_PIN( |
| + 35, "GPIO35", |
| + MTK_EINT_FUNCTION(0, 35), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO35"), |
| + MTK_FUNCTION(1, "I2S3_DO"), |
| + MTK_FUNCTION(2, "I2S1_DO"), |
| + MTK_FUNCTION(3, "I2S5_DO"), |
| + MTK_FUNCTION(4, "PCM0_DO") |
| + ), |
| + MTK_PIN( |
| + 36, "GPIO36", |
| + MTK_EINT_FUNCTION(0, 36), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO36"), |
| + MTK_FUNCTION(1, "SPI5_A_CLK"), |
| + MTK_FUNCTION(2, "DMIC1_CLK"), |
| + MTK_FUNCTION(4, "MD_URXD0"), |
| + MTK_FUNCTION(5, "UCTS0"), |
| + MTK_FUNCTION(6, "URXD1") |
| + ), |
| + MTK_PIN( |
| + 37, "GPIO37", |
| + MTK_EINT_FUNCTION(0, 37), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO37"), |
| + MTK_FUNCTION(1, "SPI5_A_CSB"), |
| + MTK_FUNCTION(2, "DMIC1_DAT"), |
| + MTK_FUNCTION(4, "MD_UTXD0"), |
| + MTK_FUNCTION(5, "URTS0"), |
| + MTK_FUNCTION(6, "UTXD1") |
| + ), |
| + MTK_PIN( |
| + 38, "GPIO38", |
| + MTK_EINT_FUNCTION(0, 38), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO38"), |
| + MTK_FUNCTION(1, "SPI5_A_MI"), |
| + MTK_FUNCTION(2, "DMIC_CLK"), |
| + MTK_FUNCTION(4, "MD_URXD1"), |
| + MTK_FUNCTION(5, "URXD0"), |
| + MTK_FUNCTION(6, "UCTS1") |
| + ), |
| + MTK_PIN( |
| + 39, "GPIO39", |
| + MTK_EINT_FUNCTION(0, 39), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO39"), |
| + MTK_FUNCTION(1, "SPI5_A_MO"), |
| + MTK_FUNCTION(2, "DMIC_DAT"), |
| + MTK_FUNCTION(4, "MD_UTXD1"), |
| + MTK_FUNCTION(5, "UTXD0"), |
| + MTK_FUNCTION(6, "URTS1") |
| + ), |
| + MTK_PIN( |
| + 40, "GPIO40", |
| + MTK_EINT_FUNCTION(0, 40), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO40"), |
| + MTK_FUNCTION(1, "DISP_PWM"), |
| + MTK_FUNCTION(7, "DBG_MON_A6") |
| + ), |
| + MTK_PIN( |
| + 41, "GPIO41", |
| + MTK_EINT_FUNCTION(0, 41), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO41"), |
| + MTK_FUNCTION(1, "DSI_TE"), |
| + MTK_FUNCTION(7, "DBG_MON_A7") |
| + ), |
| + MTK_PIN( |
| + 42, "GPIO42", |
| + MTK_EINT_FUNCTION(0, 42), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO42"), |
| + MTK_FUNCTION(1, "LCM_RST"), |
| + MTK_FUNCTION(7, "DBG_MON_A8") |
| + ), |
| + MTK_PIN( |
| + 43, "GPIO43", |
| + MTK_EINT_FUNCTION(0, 43), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO43"), |
| + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), |
| + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), |
| + MTK_FUNCTION(3, "SCL_6306"), |
| + MTK_FUNCTION(4, "ADSP_URXD0"), |
| + MTK_FUNCTION(5, "PTA_RXD"), |
| + MTK_FUNCTION(6, "SSPM_URXD_AO"), |
| + MTK_FUNCTION(7, "DBG_MON_B0") |
| + ), |
| + MTK_PIN( |
| + 44, "GPIO44", |
| + MTK_EINT_FUNCTION(0, 44), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO44"), |
| + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), |
| + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), |
| + MTK_FUNCTION(3, "SDA_6306"), |
| + MTK_FUNCTION(4, "ADSP_UTXD0"), |
| + MTK_FUNCTION(5, "PTA_TXD"), |
| + MTK_FUNCTION(6, "SSPM_UTXD_AO"), |
| + MTK_FUNCTION(7, "DBG_MON_B1") |
| + ), |
| + MTK_PIN( |
| + 45, "GPIO45", |
| + MTK_EINT_FUNCTION(0, 45), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO45"), |
| + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), |
| + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), |
| + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), |
| + MTK_FUNCTION(4, "APU_JTAG_TDI"), |
| + MTK_FUNCTION(5, "CCU_JTAG_TDI"), |
| + MTK_FUNCTION(6, "LVTS_SCK"), |
| + MTK_FUNCTION(7, "CONN_DSP_JDI") |
| + ), |
| + MTK_PIN( |
| + 46, "GPIO46", |
| + MTK_EINT_FUNCTION(0, 46), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO46"), |
| + MTK_FUNCTION(1, "MD1_SIM2_SRST"), |
| + MTK_FUNCTION(2, "MD1_SIM1_SRST"), |
| + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), |
| + MTK_FUNCTION(4, "APU_JTAG_TMS"), |
| + MTK_FUNCTION(5, "CCU_JTAG_TMS"), |
| + MTK_FUNCTION(6, "LVTS_SDI"), |
| + MTK_FUNCTION(7, "CONN_DSP_JMS") |
| + ), |
| + MTK_PIN( |
| + 47, "GPIO47", |
| + MTK_EINT_FUNCTION(0, 47), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO47"), |
| + MTK_FUNCTION(1, "MD1_SIM2_SIO"), |
| + MTK_FUNCTION(2, "MD1_SIM1_SIO"), |
| + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), |
| + MTK_FUNCTION(4, "APU_JTAG_TDO"), |
| + MTK_FUNCTION(5, "CCU_JTAG_TDO"), |
| + MTK_FUNCTION(6, "LVTS_SCF"), |
| + MTK_FUNCTION(7, "CONN_DSP_JDO") |
| + ), |
| + MTK_PIN( |
| + 48, "GPIO48", |
| + MTK_EINT_FUNCTION(0, 48), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO48"), |
| + MTK_FUNCTION(1, "MD1_SIM1_SIO"), |
| + MTK_FUNCTION(2, "MD1_SIM2_SIO"), |
| + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), |
| + MTK_FUNCTION(4, "APU_JTAG_TRST"), |
| + MTK_FUNCTION(5, "CCU_JTAG_TRST"), |
| + MTK_FUNCTION(6, "LVTS_FOUT"), |
| + MTK_FUNCTION(7, "CONN_DSP_JINTP") |
| + ), |
| + MTK_PIN( |
| + 49, "GPIO49", |
| + MTK_EINT_FUNCTION(0, 49), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO49"), |
| + MTK_FUNCTION(1, "MD1_SIM1_SRST"), |
| + MTK_FUNCTION(2, "MD1_SIM2_SRST"), |
| + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), |
| + MTK_FUNCTION(4, "APU_JTAG_TCK"), |
| + MTK_FUNCTION(5, "CCU_JTAG_TCK"), |
| + MTK_FUNCTION(6, "LVTS_SDO"), |
| + MTK_FUNCTION(7, "CONN_DSP_JCK") |
| + ), |
| + MTK_PIN( |
| + 50, "GPIO50", |
| + MTK_EINT_FUNCTION(0, 50), |
| + DRV_GRP0, |
| + MTK_FUNCTION(0, "GPIO50"), |
| + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), |
| + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), |
| + MTK_FUNCTION(6, "LVTS_26M") |
| + ), |
| + MTK_PIN( |
| + 51, "GPIO51", |
| + MTK_EINT_FUNCTION(0, 51), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO51"), |
| + MTK_FUNCTION(1, "MSDC1_CLK"), |
| + MTK_FUNCTION(2, "PCM1_CLK"), |
| + MTK_FUNCTION(3, "CONN_DSP_JCK"), |
| + MTK_FUNCTION(4, "UDI_TCK"), |
| + MTK_FUNCTION(5, "IPU_JTAG_TCK"), |
| + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), |
| + MTK_FUNCTION(7, "JTCK_SEL3") |
| + ), |
| + MTK_PIN( |
| + 52, "GPIO52", |
| + MTK_EINT_FUNCTION(0, 52), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO52"), |
| + MTK_FUNCTION(1, "MSDC1_CMD"), |
| + MTK_FUNCTION(2, "PCM1_SYNC"), |
| + MTK_FUNCTION(3, "CONN_DSP_JMS"), |
| + MTK_FUNCTION(4, "UDI_TMS"), |
| + MTK_FUNCTION(5, "IPU_JTAG_TMS"), |
| + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), |
| + MTK_FUNCTION(7, "JTMS_SEL3") |
| + ), |
| + MTK_PIN( |
| + 53, "GPIO53", |
| + MTK_EINT_FUNCTION(0, 53), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO53"), |
| + MTK_FUNCTION(1, "MSDC1_DAT3"), |
| + MTK_FUNCTION(2, "PCM1_DI"), |
| + MTK_FUNCTION(3, "CONN_DSP_JINTP"), |
| + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC") |
| + ), |
| + MTK_PIN( |
| + 54, "GPIO54", |
| + MTK_EINT_FUNCTION(0, 54), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO54"), |
| + MTK_FUNCTION(1, "MSDC1_DAT0"), |
| + MTK_FUNCTION(2, "PCM1_DO0"), |
| + MTK_FUNCTION(3, "CONN_DSP_JDI"), |
| + MTK_FUNCTION(4, "UDI_TDI"), |
| + MTK_FUNCTION(5, "IPU_JTAG_TDI"), |
| + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), |
| + MTK_FUNCTION(7, "JTDI_SEL3") |
| + ), |
| + MTK_PIN( |
| + 55, "GPIO55", |
| + MTK_EINT_FUNCTION(0, 55), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO55"), |
| + MTK_FUNCTION(1, "MSDC1_DAT2"), |
| + MTK_FUNCTION(2, "PCM1_DO2"), |
| + MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"), |
| + MTK_FUNCTION(4, "UDI_NTRST"), |
| + MTK_FUNCTION(5, "IPU_JTAG_TRST"), |
| + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN"), |
| + MTK_FUNCTION(7, "JTRSTN_SEL3") |
| + ), |
| + MTK_PIN( |
| + 56, "GPIO56", |
| + MTK_EINT_FUNCTION(0, 56), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO56"), |
| + MTK_FUNCTION(1, "MSDC1_DAT1"), |
| + MTK_FUNCTION(2, "PCM1_DO1"), |
| + MTK_FUNCTION(3, "CONN_DSP_JDO"), |
| + MTK_FUNCTION(4, "UDI_TDO"), |
| + MTK_FUNCTION(5, "IPU_JTAG_TDO"), |
| + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), |
| + MTK_FUNCTION(7, "JTDO_SEL3") |
| + ), |
| + MTK_PIN( |
| + 57, "GPIO57", |
| + MTK_EINT_FUNCTION(0, 57), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO57"), |
| + MTK_FUNCTION(1, "MIPI2_D_SCLK") |
| + ), |
| + MTK_PIN( |
| + 58, "GPIO58", |
| + MTK_EINT_FUNCTION(0, 58), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO58"), |
| + MTK_FUNCTION(1, "MIPI2_D_SDATA") |
| + ), |
| + MTK_PIN( |
| + 59, "GPIO59", |
| + MTK_EINT_FUNCTION(0, 59), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO59"), |
| + MTK_FUNCTION(1, "MIPI_M_SCLK") |
| + ), |
| + MTK_PIN( |
| + 60, "GPIO60", |
| + MTK_EINT_FUNCTION(0, 60), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO60"), |
| + MTK_FUNCTION(1, "MIPI_M_SDATA") |
| + ), |
| + MTK_PIN( |
| + 61, "GPIO61", |
| + MTK_EINT_FUNCTION(0, 61), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO61"), |
| + MTK_FUNCTION(1, "MD_UCNT_A_TGL") |
| + ), |
| + MTK_PIN( |
| + 62, "GPIO62", |
| + MTK_EINT_FUNCTION(0, 62), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO62"), |
| + MTK_FUNCTION(1, "DIGRF_IRQ") |
| + ), |
| + MTK_PIN( |
| + 63, "GPIO63", |
| + MTK_EINT_FUNCTION(0, 63), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO63"), |
| + MTK_FUNCTION(1, "BPI_BUS0"), |
| + MTK_FUNCTION(3, "PCIE_WAKE_N") |
| + ), |
| + MTK_PIN( |
| + 64, "GPIO64", |
| + MTK_EINT_FUNCTION(0, 64), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO64"), |
| + MTK_FUNCTION(1, "BPI_BUS1"), |
| + MTK_FUNCTION(3, "PCIE_PERESET_N") |
| + ), |
| + MTK_PIN( |
| + 65, "GPIO65", |
| + MTK_EINT_FUNCTION(0, 65), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO65"), |
| + MTK_FUNCTION(1, "BPI_BUS2"), |
| + MTK_FUNCTION(3, "PCIE_CLKREQ_N") |
| + ), |
| + MTK_PIN( |
| + 66, "GPIO66", |
| + MTK_EINT_FUNCTION(0, 66), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO66"), |
| + MTK_FUNCTION(1, "BPI_BUS3") |
| + ), |
| + MTK_PIN( |
| + 67, "GPIO67", |
| + MTK_EINT_FUNCTION(0, 67), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO67"), |
| + MTK_FUNCTION(1, "BPI_BUS4") |
| + ), |
| + MTK_PIN( |
| + 68, "GPIO68", |
| + MTK_EINT_FUNCTION(0, 68), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO68"), |
| + MTK_FUNCTION(1, "BPI_BUS5") |
| + ), |
| + MTK_PIN( |
| + 69, "GPIO69", |
| + MTK_EINT_FUNCTION(0, 69), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO69"), |
| + MTK_FUNCTION(1, "BPI_BUS6"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS6") |
| + ), |
| + MTK_PIN( |
| + 70, "GPIO70", |
| + MTK_EINT_FUNCTION(0, 70), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO70"), |
| + MTK_FUNCTION(1, "BPI_BUS7"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS7") |
| + ), |
| + MTK_PIN( |
| + 71, "GPIO71", |
| + MTK_EINT_FUNCTION(0, 71), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO71"), |
| + MTK_FUNCTION(1, "BPI_BUS8"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS8") |
| + ), |
| + MTK_PIN( |
| + 72, "GPIO72", |
| + MTK_EINT_FUNCTION(0, 72), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO72"), |
| + MTK_FUNCTION(1, "BPI_BUS9"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS9") |
| + ), |
| + MTK_PIN( |
| + 73, "GPIO73", |
| + MTK_EINT_FUNCTION(0, 73), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO73"), |
| + MTK_FUNCTION(1, "BPI_BUS10"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS10") |
| + ), |
| + MTK_PIN( |
| + 74, "GPIO74", |
| + MTK_EINT_FUNCTION(0, 74), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO74"), |
| + MTK_FUNCTION(1, "BPI_BUS11_OLAT0"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0") |
| + ), |
| + MTK_PIN( |
| + 75, "GPIO75", |
| + MTK_EINT_FUNCTION(0, 75), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO75"), |
| + MTK_FUNCTION(1, "BPI_BUS12_OLAT1"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1") |
| + ), |
| + MTK_PIN( |
| + 76, "GPIO76", |
| + MTK_EINT_FUNCTION(0, 76), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO76"), |
| + MTK_FUNCTION(1, "BPI_BUS13_OLAT2"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2") |
| + ), |
| + MTK_PIN( |
| + 77, "GPIO77", |
| + MTK_EINT_FUNCTION(0, 77), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO77"), |
| + MTK_FUNCTION(1, "BPI_BUS14_OLAT3"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3") |
| + ), |
| + MTK_PIN( |
| + 78, "GPIO78", |
| + MTK_EINT_FUNCTION(0, 78), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO78"), |
| + MTK_FUNCTION(1, "BPI_BUS15_OLAT4"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4") |
| + ), |
| + MTK_PIN( |
| + 79, "GPIO79", |
| + MTK_EINT_FUNCTION(0, 79), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO79"), |
| + MTK_FUNCTION(1, "BPI_BUS16_OLAT5"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5") |
| + ), |
| + MTK_PIN( |
| + 80, "GPIO80", |
| + MTK_EINT_FUNCTION(0, 80), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO80"), |
| + MTK_FUNCTION(1, "BPI_BUS17_ANT0"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), |
| + MTK_FUNCTION(3, "PCIE_WAKE_N") |
| + ), |
| + MTK_PIN( |
| + 81, "GPIO81", |
| + MTK_EINT_FUNCTION(0, 81), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO81"), |
| + MTK_FUNCTION(1, "BPI_BUS18_ANT1"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), |
| + MTK_FUNCTION(3, "PCIE_PERESET_N") |
| + ), |
| + MTK_PIN( |
| + 82, "GPIO82", |
| + MTK_EINT_FUNCTION(0, 82), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO82"), |
| + MTK_FUNCTION(1, "BPI_BUS19_ANT2"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), |
| + MTK_FUNCTION(3, "PCIE_CLKREQ_N") |
| + ), |
| + MTK_PIN( |
| + 83, "GPIO83", |
| + MTK_EINT_FUNCTION(0, 83), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO83"), |
| + MTK_FUNCTION(1, "BPI_BUS20_ANT3"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3") |
| + ), |
| + MTK_PIN( |
| + 84, "GPIO84", |
| + MTK_EINT_FUNCTION(0, 84), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO84"), |
| + MTK_FUNCTION(1, "BPI_BUS21_ANT4"), |
| + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4") |
| + ), |
| + MTK_PIN( |
| + 85, "GPIO85", |
| + MTK_EINT_FUNCTION(0, 85), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO85"), |
| + MTK_FUNCTION(1, "MIPI1_D_SCLK"), |
| + MTK_FUNCTION(2, "CONN_MIPI1_SCLK") |
| + ), |
| + MTK_PIN( |
| + 86, "GPIO86", |
| + MTK_EINT_FUNCTION(0, 86), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO86"), |
| + MTK_FUNCTION(1, "MIPI1_D_SDATA"), |
| + MTK_FUNCTION(2, "CONN_MIPI1_SDATA") |
| + ), |
| + MTK_PIN( |
| + 87, "GPIO87", |
| + MTK_EINT_FUNCTION(0, 87), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO87"), |
| + MTK_FUNCTION(1, "MIPI0_D_SCLK"), |
| + MTK_FUNCTION(2, "CONN_MIPI0_SCLK") |
| + ), |
| + MTK_PIN( |
| + 88, "GPIO88", |
| + MTK_EINT_FUNCTION(0, 88), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO88"), |
| + MTK_FUNCTION(1, "MIPI0_D_SDATA"), |
| + MTK_FUNCTION(2, "CONN_MIPI0_SDATA") |
| + ), |
| + MTK_PIN( |
| + 89, "GPIO89", |
| + MTK_EINT_FUNCTION(0, 89), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO89"), |
| + MTK_FUNCTION(1, "SPMI_SCL"), |
| + MTK_FUNCTION(2, "SCL10") |
| + ), |
| + MTK_PIN( |
| + 90, "GPIO90", |
| + MTK_EINT_FUNCTION(0, 90), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO90"), |
| + MTK_FUNCTION(1, "SPMI_SDA"), |
| + MTK_FUNCTION(2, "SDA10") |
| + ), |
| + MTK_PIN( |
| + 91, "GPIO91", |
| + MTK_EINT_FUNCTION(0, 91), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO91"), |
| + MTK_FUNCTION(1, "AP_GOOD") |
| + ), |
| + MTK_PIN( |
| + 92, "GPIO92", |
| + MTK_EINT_FUNCTION(0, 92), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO92"), |
| + MTK_FUNCTION(1, "URXD0"), |
| + MTK_FUNCTION(2, "MD_URXD0"), |
| + MTK_FUNCTION(3, "MD_URXD1"), |
| + MTK_FUNCTION(4, "SSPM_URXD_AO"), |
| + MTK_FUNCTION(5, "CONN_UART0_RXD") |
| + ), |
| + MTK_PIN( |
| + 93, "GPIO93", |
| + MTK_EINT_FUNCTION(0, 93), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO93"), |
| + MTK_FUNCTION(1, "UTXD0"), |
| + MTK_FUNCTION(2, "MD_UTXD0"), |
| + MTK_FUNCTION(3, "MD_UTXD1"), |
| + MTK_FUNCTION(4, "SSPM_UTXD_AO"), |
| + MTK_FUNCTION(5, "CONN_UART0_TXD"), |
| + MTK_FUNCTION(6, "WIFI_TXD") |
| + ), |
| + MTK_PIN( |
| + 94, "GPIO94", |
| + MTK_EINT_FUNCTION(0, 94), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO94"), |
| + MTK_FUNCTION(1, "URXD1"), |
| + MTK_FUNCTION(2, "ADSP_URXD0"), |
| + MTK_FUNCTION(3, "MD32_0_RXD"), |
| + MTK_FUNCTION(4, "SSPM_URXD_AO"), |
| + MTK_FUNCTION(5, "TP_URXD1_AO"), |
| + MTK_FUNCTION(6, "TP_URXD2_AO"), |
| + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER") |
| + ), |
| + MTK_PIN( |
| + 95, "GPIO95", |
| + MTK_EINT_FUNCTION(0, 95), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO95"), |
| + MTK_FUNCTION(1, "UTXD1"), |
| + MTK_FUNCTION(2, "ADSP_UTXD0"), |
| + MTK_FUNCTION(3, "MD32_0_TXD"), |
| + MTK_FUNCTION(4, "SSPM_UTXD_AO"), |
| + MTK_FUNCTION(5, "TP_UTXD1_AO"), |
| + MTK_FUNCTION(6, "TP_UTXD2_AO"), |
| + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER") |
| + ), |
| + MTK_PIN( |
| + 96, "GPIO96", |
| + MTK_EINT_FUNCTION(0, 96), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO96"), |
| + MTK_FUNCTION(1, "TDM_LRCK"), |
| + MTK_FUNCTION(2, "I2S7_LRCK"), |
| + MTK_FUNCTION(3, "I2S9_LRCK"), |
| + MTK_FUNCTION(4, "DPI_D0"), |
| + MTK_FUNCTION(5, "ADSP_JTAG0_TDI"), |
| + MTK_FUNCTION(7, "IO_JTAG_TDI") |
| + ), |
| + MTK_PIN( |
| + 97, "GPIO97", |
| + MTK_EINT_FUNCTION(0, 97), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO97"), |
| + MTK_FUNCTION(1, "TDM_BCK"), |
| + MTK_FUNCTION(2, "I2S7_BCK"), |
| + MTK_FUNCTION(3, "I2S9_BCK"), |
| + MTK_FUNCTION(4, "DPI_D1"), |
| + MTK_FUNCTION(5, "ADSP_JTAG0_TRSTN"), |
| + MTK_FUNCTION(7, "IO_JTAG_TRSTN") |
| + ), |
| + MTK_PIN( |
| + 98, "GPIO98", |
| + MTK_EINT_FUNCTION(0, 98), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO98"), |
| + MTK_FUNCTION(1, "TDM_MCK"), |
| + MTK_FUNCTION(2, "I2S7_MCK"), |
| + MTK_FUNCTION(3, "I2S9_MCK"), |
| + MTK_FUNCTION(4, "DPI_D2"), |
| + MTK_FUNCTION(5, "ADSP_JTAG0_TCK"), |
| + MTK_FUNCTION(7, "IO_JTAG_TCK") |
| + ), |
| + MTK_PIN( |
| + 99, "GPIO99", |
| + MTK_EINT_FUNCTION(0, 99), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO99"), |
| + MTK_FUNCTION(1, "TDM_DATA0"), |
| + MTK_FUNCTION(2, "I2S6_DI"), |
| + MTK_FUNCTION(3, "I2S8_DI"), |
| + MTK_FUNCTION(4, "DPI_D3"), |
| + MTK_FUNCTION(5, "ADSP_JTAG0_TDO"), |
| + MTK_FUNCTION(7, "IO_JTAG_TDO") |
| + ), |
| + MTK_PIN( |
| + 100, "GPIO100", |
| + MTK_EINT_FUNCTION(0, 100), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO100"), |
| + MTK_FUNCTION(1, "TDM_DATA1"), |
| + MTK_FUNCTION(2, "I2S7_DO"), |
| + MTK_FUNCTION(3, "I2S9_DO"), |
| + MTK_FUNCTION(4, "DPI_D4"), |
| + MTK_FUNCTION(5, "ADSP_JTAG0_TMS"), |
| + MTK_FUNCTION(7, "IO_JTAG_TMS") |
| + ), |
| + MTK_PIN( |
| + 101, "GPIO101", |
| + MTK_EINT_FUNCTION(0, 101), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO101"), |
| + MTK_FUNCTION(1, "TDM_DATA2"), |
| + MTK_FUNCTION(2, "DMIC1_CLK"), |
| + MTK_FUNCTION(3, "SRCLKENAI0"), |
| + MTK_FUNCTION(4, "DPI_D5"), |
| + MTK_FUNCTION(5, "CLKM0"), |
| + MTK_FUNCTION(7, "DAP_MD32_SWD") |
| + ), |
| + MTK_PIN( |
| + 102, "GPIO102", |
| + MTK_EINT_FUNCTION(0, 102), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO102"), |
| + MTK_FUNCTION(1, "TDM_DATA3"), |
| + MTK_FUNCTION(2, "DMIC1_DAT"), |
| + MTK_FUNCTION(3, "SRCLKENAI1"), |
| + MTK_FUNCTION(4, "DPI_D6"), |
| + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), |
| + MTK_FUNCTION(7, "DAP_MD32_SWCK") |
| + ), |
| + MTK_PIN( |
| + 103, "GPIO103", |
| + MTK_EINT_FUNCTION(0, 103), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO103"), |
| + MTK_FUNCTION(1, "SPI0_A_MI"), |
| + MTK_FUNCTION(2, "SCP_SPI0_MI"), |
| + MTK_FUNCTION(4, "DPI_D7"), |
| + MTK_FUNCTION(5, "DFD_TDO"), |
| + MTK_FUNCTION(6, "SPM_JTAG_TDO"), |
| + MTK_FUNCTION(7, "JTDO_SEL1") |
| + ), |
| + MTK_PIN( |
| + 104, "GPIO104", |
| + MTK_EINT_FUNCTION(0, 104), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO104"), |
| + MTK_FUNCTION(1, "SPI0_A_CSB"), |
| + MTK_FUNCTION(2, "SCP_SPI0_CS"), |
| + MTK_FUNCTION(4, "DPI_D8"), |
| + MTK_FUNCTION(5, "DFD_TMS"), |
| + MTK_FUNCTION(6, "SPM_JTAG_TMS"), |
| + MTK_FUNCTION(7, "JTMS_SEL1") |
| + ), |
| + MTK_PIN( |
| + 105, "GPIO105", |
| + MTK_EINT_FUNCTION(0, 105), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO105"), |
| + MTK_FUNCTION(1, "SPI0_A_MO"), |
| + MTK_FUNCTION(2, "SCP_SPI0_MO"), |
| + MTK_FUNCTION(3, "SCP_SDA0"), |
| + MTK_FUNCTION(4, "DPI_D9"), |
| + MTK_FUNCTION(5, "DFD_TDI"), |
| + MTK_FUNCTION(6, "SPM_JTAG_TDI"), |
| + MTK_FUNCTION(7, "JTDI_SEL1") |
| + ), |
| + MTK_PIN( |
| + 106, "GPIO106", |
| + MTK_EINT_FUNCTION(0, 106), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO106"), |
| + MTK_FUNCTION(1, "SPI0_A_CLK"), |
| + MTK_FUNCTION(2, "SCP_SPI0_CK"), |
| + MTK_FUNCTION(3, "SCP_SCL0"), |
| + MTK_FUNCTION(4, "DPI_D10"), |
| + MTK_FUNCTION(5, "DFD_TCK_XI"), |
| + MTK_FUNCTION(6, "SPM_JTAG_TCK"), |
| + MTK_FUNCTION(7, "JTCK_SEL1") |
| + ), |
| + MTK_PIN( |
| + 107, "GPIO107", |
| + MTK_EINT_FUNCTION(0, 107), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO107"), |
| + MTK_FUNCTION(1, "DMIC_CLK"), |
| + MTK_FUNCTION(2, "PWM_0"), |
| + MTK_FUNCTION(3, "CLKM2"), |
| + MTK_FUNCTION(6, "SPM_JTAG_TRSTN"), |
| + MTK_FUNCTION(7, "JTRSTN_SEL1") |
| + ), |
| + MTK_PIN( |
| + 108, "GPIO108", |
| + MTK_EINT_FUNCTION(0, 108), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO108"), |
| + MTK_FUNCTION(1, "DMIC_DAT"), |
| + MTK_FUNCTION(2, "PWM_1"), |
| + MTK_FUNCTION(3, "CLKM3"), |
| + MTK_FUNCTION(7, "DAP_SONIC_SWD") |
| + ), |
| + MTK_PIN( |
| + 109, "GPIO109", |
| + MTK_EINT_FUNCTION(0, 109), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO109"), |
| + MTK_FUNCTION(1, "I2S1_MCK"), |
| + MTK_FUNCTION(2, "I2S3_MCK"), |
| + MTK_FUNCTION(3, "I2S2_MCK"), |
| + MTK_FUNCTION(4, "DPI_DE"), |
| + MTK_FUNCTION(5, "I2S2_MCK"), |
| + MTK_FUNCTION(6, "SRCLKENAI0"), |
| + MTK_FUNCTION(7, "DAP_SONIC_SWCK") |
| + ), |
| + MTK_PIN( |
| + 110, "GPIO110", |
| + MTK_EINT_FUNCTION(0, 110), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO110"), |
| + MTK_FUNCTION(1, "I2S1_BCK"), |
| + MTK_FUNCTION(2, "I2S3_BCK"), |
| + MTK_FUNCTION(3, "I2S2_BCK"), |
| + MTK_FUNCTION(4, "DPI_D11"), |
| + MTK_FUNCTION(5, "I2S2_BCK"), |
| + MTK_FUNCTION(6, "CONN_MCU_TDO") |
| + ), |
| + MTK_PIN( |
| + 111, "GPIO111", |
| + MTK_EINT_FUNCTION(0, 111), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO111"), |
| + MTK_FUNCTION(1, "I2S1_LRCK"), |
| + MTK_FUNCTION(2, "I2S3_LRCK"), |
| + MTK_FUNCTION(3, "I2S2_LRCK"), |
| + MTK_FUNCTION(4, "DPI_VSYNC"), |
| + MTK_FUNCTION(5, "I2S2_LRCK"), |
| + MTK_FUNCTION(6, "CONN_MCU_TDI") |
| + ), |
| + MTK_PIN( |
| + 112, "GPIO112", |
| + MTK_EINT_FUNCTION(0, 112), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO112"), |
| + MTK_FUNCTION(1, "I2S2_DI"), |
| + MTK_FUNCTION(2, "I2S0_DI"), |
| + MTK_FUNCTION(3, "I2S2_DI2"), |
| + MTK_FUNCTION(4, "DPI_CK"), |
| + MTK_FUNCTION(5, "I2S2_DI"), |
| + MTK_FUNCTION(6, "CONN_MCU_TMS") |
| + ), |
| + MTK_PIN( |
| + 113, "GPIO113", |
| + MTK_EINT_FUNCTION(0, 113), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO113"), |
| + MTK_FUNCTION(1, "I2S1_DO"), |
| + MTK_FUNCTION(2, "I2S3_DO"), |
| + MTK_FUNCTION(3, "I2S5_DO"), |
| + MTK_FUNCTION(4, "DPI_HSYNC"), |
| + MTK_FUNCTION(5, "I2S2_DI2"), |
| + MTK_FUNCTION(6, "CONN_MCU_TCK") |
| + ), |
| + MTK_PIN( |
| + 114, "GPIO114", |
| + MTK_EINT_FUNCTION(0, 114), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO114"), |
| + MTK_FUNCTION(1, "SPI2_MI"), |
| + MTK_FUNCTION(2, "SCP_SPI2_MI"), |
| + MTK_FUNCTION(4, "PCM0_DI"), |
| + MTK_FUNCTION(6, "CONN_MCU_TRST_B") |
| + ), |
| + MTK_PIN( |
| + 115, "GPIO115", |
| + MTK_EINT_FUNCTION(0, 115), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO115"), |
| + MTK_FUNCTION(1, "SPI2_CSB"), |
| + MTK_FUNCTION(2, "SCP_SPI2_CS"), |
| + MTK_FUNCTION(4, "PCM0_SYNC"), |
| + MTK_FUNCTION(6, "CONN_MCU_DBGI_N") |
| + ), |
| + MTK_PIN( |
| + 116, "GPIO116", |
| + MTK_EINT_FUNCTION(0, 116), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO116"), |
| + MTK_FUNCTION(1, "SPI2_MO"), |
| + MTK_FUNCTION(2, "SCP_SPI2_MO"), |
| + MTK_FUNCTION(3, "SCP_SDA1"), |
| + MTK_FUNCTION(4, "PCM0_DO"), |
| + MTK_FUNCTION(6, "CONN_MCU_DBGACK_N") |
| + ), |
| + MTK_PIN( |
| + 117, "GPIO117", |
| + MTK_EINT_FUNCTION(0, 117), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO117"), |
| + MTK_FUNCTION(1, "SPI2_CLK"), |
| + MTK_FUNCTION(2, "SCP_SPI2_CK"), |
| + MTK_FUNCTION(3, "SCP_SCL1"), |
| + MTK_FUNCTION(4, "PCM0_CLK") |
| + ), |
| + MTK_PIN( |
| + 118, "GPIO118", |
| + MTK_EINT_FUNCTION(0, 118), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO118"), |
| + MTK_FUNCTION(1, "SCL1"), |
| + MTK_FUNCTION(2, "SCP_SCL0"), |
| + MTK_FUNCTION(3, "SCP_SCL1") |
| + ), |
| + MTK_PIN( |
| + 119, "GPIO119", |
| + MTK_EINT_FUNCTION(0, 119), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO119"), |
| + MTK_FUNCTION(1, "SDA1"), |
| + MTK_FUNCTION(2, "SCP_SDA0"), |
| + MTK_FUNCTION(3, "SCP_SDA1") |
| + ), |
| + MTK_PIN( |
| + 120, "GPIO120", |
| + MTK_EINT_FUNCTION(0, 120), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO120"), |
| + MTK_FUNCTION(1, "SCL9"), |
| + MTK_FUNCTION(2, "SCP_SCL0") |
| + ), |
| + MTK_PIN( |
| + 121, "GPIO121", |
| + MTK_EINT_FUNCTION(0, 121), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO121"), |
| + MTK_FUNCTION(1, "SDA9"), |
| + MTK_FUNCTION(2, "SCP_SDA0") |
| + ), |
| + MTK_PIN( |
| + 122, "GPIO122", |
| + MTK_EINT_FUNCTION(0, 122), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO122"), |
| + MTK_FUNCTION(1, "SCL8"), |
| + MTK_FUNCTION(2, "SCP_SDA0") |
| + ), |
| + MTK_PIN( |
| + 123, "GPIO123", |
| + MTK_EINT_FUNCTION(0, 123), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO123"), |
| + MTK_FUNCTION(1, "SDA8"), |
| + MTK_FUNCTION(2, "SCP_SCL0") |
| + ), |
| + MTK_PIN( |
| + 124, "GPIO124", |
| + MTK_EINT_FUNCTION(0, 124), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO124"), |
| + MTK_FUNCTION(1, "SCL7"), |
| + MTK_FUNCTION(2, "DMIC1_CLK") |
| + ), |
| + MTK_PIN( |
| + 125, "GPIO125", |
| + MTK_EINT_FUNCTION(0, 125), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO125"), |
| + MTK_FUNCTION(1, "SDA7"), |
| + MTK_FUNCTION(2, "DMIC1_DAT") |
| + ), |
| + MTK_PIN( |
| + 126, "GPIO126", |
| + MTK_EINT_FUNCTION(0, 126), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO126"), |
| + MTK_FUNCTION(1, "CMFLASH0"), |
| + MTK_FUNCTION(2, "PWM_2"), |
| + MTK_FUNCTION(3, "TP_UCTS1_AO"), |
| + MTK_FUNCTION(4, "UCTS0"), |
| + MTK_FUNCTION(5, "SCL11"), |
| + MTK_FUNCTION(6, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(7, "DBG_MON_A14") |
| + ), |
| + MTK_PIN( |
| + 127, "GPIO127", |
| + MTK_EINT_FUNCTION(0, 127), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO127"), |
| + MTK_FUNCTION(1, "CMFLASH1"), |
| + MTK_FUNCTION(2, "PWM_3"), |
| + MTK_FUNCTION(3, "TP_URTS1_AO"), |
| + MTK_FUNCTION(4, "URTS0"), |
| + MTK_FUNCTION(5, "SDA11"), |
| + MTK_FUNCTION(7, "DBG_MON_A15") |
| + ), |
| + MTK_PIN( |
| + 128, "GPIO128", |
| + MTK_EINT_FUNCTION(0, 128), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO128"), |
| + MTK_FUNCTION(1, "CMFLASH2"), |
| + MTK_FUNCTION(2, "PWM_0"), |
| + MTK_FUNCTION(3, "TP_UCTS2_AO"), |
| + MTK_FUNCTION(4, "UCTS1"), |
| + MTK_FUNCTION(5, "SCL_6306"), |
| + MTK_FUNCTION(7, "DBG_MON_A16") |
| + ), |
| + MTK_PIN( |
| + 129, "GPIO129", |
| + MTK_EINT_FUNCTION(0, 129), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO129"), |
| + MTK_FUNCTION(1, "CMFLASH3"), |
| + MTK_FUNCTION(2, "PWM_1"), |
| + MTK_FUNCTION(3, "TP_URTS2_AO"), |
| + MTK_FUNCTION(4, "URTS1"), |
| + MTK_FUNCTION(5, "SDA_6306"), |
| + MTK_FUNCTION(7, "DBG_MON_A17") |
| + ), |
| + MTK_PIN( |
| + 130, "GPIO130", |
| + MTK_EINT_FUNCTION(0, 130), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO130"), |
| + MTK_FUNCTION(1, "CMVREF0"), |
| + MTK_FUNCTION(2, "ANT_SEL10"), |
| + MTK_FUNCTION(3, "SCP_JTAG0_TDO"), |
| + MTK_FUNCTION(4, "MD32_0_JTAG_TDO"), |
| + MTK_FUNCTION(5, "SCL11"), |
| + MTK_FUNCTION(6, "SPI5_B_CLK"), |
| + MTK_FUNCTION(7, "DBG_MON_A22") |
| + ), |
| + MTK_PIN( |
| + 131, "GPIO131", |
| + MTK_EINT_FUNCTION(0, 131), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO131"), |
| + MTK_FUNCTION(1, "CMVREF1"), |
| + MTK_FUNCTION(2, "ANT_SEL11"), |
| + MTK_FUNCTION(3, "SCP_JTAG0_TDI"), |
| + MTK_FUNCTION(4, "MD32_0_JTAG_TDI"), |
| + MTK_FUNCTION(5, "SDA11"), |
| + MTK_FUNCTION(6, "SPI5_B_MO"), |
| + MTK_FUNCTION(7, "DBG_MON_A25") |
| + ), |
| + MTK_PIN( |
| + 132, "GPIO132", |
| + MTK_EINT_FUNCTION(0, 132), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO132"), |
| + MTK_FUNCTION(1, "CMVREF2"), |
| + MTK_FUNCTION(2, "ANT_SEL12"), |
| + MTK_FUNCTION(3, "SCP_JTAG0_TMS"), |
| + MTK_FUNCTION(4, "MD32_0_JTAG_TMS"), |
| + MTK_FUNCTION(7, "DBG_MON_A28") |
| + ), |
| + MTK_PIN( |
| + 133, "GPIO133", |
| + MTK_EINT_FUNCTION(0, 133), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO133"), |
| + MTK_FUNCTION(1, "CMVREF3"), |
| + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(3, "SCP_JTAG0_TCK"), |
| + MTK_FUNCTION(4, "MD32_0_JTAG_TCK"), |
| + MTK_FUNCTION(6, "SPI5_B_CSB"), |
| + MTK_FUNCTION(7, "DBG_MON_A23") |
| + ), |
| + MTK_PIN( |
| + 134, "GPIO134", |
| + MTK_EINT_FUNCTION(0, 134), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO134"), |
| + MTK_FUNCTION(1, "CMVREF4"), |
| + MTK_FUNCTION(3, "SCP_JTAG0_TRSTN"), |
| + MTK_FUNCTION(4, "MD32_0_JTAG_TRST"), |
| + MTK_FUNCTION(7, "DBG_MON_A26") |
| + ), |
| + MTK_PIN( |
| + 135, "GPIO135", |
| + MTK_EINT_FUNCTION(0, 135), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO135"), |
| + MTK_FUNCTION(1, "PWM_0"), |
| + MTK_FUNCTION(2, "SRCLKENAI1"), |
| + MTK_FUNCTION(3, "MD_URXD0"), |
| + MTK_FUNCTION(4, "MD32_0_RXD"), |
| + MTK_FUNCTION(5, "CONN_TCXOENA_REQ"), |
| + MTK_FUNCTION(7, "DBG_MON_A29") |
| + ), |
| + MTK_PIN( |
| + 136, "GPIO136", |
| + MTK_EINT_FUNCTION(0, 136), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO136"), |
| + MTK_FUNCTION(1, "CMMCLK3"), |
| + MTK_FUNCTION(2, "CLKM1"), |
| + MTK_FUNCTION(3, "MD_UTXD0"), |
| + MTK_FUNCTION(4, "MD32_0_TXD"), |
| + MTK_FUNCTION(6, "SPI5_B_MI"), |
| + MTK_FUNCTION(7, "DBG_MON_A24") |
| + ), |
| + MTK_PIN( |
| + 137, "GPIO137", |
| + MTK_EINT_FUNCTION(0, 137), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO137"), |
| + MTK_FUNCTION(1, "CMMCLK4"), |
| + MTK_FUNCTION(2, "CLKM2"), |
| + MTK_FUNCTION(3, "MD_URXD1"), |
| + MTK_FUNCTION(6, "CONN_UART0_RXD"), |
| + MTK_FUNCTION(7, "DBG_MON_A27") |
| + ), |
| + MTK_PIN( |
| + 138, "GPIO138", |
| + MTK_EINT_FUNCTION(0, 138), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO138"), |
| + MTK_FUNCTION(1, "CMMCLK5"), |
| + MTK_FUNCTION(2, "CLKM3"), |
| + MTK_FUNCTION(3, "MD_UTXD1"), |
| + MTK_FUNCTION(6, "CONN_UART0_TXD"), |
| + MTK_FUNCTION(7, "DBG_MON_A30") |
| + ), |
| + MTK_PIN( |
| + 139, "GPIO139", |
| + MTK_EINT_FUNCTION(0, 139), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO139"), |
| + MTK_FUNCTION(1, "SCL4"), |
| + MTK_FUNCTION(7, "DBG_MON_A21") |
| + ), |
| + MTK_PIN( |
| + 140, "GPIO140", |
| + MTK_EINT_FUNCTION(0, 140), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO140"), |
| + MTK_FUNCTION(1, "SDA4"), |
| + MTK_FUNCTION(7, "DBG_MON_A20") |
| + ), |
| + MTK_PIN( |
| + 141, "GPIO141", |
| + MTK_EINT_FUNCTION(0, 141), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO141"), |
| + MTK_FUNCTION(1, "SCL2"), |
| + MTK_FUNCTION(7, "DBG_MON_A18") |
| + ), |
| + MTK_PIN( |
| + 142, "GPIO142", |
| + MTK_EINT_FUNCTION(0, 142), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO142"), |
| + MTK_FUNCTION(1, "SDA2"), |
| + MTK_FUNCTION(7, "DBG_MON_A19") |
| + ), |
| + MTK_PIN( |
| + 143, "GPIO143", |
| + MTK_EINT_FUNCTION(0, 143), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO143"), |
| + MTK_FUNCTION(1, "CMVREF0"), |
| + MTK_FUNCTION(2, "SPI3_CLK"), |
| + MTK_FUNCTION(3, "ADSP_JTAG1_TDO"), |
| + MTK_FUNCTION(4, "SCP_JTAG1_TDO"), |
| + MTK_FUNCTION(7, "DBG_MON_A31") |
| + ), |
| + MTK_PIN( |
| + 144, "GPIO144", |
| + MTK_EINT_FUNCTION(0, 144), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO144"), |
| + MTK_FUNCTION(1, "CMVREF1"), |
| + MTK_FUNCTION(2, "SPI3_CSB"), |
| + MTK_FUNCTION(3, "ADSP_JTAG1_TDI"), |
| + MTK_FUNCTION(4, "SCP_JTAG1_TDI") |
| + ), |
| + MTK_PIN( |
| + 145, "GPIO145", |
| + MTK_EINT_FUNCTION(0, 145), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO145"), |
| + MTK_FUNCTION(1, "CMVREF2"), |
| + MTK_FUNCTION(2, "SPI3_MI"), |
| + MTK_FUNCTION(3, "ADSP_JTAG1_TMS"), |
| + MTK_FUNCTION(4, "SCP_JTAG1_TMS") |
| + ), |
| + MTK_PIN( |
| + 146, "GPIO146", |
| + MTK_EINT_FUNCTION(0, 146), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO146"), |
| + MTK_FUNCTION(1, "CMVREF3"), |
| + MTK_FUNCTION(2, "SPI3_MO"), |
| + MTK_FUNCTION(3, "ADSP_JTAG1_TCK"), |
| + MTK_FUNCTION(4, "SCP_JTAG1_TCK"), |
| + MTK_FUNCTION(7, "DBG_MON_A32") |
| + ), |
| + MTK_PIN( |
| + 147, "GPIO147", |
| + MTK_EINT_FUNCTION(0, 147), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO147"), |
| + MTK_FUNCTION(1, "CMVREF4"), |
| + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), |
| + MTK_FUNCTION(3, "ADSP_JTAG1_TRSTN"), |
| + MTK_FUNCTION(4, "SCP_JTAG1_TRSTN") |
| + ), |
| + MTK_PIN( |
| + 148, "GPIO148", |
| + MTK_EINT_FUNCTION(0, 148), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO148"), |
| + MTK_FUNCTION(1, "PWM_1"), |
| + MTK_FUNCTION(2, "AGPS_SYNC"), |
| + MTK_FUNCTION(3, "CMMCLK5") |
| + ), |
| + MTK_PIN( |
| + 149, "GPIO149", |
| + MTK_EINT_FUNCTION(0, 149), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO149"), |
| + MTK_FUNCTION(1, "CMMCLK0"), |
| + MTK_FUNCTION(2, "CLKM0"), |
| + MTK_FUNCTION(3, "MD32_0_GPIO0") |
| + ), |
| + MTK_PIN( |
| + 150, "GPIO150", |
| + MTK_EINT_FUNCTION(0, 150), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO150"), |
| + MTK_FUNCTION(1, "CMMCLK1"), |
| + MTK_FUNCTION(2, "CLKM1"), |
| + MTK_FUNCTION(3, "MD32_0_GPIO1"), |
| + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") |
| + ), |
| + MTK_PIN( |
| + 151, "GPIO151", |
| + MTK_EINT_FUNCTION(0, 151), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO151"), |
| + MTK_FUNCTION(1, "CMMCLK2"), |
| + MTK_FUNCTION(2, "CLKM2"), |
| + MTK_FUNCTION(3, "MD32_0_GPIO2"), |
| + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") |
| + ), |
| + MTK_PIN( |
| + 152, "GPIO152", |
| + MTK_EINT_FUNCTION(0, 152), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO152"), |
| + MTK_FUNCTION(1, "KPROW1"), |
| + MTK_FUNCTION(2, "PWM_2"), |
| + MTK_FUNCTION(3, "IDDIG"), |
| + MTK_FUNCTION(6, "MBISTREADEN_TRIGGER"), |
| + MTK_FUNCTION(7, "DBG_MON_B9") |
| + ), |
| + MTK_PIN( |
| + 153, "GPIO153", |
| + MTK_EINT_FUNCTION(0, 153), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO153"), |
| + MTK_FUNCTION(1, "KPROW0"), |
| + MTK_FUNCTION(7, "DBG_MON_B8") |
| + ), |
| + MTK_PIN( |
| + 154, "GPIO154", |
| + MTK_EINT_FUNCTION(0, 154), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO154"), |
| + MTK_FUNCTION(1, "KPCOL0"), |
| + MTK_FUNCTION(7, "DBG_MON_B6") |
| + ), |
| + MTK_PIN( |
| + 155, "GPIO155", |
| + MTK_EINT_FUNCTION(0, 155), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO155"), |
| + MTK_FUNCTION(1, "KPCOL1"), |
| + MTK_FUNCTION(2, "PWM_3"), |
| + MTK_FUNCTION(3, "USB_DRVVBUS"), |
| + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), |
| + MTK_FUNCTION(6, "MBISTWRITEEN_TRIGGER"), |
| + MTK_FUNCTION(7, "DBG_MON_B7") |
| + ), |
| + MTK_PIN( |
| + 156, "GPIO156", |
| + MTK_EINT_FUNCTION(0, 156), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO156"), |
| + MTK_FUNCTION(1, "SPI1_A_CLK"), |
| + MTK_FUNCTION(2, "SCP_SPI1_A_CK"), |
| + MTK_FUNCTION(3, "MRG_CLK"), |
| + MTK_FUNCTION(4, "AGPS_SYNC"), |
| + MTK_FUNCTION(5, "MD_URXD0"), |
| + MTK_FUNCTION(6, "UDI_TMS"), |
| + MTK_FUNCTION(7, "DBG_MON_B10") |
| + ), |
| + MTK_PIN( |
| + 157, "GPIO157", |
| + MTK_EINT_FUNCTION(0, 157), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO157"), |
| + MTK_FUNCTION(1, "SPI1_A_CSB"), |
| + MTK_FUNCTION(2, "SCP_SPI1_A_CS"), |
| + MTK_FUNCTION(3, "MRG_SYNC"), |
| + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), |
| + MTK_FUNCTION(5, "MD_UTXD0"), |
| + MTK_FUNCTION(6, "UDI_TCK"), |
| + MTK_FUNCTION(7, "DBG_MON_B11") |
| + ), |
| + MTK_PIN( |
| + 158, "GPIO158", |
| + MTK_EINT_FUNCTION(0, 158), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO158"), |
| + MTK_FUNCTION(1, "SPI1_A_MI"), |
| + MTK_FUNCTION(2, "SCP_SPI1_A_MI"), |
| + MTK_FUNCTION(3, "MRG_DI"), |
| + MTK_FUNCTION(4, "PTA_RXD"), |
| + MTK_FUNCTION(5, "MD_URXD1"), |
| + MTK_FUNCTION(6, "UDI_TDO"), |
| + MTK_FUNCTION(7, "DBG_MON_B12") |
| + ), |
| + MTK_PIN( |
| + 159, "GPIO159", |
| + MTK_EINT_FUNCTION(0, 159), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO159"), |
| + MTK_FUNCTION(1, "SPI1_A_MO"), |
| + MTK_FUNCTION(2, "SCP_SPI1_A_MO"), |
| + MTK_FUNCTION(3, "MRG_DO"), |
| + MTK_FUNCTION(4, "PTA_TXD"), |
| + MTK_FUNCTION(5, "MD_UTXD1"), |
| + MTK_FUNCTION(6, "UDI_NTRST"), |
| + MTK_FUNCTION(7, "DBG_MON_B13") |
| + ), |
| + MTK_PIN( |
| + 160, "GPIO160", |
| + MTK_EINT_FUNCTION(0, 160), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO160"), |
| + MTK_FUNCTION(1, "SCL3"), |
| + MTK_FUNCTION(3, "SCP_SCL1"), |
| + MTK_FUNCTION(7, "DBG_MON_B14") |
| + ), |
| + MTK_PIN( |
| + 161, "GPIO161", |
| + MTK_EINT_FUNCTION(0, 161), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO161"), |
| + MTK_FUNCTION(1, "SDA3"), |
| + MTK_FUNCTION(3, "SCP_SDA1"), |
| + MTK_FUNCTION(7, "DBG_MON_B15") |
| + ), |
| + MTK_PIN( |
| + 162, "GPIO162", |
| + MTK_EINT_FUNCTION(0, 162), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO162"), |
| + MTK_FUNCTION(1, "ANT_SEL0"), |
| + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(6, "UDI_TDI"), |
| + MTK_FUNCTION(7, "DBG_MON_B16") |
| + ), |
| + MTK_PIN( |
| + 163, "GPIO163", |
| + MTK_EINT_FUNCTION(0, 163), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO163"), |
| + MTK_FUNCTION(1, "ANT_SEL1"), |
| + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), |
| + MTK_FUNCTION(7, "DBG_MON_B17") |
| + ), |
| + MTK_PIN( |
| + 164, "GPIO164", |
| + MTK_EINT_FUNCTION(0, 164), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO164"), |
| + MTK_FUNCTION(1, "ANT_SEL2"), |
| + MTK_FUNCTION(2, "SCP_SPI1_B_CK"), |
| + MTK_FUNCTION(3, "TP_URXD1_AO"), |
| + MTK_FUNCTION(5, "UCTS0"), |
| + MTK_FUNCTION(7, "DBG_MON_B18") |
| + ), |
| + MTK_PIN( |
| + 165, "GPIO165", |
| + MTK_EINT_FUNCTION(0, 165), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO165"), |
| + MTK_FUNCTION(1, "ANT_SEL3"), |
| + MTK_FUNCTION(2, "SCP_SPI1_B_CS"), |
| + MTK_FUNCTION(3, "TP_UTXD1_AO"), |
| + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), |
| + MTK_FUNCTION(5, "URTS0"), |
| + MTK_FUNCTION(7, "DBG_MON_B19") |
| + ), |
| + MTK_PIN( |
| + 166, "GPIO166", |
| + MTK_EINT_FUNCTION(0, 166), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO166"), |
| + MTK_FUNCTION(1, "ANT_SEL4"), |
| + MTK_FUNCTION(2, "SCP_SPI1_B_MI"), |
| + MTK_FUNCTION(3, "TP_URXD2_AO"), |
| + MTK_FUNCTION(4, "SRCLKENAI1"), |
| + MTK_FUNCTION(5, "UCTS1"), |
| + MTK_FUNCTION(7, "DBG_MON_B20") |
| + ), |
| + MTK_PIN( |
| + 167, "GPIO167", |
| + MTK_EINT_FUNCTION(0, 167), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO167"), |
| + MTK_FUNCTION(1, "ANT_SEL5"), |
| + MTK_FUNCTION(2, "SCP_SPI1_B_MO"), |
| + MTK_FUNCTION(3, "TP_UTXD2_AO"), |
| + MTK_FUNCTION(4, "SRCLKENAI0"), |
| + MTK_FUNCTION(5, "URTS1"), |
| + MTK_FUNCTION(7, "DBG_MON_B21") |
| + ), |
| + MTK_PIN( |
| + 168, "GPIO168", |
| + MTK_EINT_FUNCTION(0, 168), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO168"), |
| + MTK_FUNCTION(1, "ANT_SEL6"), |
| + MTK_FUNCTION(2, "SPI0_B_CLK"), |
| + MTK_FUNCTION(3, "TP_UCTS1_AO"), |
| + MTK_FUNCTION(4, "KPCOL2"), |
| + MTK_FUNCTION(5, "MD_UCTS0"), |
| + MTK_FUNCTION(6, "SCL11"), |
| + MTK_FUNCTION(7, "DBG_MON_B22") |
| + ), |
| + MTK_PIN( |
| + 169, "GPIO169", |
| + MTK_EINT_FUNCTION(0, 169), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO169"), |
| + MTK_FUNCTION(1, "ANT_SEL7"), |
| + MTK_FUNCTION(2, "SPI0_B_CSB"), |
| + MTK_FUNCTION(3, "TP_URTS1_AO"), |
| + MTK_FUNCTION(4, "KPROW2"), |
| + MTK_FUNCTION(5, "MD_URTS0"), |
| + MTK_FUNCTION(6, "SDA11"), |
| + MTK_FUNCTION(7, "DBG_MON_B23") |
| + ), |
| + MTK_PIN( |
| + 170, "GPIO170", |
| + MTK_EINT_FUNCTION(0, 170), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO170"), |
| + MTK_FUNCTION(1, "ANT_SEL8"), |
| + MTK_FUNCTION(2, "SPI0_B_MI"), |
| + MTK_FUNCTION(3, "TP_UCTS2_AO"), |
| + MTK_FUNCTION(4, "SRCLKENAI1"), |
| + MTK_FUNCTION(5, "MD_UCTS1"), |
| + MTK_FUNCTION(7, "DBG_MON_B24") |
| + ), |
| + MTK_PIN( |
| + 171, "GPIO171", |
| + MTK_EINT_FUNCTION(0, 171), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO171"), |
| + MTK_FUNCTION(1, "ANT_SEL9"), |
| + MTK_FUNCTION(2, "SPI0_B_MO"), |
| + MTK_FUNCTION(3, "TP_URTS2_AO"), |
| + MTK_FUNCTION(4, "SRCLKENAI0"), |
| + MTK_FUNCTION(5, "MD_URTS1"), |
| + MTK_FUNCTION(7, "DBG_MON_B25") |
| + ), |
| + MTK_PIN( |
| + 172, "GPIO172", |
| + MTK_EINT_FUNCTION(0, 172), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO172"), |
| + MTK_FUNCTION(1, "CONN_TOP_CLK"), |
| + MTK_FUNCTION(2, "AUXIF_CLK0"), |
| + MTK_FUNCTION(7, "DBG_MON_B29") |
| + ), |
| + MTK_PIN( |
| + 173, "GPIO173", |
| + MTK_EINT_FUNCTION(0, 173), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO173"), |
| + MTK_FUNCTION(1, "CONN_TOP_DATA"), |
| + MTK_FUNCTION(2, "AUXIF_ST0"), |
| + MTK_FUNCTION(7, "DBG_MON_B30") |
| + ), |
| + MTK_PIN( |
| + 174, "GPIO174", |
| + MTK_EINT_FUNCTION(0, 174), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO174"), |
| + MTK_FUNCTION(1, "CONN_HRST_B"), |
| + MTK_FUNCTION(7, "DBG_MON_B28") |
| + ), |
| + MTK_PIN( |
| + 175, "GPIO175", |
| + MTK_EINT_FUNCTION(0, 175), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO175"), |
| + MTK_FUNCTION(1, "CONN_WB_PTA"), |
| + MTK_FUNCTION(7, "DBG_MON_B31") |
| + ), |
| + MTK_PIN( |
| + 176, "GPIO176", |
| + MTK_EINT_FUNCTION(0, 176), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO176"), |
| + MTK_FUNCTION(1, "CONN_BT_CLK"), |
| + MTK_FUNCTION(2, "AUXIF_CLK1"), |
| + MTK_FUNCTION(7, "DBG_MON_B26") |
| + ), |
| + MTK_PIN( |
| + 177, "GPIO177", |
| + MTK_EINT_FUNCTION(0, 177), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO177"), |
| + MTK_FUNCTION(1, "CONN_BT_DATA"), |
| + MTK_FUNCTION(2, "AUXIF_ST1"), |
| + MTK_FUNCTION(7, "DBG_MON_B27") |
| + ), |
| + MTK_PIN( |
| + 178, "GPIO178", |
| + MTK_EINT_FUNCTION(0, 178), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO178"), |
| + MTK_FUNCTION(1, "CONN_WF_CTRL0") |
| + ), |
| + MTK_PIN( |
| + 179, "GPIO179", |
| + MTK_EINT_FUNCTION(0, 179), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO179"), |
| + MTK_FUNCTION(1, "CONN_WF_CTRL1"), |
| + MTK_FUNCTION(2, "UFS_MPHY_SCL") |
| + ), |
| + MTK_PIN( |
| + 180, "GPIO180", |
| + MTK_EINT_FUNCTION(0, 180), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO180"), |
| + MTK_FUNCTION(1, "CONN_WF_CTRL2"), |
| + MTK_FUNCTION(2, "UFS_MPHY_SDA") |
| + ), |
| + MTK_PIN( |
| + 181, "GPIO181", |
| + MTK_EINT_FUNCTION(0, 181), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO181"), |
| + MTK_FUNCTION(1, "CONN_WF_CTRL3") |
| + ), |
| + MTK_PIN( |
| + 182, "GPIO182", |
| + MTK_EINT_FUNCTION(0, 182), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO182"), |
| + MTK_FUNCTION(1, "CONN_WF_CTRL4") |
| + ), |
| + MTK_PIN( |
| + 183, "GPIO183", |
| + MTK_EINT_FUNCTION(0, 183), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO183"), |
| + MTK_FUNCTION(1, "MSDC0_CMD") |
| + ), |
| + MTK_PIN( |
| + 184, "GPIO184", |
| + MTK_EINT_FUNCTION(0, 184), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO184"), |
| + MTK_FUNCTION(1, "MSDC0_DAT0") |
| + ), |
| + MTK_PIN( |
| + 185, "GPIO185", |
| + MTK_EINT_FUNCTION(0, 185), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO185"), |
| + MTK_FUNCTION(1, "MSDC0_DAT2") |
| + ), |
| + MTK_PIN( |
| + 186, "GPIO186", |
| + MTK_EINT_FUNCTION(0, 186), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO186"), |
| + MTK_FUNCTION(1, "MSDC0_DAT4") |
| + ), |
| + MTK_PIN( |
| + 187, "GPIO187", |
| + MTK_EINT_FUNCTION(0, 187), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO187"), |
| + MTK_FUNCTION(1, "MSDC0_DAT6") |
| + ), |
| + MTK_PIN( |
| + 188, "GPIO188", |
| + MTK_EINT_FUNCTION(0, 188), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO188"), |
| + MTK_FUNCTION(1, "MSDC0_DAT1") |
| + ), |
| + MTK_PIN( |
| + 189, "GPIO189", |
| + MTK_EINT_FUNCTION(0, 189), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO189"), |
| + MTK_FUNCTION(1, "MSDC0_DAT5") |
| + ), |
| + MTK_PIN( |
| + 190, "GPIO190", |
| + MTK_EINT_FUNCTION(0, 190), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO190"), |
| + MTK_FUNCTION(1, "MSDC0_DAT7") |
| + ), |
| + MTK_PIN( |
| + 191, "GPIO191", |
| + MTK_EINT_FUNCTION(0, 191), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO191"), |
| + MTK_FUNCTION(1, "MSDC0_DSL"), |
| + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), |
| + MTK_FUNCTION(3, "IDDIG"), |
| + MTK_FUNCTION(4, "DMIC_CLK") |
| + ), |
| + MTK_PIN( |
| + 192, "GPIO192", |
| + MTK_EINT_FUNCTION(0, 192), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO192"), |
| + MTK_FUNCTION(1, "MSDC0_CLK"), |
| + MTK_FUNCTION(3, "USB_DRVVBUS"), |
| + MTK_FUNCTION(4, "DMIC_DAT") |
| + ), |
| + MTK_PIN( |
| + 193, "GPIO193", |
| + MTK_EINT_FUNCTION(0, 193), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO193"), |
| + MTK_FUNCTION(1, "MSDC0_DAT3") |
| + ), |
| + MTK_PIN( |
| + 194, "GPIO194", |
| + MTK_EINT_FUNCTION(0, 194), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO194"), |
| + MTK_FUNCTION(1, "MSDC0_RSTB") |
| + ), |
| + MTK_PIN( |
| + 195, "GPIO195", |
| + MTK_EINT_FUNCTION(0, 195), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO195"), |
| + MTK_FUNCTION(1, "SCP_VREQ_VAO"), |
| + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") |
| + ), |
| + MTK_PIN( |
| + 196, "GPIO196", |
| + MTK_EINT_FUNCTION(0, 196), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO196"), |
| + MTK_FUNCTION(1, "AUD_DAT_MOSI2") |
| + ), |
| + MTK_PIN( |
| + 197, "GPIO197", |
| + MTK_EINT_FUNCTION(0, 197), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO197"), |
| + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), |
| + MTK_FUNCTION(2, "AUD_CLK_MISO"), |
| + MTK_FUNCTION(3, "I2S2_MCK"), |
| + MTK_FUNCTION(4, "I2S6_MCK"), |
| + MTK_FUNCTION(5, "I2S8_MCK") |
| + ), |
| + MTK_PIN( |
| + 198, "GPIO198", |
| + MTK_EINT_FUNCTION(0, 198), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO198"), |
| + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), |
| + MTK_FUNCTION(2, "AUD_SYNC_MISO"), |
| + MTK_FUNCTION(3, "I2S2_BCK"), |
| + MTK_FUNCTION(4, "I2S6_BCK"), |
| + MTK_FUNCTION(5, "I2S8_BCK") |
| + ), |
| + MTK_PIN( |
| + 199, "GPIO199", |
| + MTK_EINT_FUNCTION(0, 199), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO199"), |
| + MTK_FUNCTION(1, "AUD_DAT_MISO2"), |
| + MTK_FUNCTION(3, "I2S2_DI2") |
| + ), |
| + MTK_PIN( |
| + 200, "GPIO200", |
| + MTK_EINT_FUNCTION(0, 200), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO200"), |
| + MTK_FUNCTION(1, "SCL6"), |
| + MTK_FUNCTION(3, "SCP_SCL1"), |
| + MTK_FUNCTION(4, "SCL_6306"), |
| + MTK_FUNCTION(7, "DBG_MON_A4") |
| + ), |
| + MTK_PIN( |
| + 201, "GPIO201", |
| + MTK_EINT_FUNCTION(0, 201), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO201"), |
| + MTK_FUNCTION(1, "SDA6"), |
| + MTK_FUNCTION(3, "SCP_SDA1"), |
| + MTK_FUNCTION(4, "SDA_6306"), |
| + MTK_FUNCTION(7, "DBG_MON_A5") |
| + ), |
| + MTK_PIN( |
| + 202, "GPIO202", |
| + MTK_EINT_FUNCTION(0, 202), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO202"), |
| + MTK_FUNCTION(1, "SCL5") |
| + ), |
| + MTK_PIN( |
| + 203, "GPIO203", |
| + MTK_EINT_FUNCTION(0, 203), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO203"), |
| + MTK_FUNCTION(1, "SDA5") |
| + ), |
| + MTK_PIN( |
| + 204, "GPIO204", |
| + MTK_EINT_FUNCTION(0, 204), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO204"), |
| + MTK_FUNCTION(1, "SCL0"), |
| + MTK_FUNCTION(6, "SPI7_A_CLK"), |
| + MTK_FUNCTION(7, "DBG_MON_A2") |
| + ), |
| + MTK_PIN( |
| + 205, "GPIO205", |
| + MTK_EINT_FUNCTION(0, 205), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO205"), |
| + MTK_FUNCTION(1, "SDA0"), |
| + MTK_FUNCTION(6, "SPI7_A_CSB"), |
| + MTK_FUNCTION(7, "DBG_MON_A3") |
| + ), |
| + MTK_PIN( |
| + 206, "GPIO206", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO206"), |
| + MTK_FUNCTION(1, "SRCLKENA0") |
| + ), |
| + MTK_PIN( |
| + 207, "GPIO207", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO207"), |
| + MTK_FUNCTION(1, "SRCLKENA1") |
| + ), |
| + MTK_PIN( |
| + 208, "GPIO208", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO208"), |
| + MTK_FUNCTION(1, "WATCHDOG") |
| + ), |
| + MTK_PIN( |
| + 209, "GPIO209", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO209"), |
| + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), |
| + MTK_FUNCTION(2, "PWRAP_SPI0_MO") |
| + ), |
| + MTK_PIN( |
| + 210, "GPIO210", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO210"), |
| + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") |
| + ), |
| + MTK_PIN( |
| + 211, "GPIO211", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO211"), |
| + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), |
| + MTK_FUNCTION(2, "PWRAP_SPI0_MI") |
| + ), |
| + MTK_PIN( |
| + 212, "GPIO212", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO212"), |
| + MTK_FUNCTION(1, "PWRAP_SPI0_CK") |
| + ), |
| + MTK_PIN( |
| + 213, "GPIO213", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO213"), |
| + MTK_FUNCTION(1, "RTC32K_CK") |
| + ), |
| + MTK_PIN( |
| + 214, "GPIO214", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO214"), |
| + MTK_FUNCTION(1, "AUD_CLK_MOSI"), |
| + MTK_FUNCTION(3, "I2S1_MCK"), |
| + MTK_FUNCTION(4, "I2S7_MCK"), |
| + MTK_FUNCTION(5, "I2S9_MCK") |
| + ), |
| + MTK_PIN( |
| + 215, "GPIO215", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO215"), |
| + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), |
| + MTK_FUNCTION(3, "I2S1_BCK"), |
| + MTK_FUNCTION(4, "I2S7_BCK"), |
| + MTK_FUNCTION(5, "I2S9_BCK") |
| + ), |
| + MTK_PIN( |
| + 216, "GPIO216", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO216"), |
| + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), |
| + MTK_FUNCTION(3, "I2S1_LRCK"), |
| + MTK_FUNCTION(4, "I2S7_LRCK"), |
| + MTK_FUNCTION(5, "I2S9_LRCK") |
| + ), |
| + MTK_PIN( |
| + 217, "GPIO217", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO217"), |
| + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), |
| + MTK_FUNCTION(3, "I2S1_DO"), |
| + MTK_FUNCTION(4, "I2S7_DO"), |
| + MTK_FUNCTION(5, "I2S9_DO") |
| + ), |
| + MTK_PIN( |
| + 218, "GPIO218", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO218"), |
| + MTK_FUNCTION(1, "AUD_DAT_MISO0"), |
| + MTK_FUNCTION(2, "VOW_DAT_MISO"), |
| + MTK_FUNCTION(3, "I2S2_LRCK"), |
| + MTK_FUNCTION(4, "I2S6_LRCK"), |
| + MTK_FUNCTION(5, "I2S8_LRCK") |
| + ), |
| + MTK_PIN( |
| + 219, "GPIO219", |
| + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, "GPIO219"), |
| + MTK_FUNCTION(1, "AUD_DAT_MISO1"), |
| + MTK_FUNCTION(2, "VOW_CLK_MISO"), |
| + MTK_FUNCTION(3, "I2S2_DI"), |
| + MTK_FUNCTION(4, "I2S6_DI"), |
| + MTK_FUNCTION(5, "I2S8_DI") |
| + ), |
| + MTK_PIN( |
| + 220, "GPIO220", |
| + MTK_EINT_FUNCTION(0, 208), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 221, "GPIO221", |
| + MTK_EINT_FUNCTION(0, 209), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 222, "GPIO222", |
| + MTK_EINT_FUNCTION(0, 210), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 223, "GPIO223", |
| + MTK_EINT_FUNCTION(0, 211), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 224, "GPIO224", |
| + MTK_EINT_FUNCTION(0, 212), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 225, "GPIO225", |
| + MTK_EINT_FUNCTION(0, 214), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 226, "GPIO226", |
| + MTK_EINT_FUNCTION(0, 215), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + MTK_PIN( |
| + 227, "GPIO227", |
| + MTK_EINT_FUNCTION(0, 216), |
| + DRV_GRP4, |
| + MTK_FUNCTION(0, NULL) |
| + ), |
| + |
| +}; |
| + |
| +#endif /* __PINCTRL_MTK_MT6873_H */ |
| diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c |
| index 923264d0e9ef2c595b93d559bc04fb209e736045..ab1732c61c9a2f20e82f9bb287029a61d72ce59e 100644 |
| --- a/drivers/pinctrl/mediatek/pinctrl-paris.c |
| +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c |
| @@ -51,13 +51,24 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, |
| struct pinctrl_gpio_range *range, |
| unsigned int pin) |
| { |
| + int err; |
| struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
| const struct mtk_pin_desc *desc; |
| |
| desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; |
| |
| - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, |
| + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, |
| hw->soc->gpio_m); |
| + if (err) |
| + return err; |
| + |
| + if (hw->soc->eh_pin_pinmux) { |
| + err = mtk_eh_ctrl(hw, desc, hw->soc->gpio_m); |
| + if (err) |
| + return err; |
| + } |
| + |
| + return 0; |
| } |
| |
| static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, |
| @@ -629,7 +640,16 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, |
| return -EINVAL; |
| |
| desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin]; |
| - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval); |
| + ret = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, |
| + desc_func->muxval); |
| + if (ret) |
| + return ret; |
| + |
| + if (hw->soc->eh_pin_pinmux) { |
| + ret = mtk_eh_ctrl(hw, desc, desc_func->muxval); |
| + if (ret) |
| + return ret; |
| + } |
| |
| return 0; |
| } |
| @@ -693,6 +713,12 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) |
| const struct mtk_pin_desc *desc; |
| int value, err; |
| |
| + if (gpio > hw->soc->npins) |
| + return -EINVAL; |
| + |
| + if (mtk_is_virt_gpio(hw, gpio)) |
| + return 1; |
| + |
| desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
| |
| err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value); |
| diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig |
| index 3ee63531f6d5c36d36ffd24b2e7477cf1290e439..94b6a79f4955c6a8626561f479d5d0b40d9808ae 100644 |
| --- a/drivers/regulator/Kconfig |
| +++ b/drivers/regulator/Kconfig |
| @@ -610,6 +610,16 @@ config REGULATOR_MT6311 |
| This driver supports the control of different power rails of device |
| through regulator interface. |
| |
| +config REGULATOR_MT6315 |
| + tristate "MediaTek MT6315 PMIC" |
| + depends on SPMI |
| + select REGMAP_SPMI |
| + help |
| + Say y here to select this option to enable the power regulator of |
| + MediaTek MT6315 PMIC. |
| + This driver supports the control of different power rails of device |
| + through regulator interface. |
| + |
| config REGULATOR_MT6323 |
| tristate "MediaTek MT6323 PMIC" |
| depends on MFD_MT6397 |
| @@ -628,6 +638,15 @@ config REGULATOR_MT6358 |
| This driver supports the control of different power rails of device |
| through regulator interface. |
| |
| +config REGULATOR_MT6359 |
| + tristate "MediaTek MT6359 PMIC" |
| + depends on MFD_MT6397 |
| + help |
| + Say y here to select this option to enable the power regulator of |
| + MediaTek MT6359 PMIC. |
| + This driver supports the control of different power rails of device |
| + through regulator interface. |
| + |
| config REGULATOR_MT6380 |
| tristate "MediaTek MT6380 PMIC" |
| depends on MTK_PMIC_WRAP |
| diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile |
| index 2210ba56f9bd115e6229e02861d7009358d977dd..f426c34cfa33b4a61bf3a6466fe8f753e79940ea 100644 |
| --- a/drivers/regulator/Makefile |
| +++ b/drivers/regulator/Makefile |
| @@ -78,8 +78,10 @@ obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o |
| obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o |
| obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o |
| obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o |
| +obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o |
| obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o |
| obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o |
| +obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o |
| obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o |
| obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o |
| obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o |
| diff --git a/drivers/regulator/mt6315-regulator.c b/drivers/regulator/mt6315-regulator.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..f62e5de96e913fba8fc6051beaae62e2bc953fc3 |
| --- /dev/null |
| +++ b/drivers/regulator/mt6315-regulator.c |
| @@ -0,0 +1,389 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| + |
| +#include <linux/interrupt.h> |
| +#include <linux/module.h> |
| +#include <linux/of_device.h> |
| +#include <linux/of_irq.h> |
| +#include <linux/platform_device.h> |
| +#include <linux/regmap.h> |
| +#include <linux/regulator/driver.h> |
| +#include <linux/regulator/machine.h> |
| +#include <linux/regulator/mt6315-regulator.h> |
| +#include <linux/regulator/of_regulator.h> |
| +#include <linux/spmi.h> |
| + |
| +#define MT6315_REG_WIDTH 8 |
| + |
| +#define MT6315_BUCK_MODE_AUTO 0 |
| +#define MT6315_BUCK_MODE_FORCE_PWM 1 |
| +#define MT6315_BUCK_MODE_NORMAL 0 |
| +#define MT6315_BUCK_MODE_LP 2 |
| + |
| +/* |
| + * MT6315 regulators' information |
| + * |
| + * @desc: standard fields of regulator description. |
| + * @da_reg: for query status of regulators. |
| + * @qi: Mask for query enable signal status of regulators. |
| + * @modeset_reg: for operating AUTO/PWM mode register. |
| + * @modeset_mask: MASK for operating modeset register. |
| + */ |
| +struct mt6315_regulator_info { |
| + struct regulator_desc desc; |
| + u32 da_vsel_reg; |
| + u32 da_reg; |
| + u32 qi; |
| + u32 modeset_reg; |
| + u32 modeset_mask; |
| + u32 lp_mode_reg; |
| + u32 lp_mode_mask; |
| + u32 lp_mode_shift; |
| +}; |
| + |
| +/* |
| + * MTK regulators' init data |
| + * |
| + * @id: chip slave id |
| + * @size: num of regulators |
| + * @regulator_info: regulator info. |
| + */ |
| +struct mt_regulator_init_data { |
| + u32 id; |
| + u32 size; |
| + struct mt6315_regulator_info *regulator_info; |
| +}; |
| + |
| +struct mt6315_chip { |
| + struct device *dev; |
| + struct regmap *regmap; |
| + struct mutex lock; |
| + u32 slave_id; |
| +}; |
| + |
| +#define MT_BUCK(match, _name, volt_ranges, _bid, _vsel, _modeset_mask) \ |
| +[MT6315_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6315_volt_range_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6315_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = 0xbf, \ |
| + .linear_ranges = volt_ranges, \ |
| + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ |
| + .vsel_reg = _vsel, \ |
| + .vsel_mask = 0xff, \ |
| + .enable_reg = MT6315_BUCK_TOP_CON0, \ |
| + .enable_mask = BIT(_bid - 1), \ |
| + .of_map_mode = mt6315_map_mode, \ |
| + }, \ |
| + .da_vsel_reg = MT6315_BUCK_VBUCK##_bid##_DBG0, \ |
| + .da_reg = MT6315_BUCK_VBUCK##_bid##_DBG4, \ |
| + .qi = BIT(0), \ |
| + .lp_mode_reg = MT6315_BUCK_TOP_CON1, \ |
| + .lp_mode_mask = BIT(_bid - 1), \ |
| + .lp_mode_shift = _bid - 1, \ |
| + .modeset_reg = MT6315_BUCK_TOP_4PHASE_ANA_CON42, \ |
| + .modeset_mask = _modeset_mask, \ |
| +} |
| + |
| +static const struct regulator_linear_range mt_volt_range1[] = { |
| + REGULATOR_LINEAR_RANGE(0, 0, 0xbf, 6250), |
| +}; |
| + |
| +static unsigned int mt6315_map_mode(unsigned int mode) |
| +{ |
| + switch (mode) { |
| + case MT6315_BUCK_MODE_AUTO: |
| + return REGULATOR_MODE_NORMAL; |
| + case MT6315_BUCK_MODE_FORCE_PWM: |
| + return REGULATOR_MODE_FAST; |
| + case MT6315_BUCK_MODE_LP: |
| + return REGULATOR_MODE_IDLE; |
| + default: |
| + return -EINVAL; |
| + } |
| +} |
| + |
| +static int mt6315_regulator_get_voltage_sel(struct regulator_dev *rdev) |
| +{ |
| + struct mt6315_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret = 0, reg_addr = 0, reg_val = 0, reg_en = 0; |
| + |
| + ret = regmap_read(rdev->regmap, info->da_reg, ®_en); |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, "Failed to get enable reg: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if (reg_en & info->qi) |
| + reg_addr = info->da_vsel_reg; |
| + else |
| + reg_addr = rdev->desc->vsel_reg; |
| + |
| + ret = regmap_read(rdev->regmap, reg_addr, ®_val); |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, |
| + "Failed to get mt6315 regulator voltage: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + ret = reg_val & rdev->desc->vsel_mask; |
| + return ret; |
| +} |
| + |
| +static unsigned int mt6315_regulator_get_mode(struct regulator_dev *rdev) |
| +{ |
| + struct mt6315_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret = 0, regval = 0; |
| + |
| + ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, |
| + "Failed to get mt6315 buck mode: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if ((regval & info->modeset_mask) == info->modeset_mask) |
| + return REGULATOR_MODE_FAST; |
| + |
| + ret = regmap_read(rdev->regmap, info->lp_mode_reg, ®val); |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, |
| + "Failed to get mt6315 buck lp mode: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if (regval & info->lp_mode_mask) |
| + return REGULATOR_MODE_IDLE; |
| + else |
| + return REGULATOR_MODE_NORMAL; |
| +} |
| + |
| +static int mt6315_regulator_set_mode(struct regulator_dev *rdev, |
| + unsigned int mode) |
| +{ |
| + struct mt6315_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret = 0, val; |
| + int curr_mode; |
| + |
| + curr_mode = mt6315_regulator_get_mode(rdev); |
| + switch (mode) { |
| + case REGULATOR_MODE_FAST: |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->modeset_reg, |
| + info->modeset_mask, |
| + info->modeset_mask); |
| + break; |
| + case REGULATOR_MODE_NORMAL: |
| + if (curr_mode == REGULATOR_MODE_FAST) { |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->modeset_reg, |
| + info->modeset_mask, |
| + 0); |
| + } else if (curr_mode == REGULATOR_MODE_IDLE) { |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->lp_mode_reg, |
| + info->lp_mode_mask, |
| + 0); |
| + usleep_range(100, 110); |
| + } |
| + break; |
| + case REGULATOR_MODE_IDLE: |
| + val = MT6315_BUCK_MODE_LP >> 1; |
| + val <<= info->lp_mode_shift; |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->lp_mode_reg, |
| + info->lp_mode_mask, |
| + val); |
| + break; |
| + default: |
| + ret = -EINVAL; |
| + goto err_mode; |
| + } |
| + |
| +err_mode: |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, |
| + "Failed to set mt6315 buck mode: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int mt6315_get_status(struct regulator_dev *rdev) |
| +{ |
| + int ret = 0; |
| + u32 regval = 0; |
| + struct mt6315_regulator_info *info = rdev_get_drvdata(rdev); |
| + |
| + ret = regmap_read(rdev->regmap, info->da_reg, ®val); |
| + if (ret != 0) { |
| + dev_notice(&rdev->dev, "Failed to get enable reg: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; |
| +} |
| + |
| +static const struct regulator_ops mt6315_volt_range_ops = { |
| + .list_voltage = regulator_list_voltage_linear_range, |
| + .map_voltage = regulator_map_voltage_linear_range, |
| + .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| + .get_voltage_sel = mt6315_regulator_get_voltage_sel, |
| + .set_voltage_time_sel = regulator_set_voltage_time_sel, |
| + .enable = regulator_enable_regmap, |
| + .disable = regulator_disable_regmap, |
| + .is_enabled = regulator_is_enabled_regmap, |
| + .get_status = mt6315_get_status, |
| + .set_mode = mt6315_regulator_set_mode, |
| + .get_mode = mt6315_regulator_get_mode, |
| +}; |
| + |
| +static struct mt6315_regulator_info mt6315_3_regulators[] = { |
| + MT_BUCK("3_vbuck1", 3_VBUCK1, mt_volt_range1, 1, |
| + MT6315_BUCK_TOP_ELR0, 0x3), |
| + MT_BUCK("3_vbuck3", 3_VBUCK3, mt_volt_range1, 3, |
| + MT6315_BUCK_TOP_ELR4, 0x4), |
| + MT_BUCK("3_vbuck4", 3_VBUCK4, mt_volt_range1, 4, |
| + MT6315_BUCK_TOP_ELR6, 0x8), |
| +}; |
| + |
| +static struct mt6315_regulator_info mt6315_6_regulators[] = { |
| + MT_BUCK("6_vbuck1", 6_VBUCK1, mt_volt_range1, 1, |
| + MT6315_BUCK_TOP_ELR0, 0xB), |
| + MT_BUCK("6_vbuck3", 6_VBUCK3, mt_volt_range1, 3, |
| + MT6315_BUCK_TOP_ELR4, 0x4), |
| +}; |
| + |
| +static struct mt6315_regulator_info mt6315_7_regulators[] = { |
| + MT_BUCK("7_vbuck1", 7_VBUCK1, mt_volt_range1, 1, |
| + MT6315_BUCK_TOP_ELR0, 0x3), |
| + MT_BUCK("7_vbuck3", 7_VBUCK3, mt_volt_range1, 3, |
| + MT6315_BUCK_TOP_ELR4, 0x4), |
| +}; |
| + |
| +static const struct mt_regulator_init_data mt6315_3_regulator_init_data = { |
| + .id = MT6315_SLAVE_ID_3, |
| + .size = MT6315_ID_3_MAX, |
| + .regulator_info = &mt6315_3_regulators[0], |
| +}; |
| + |
| +static const struct mt_regulator_init_data mt6315_6_regulator_init_data = { |
| + .id = MT6315_SLAVE_ID_6, |
| + .size = MT6315_ID_6_MAX, |
| + .regulator_info = &mt6315_6_regulators[0], |
| +}; |
| + |
| +static const struct mt_regulator_init_data mt6315_7_regulator_init_data = { |
| + .id = MT6315_SLAVE_ID_7, |
| + .size = MT6315_ID_7_MAX, |
| + .regulator_info = &mt6315_7_regulators[0], |
| +}; |
| + |
| +static const struct regmap_config mt6315_regmap_config = { |
| + .reg_bits = 16, |
| + .val_bits = 8, |
| + .max_register = 0x16d0, |
| + .fast_io = true, |
| +}; |
| + |
| +static const struct of_device_id mt6315_of_match[] = { |
| + { |
| + .compatible = "mediatek,mt6315_3-regulator", |
| + .data = &mt6315_3_regulator_init_data, |
| + }, { |
| + .compatible = "mediatek,mt6315_6-regulator", |
| + .data = &mt6315_6_regulator_init_data, |
| + }, { |
| + .compatible = "mediatek,mt6315_7-regulator", |
| + .data = &mt6315_7_regulator_init_data, |
| + }, { |
| + /* sentinel */ |
| + }, |
| +}; |
| +MODULE_DEVICE_TABLE(of, mt6315_of_match); |
| + |
| +static int mt6315_regulator_probe(struct spmi_device *pdev) |
| +{ |
| + const struct of_device_id *of_id; |
| + struct device *dev = &pdev->dev; |
| + struct regmap *regmap; |
| + struct mt6315_regulator_info *mt_regulators; |
| + struct mt_regulator_init_data *regulator_init_data; |
| + struct mt6315_chip *chip; |
| + struct regulator_config config = {}; |
| + struct regulator_dev *rdev; |
| + int i; |
| + |
| + regmap = devm_regmap_init_spmi_ext(pdev, &mt6315_regmap_config); |
| + if (!regmap) |
| + return -ENODEV; |
| + |
| + chip = devm_kzalloc(dev, sizeof(struct mt6315_chip), GFP_KERNEL); |
| + if (!chip) |
| + return -ENOMEM; |
| + |
| + of_id = of_match_device(mt6315_of_match, dev); |
| + if (!of_id || !of_id->data) |
| + return -ENODEV; |
| + |
| + regulator_init_data = (struct mt_regulator_init_data *)of_id->data; |
| + mt_regulators = regulator_init_data->regulator_info; |
| + chip->slave_id = regulator_init_data->id; |
| + chip->dev = dev; |
| + chip->regmap = regmap; |
| + mutex_init(&chip->lock); |
| + dev_set_drvdata(dev, chip); |
| + |
| + for (i = 0; i < regulator_init_data->size; i++) { |
| + config.dev = dev; |
| + config.driver_data = (mt_regulators + i); |
| + config.regmap = regmap; |
| + rdev = devm_regulator_register(dev, |
| + &(mt_regulators + i)->desc, &config); |
| + if (IS_ERR(rdev)) { |
| + dev_notice(dev, "failed to register %s\n", |
| + (mt_regulators + i)->desc.name); |
| + continue; |
| + } |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static void mt6315_regulator_shutdown(struct spmi_device *pdev) |
| +{ |
| + struct mt6315_chip *chip = dev_get_drvdata(&pdev->dev); |
| + int ret = 0; |
| + |
| + ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY_H, PROTECTION_KEY_H); |
| + ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY, PROTECTION_KEY); |
| + ret |= regmap_update_bits(chip->regmap, MT6315_TOP2_ELR7, 1, 1); |
| + ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY, 0); |
| + ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY_H, 0); |
| + if (ret < 0) |
| + dev_notice(&pdev->dev, "%s: SLV_%d enable power off sequence failed.\n", |
| + __func__, chip->slave_id); |
| + |
| + return; |
| +} |
| + |
| +static struct spmi_driver mt6315_regulator_driver = { |
| + .driver = { |
| + .name = "mt6315-regulator", |
| + .of_match_table = mt6315_of_match, |
| + }, |
| + .probe = mt6315_regulator_probe, |
| + .shutdown = mt6315_regulator_shutdown, |
| +}; |
| + |
| +module_spmi_driver(mt6315_regulator_driver); |
| + |
| +MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>"); |
| +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6315 PMIC"); |
| +MODULE_LICENSE("GPL"); |
| diff --git a/drivers/regulator/mt6359-regulator.c b/drivers/regulator/mt6359-regulator.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..41934dbcf9f327b2d687210459b0e63288d2f6bd |
| --- /dev/null |
| +++ b/drivers/regulator/mt6359-regulator.c |
| @@ -0,0 +1,1226 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2019 MediaTek Inc. |
| + |
| +#include <linux/platform_device.h> |
| +#include <linux/mfd/mt6359/registers.h> |
| +#include <linux/mfd/mt6359p/registers.h> |
| +#include <linux/mfd/mt6397/core.h> |
| +#include <linux/module.h> |
| +#include <linux/of_device.h> |
| +#include <linux/regmap.h> |
| +#include <linux/regulator/driver.h> |
| +#include <linux/regulator/machine.h> |
| +#include <linux/regulator/mt6359-regulator.h> |
| +#include <linux/regulator/of_regulator.h> |
| + |
| +#define MT6359_BUCK_MODE_AUTO 0 |
| +#define MT6359_BUCK_MODE_FORCE_PWM 1 |
| +#define MT6359_BUCK_MODE_NORMAL 0 |
| +#define MT6359_BUCK_MODE_LP 2 |
| + |
| +/* |
| + * MT6359 regulators' information |
| + * |
| + * @desc: standard fields of regulator description. |
| + * @status_reg: for query status of regulators. |
| + * @qi: Mask for query enable signal status of regulators. |
| + * @modeset_reg: for operating AUTO/PWM mode register. |
| + * @modeset_mask: MASK for operating modeset register. |
| + * @modeset_shift: SHIFT for operating modeset register. |
| + */ |
| +struct mt6359_regulator_info { |
| + struct regulator_desc desc; |
| + u32 status_reg; |
| + u32 qi; |
| + u32 da_vsel_reg; |
| + u32 da_vsel_mask; |
| + u32 da_vsel_shift; |
| + u32 modeset_reg; |
| + u32 modeset_mask; |
| + u32 modeset_shift; |
| + u32 lp_mode_reg; |
| + u32 lp_mode_mask; |
| + u32 lp_mode_shift; |
| +}; |
| + |
| +#define MT6359_BUCK(match, _name, min, max, step, min_sel, \ |
| + volt_ranges, _enable_reg, _status_reg, \ |
| + _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \ |
| + _vsel_reg, _vsel_mask, \ |
| + _lp_mode_reg, _lp_mode_shift, \ |
| + _modeset_reg, _modeset_shift) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_range_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .uV_step = (step), \ |
| + .linear_min_sel = (min_sel), \ |
| + .n_voltages = ((max) - (min)) / (step) + 1, \ |
| + .min_uV = (min), \ |
| + .linear_ranges = volt_ranges, \ |
| + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + .of_map_mode = mt6359_map_mode, \ |
| + }, \ |
| + .da_vsel_reg = _da_vsel_reg, \ |
| + .da_vsel_mask = _da_vsel_mask, \ |
| + .da_vsel_shift = _da_vsel_shift, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| + .lp_mode_reg = _lp_mode_reg, \ |
| + .lp_mode_mask = BIT(_lp_mode_shift), \ |
| + .lp_mode_shift = _lp_mode_shift, \ |
| + .modeset_reg = _modeset_reg, \ |
| + .modeset_mask = BIT(_modeset_shift), \ |
| + .modeset_shift = _modeset_shift \ |
| +} |
| + |
| +#define MT6359_LDO_LINEAR(match, _name, min, max, step, min_sel,\ |
| + volt_ranges, _enable_reg, _status_reg, \ |
| + _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \ |
| + _vsel_reg, _vsel_mask) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_range_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .uV_step = (step), \ |
| + .linear_min_sel = (min_sel), \ |
| + .n_voltages = ((max) - (min)) / (step) + 1, \ |
| + .min_uV = (min), \ |
| + .linear_ranges = volt_ranges, \ |
| + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + }, \ |
| + .da_vsel_reg = _da_vsel_reg, \ |
| + .da_vsel_mask = _da_vsel_mask, \ |
| + .da_vsel_shift = _da_vsel_shift, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359_LDO(match, _name, _volt_table, \ |
| + _enable_reg, _enable_mask, _status_reg, \ |
| + _vsel_reg, _vsel_mask) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_table_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = ARRAY_SIZE(_volt_table), \ |
| + .volt_table = _volt_table, \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(_enable_mask), \ |
| + }, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359_REG_FIXED(match, _name, _enable_reg, \ |
| + _status_reg, _fixed_volt) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_fixed_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = 1, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + .fixed_uV = (_fixed_volt), \ |
| + }, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359P_BUCK(match, _name, min, max, step, min_sel, \ |
| + volt_ranges, _enable_reg, _status_reg, \ |
| + _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \ |
| + _vsel_reg, _vsel_mask, \ |
| + _lp_mode_reg, _lp_mode_shift, \ |
| + _modeset_reg, _modeset_shift) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_range_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .uV_step = (step), \ |
| + .linear_min_sel = (min_sel), \ |
| + .n_voltages = ((max) - (min)) / (step) + 1, \ |
| + .min_uV = (min), \ |
| + .linear_ranges = volt_ranges, \ |
| + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + .of_map_mode = mt6359_map_mode, \ |
| + }, \ |
| + .da_vsel_reg = _da_vsel_reg, \ |
| + .da_vsel_mask = _da_vsel_mask, \ |
| + .da_vsel_shift = _da_vsel_shift, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| + .lp_mode_reg = _lp_mode_reg, \ |
| + .lp_mode_mask = BIT(_lp_mode_shift), \ |
| + .lp_mode_shift = _lp_mode_shift, \ |
| + .modeset_reg = _modeset_reg, \ |
| + .modeset_mask = BIT(_modeset_shift), \ |
| + .modeset_shift = _modeset_shift \ |
| +} |
| + |
| +#define MT6359P_LDO_LINEAR(match, _name, min, max, step, min_sel, \ |
| + volt_ranges, _enable_reg, _status_reg, \ |
| + _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \ |
| + _vsel_reg, _vsel_mask) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_range_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .uV_step = (step), \ |
| + .linear_min_sel = (min_sel), \ |
| + .n_voltages = ((max) - (min)) / (step) + 1, \ |
| + .min_uV = (min), \ |
| + .linear_ranges = volt_ranges, \ |
| + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + }, \ |
| + .da_vsel_reg = _da_vsel_reg, \ |
| + .da_vsel_mask = _da_vsel_mask, \ |
| + .da_vsel_shift = _da_vsel_shift, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359P_LDO(match, _name, _volt_table, \ |
| + _enable_reg, _enable_mask, _status_reg, \ |
| + _vsel_reg, _vsel_mask) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_table_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = ARRAY_SIZE(_volt_table), \ |
| + .volt_table = _volt_table, \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(_enable_mask), \ |
| + }, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359P_LDO1(match, _name, _ops, _volt_table, \ |
| + _enable_reg, _enable_mask, _status_reg, \ |
| + _vsel_reg, _vsel_mask) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = ARRAY_SIZE(_volt_table), \ |
| + .volt_table = _volt_table, \ |
| + .vsel_reg = _vsel_reg, \ |
| + .vsel_mask = _vsel_mask, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(_enable_mask), \ |
| + }, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +#define MT6359P_REG_FIXED(match, _name, _enable_reg, \ |
| + _status_reg, _fixed_volt) \ |
| +[MT6359_ID_##_name] = { \ |
| + .desc = { \ |
| + .name = #_name, \ |
| + .of_match = of_match_ptr(match), \ |
| + .ops = &mt6359_volt_fixed_ops, \ |
| + .type = REGULATOR_VOLTAGE, \ |
| + .id = MT6359_ID_##_name, \ |
| + .owner = THIS_MODULE, \ |
| + .n_voltages = 1, \ |
| + .enable_reg = _enable_reg, \ |
| + .enable_mask = BIT(0), \ |
| + .fixed_uV = (_fixed_volt), \ |
| + }, \ |
| + .status_reg = _status_reg, \ |
| + .qi = BIT(0), \ |
| +} |
| + |
| +static const struct regulator_linear_range mt_volt_range1[] = { |
| + REGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range2[] = { |
| + REGULATOR_LINEAR_RANGE(400000, 0, 0x7f, 6250), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range3[] = { |
| + REGULATOR_LINEAR_RANGE(400000, 0, 0x70, 6250), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range4[] = { |
| + REGULATOR_LINEAR_RANGE(800000, 0, 0x40, 12500), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range5[] = { |
| + REGULATOR_LINEAR_RANGE(500000, 0, 0x3F, 50000), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range6[] = { |
| + REGULATOR_LINEAR_RANGE(500000, 0, 0x6f, 6250), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range7[] = { |
| + REGULATOR_LINEAR_RANGE(500000, 0, 0x60, 6250), |
| +}; |
| + |
| +static const struct regulator_linear_range mt_volt_range8[] = { |
| + REGULATOR_LINEAR_RANGE(506250, 0, 0x7f, 6250), |
| +}; |
| + |
| +static const u32 vsim1_voltages[] = { |
| + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, |
| +}; |
| + |
| +static const u32 vibr_voltages[] = { |
| + 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000, |
| + 0, 3000000, 0, 3300000, |
| +}; |
| + |
| +static const u32 vrf12_voltages[] = { |
| + 0, 0, 1100000, 1200000, 1300000, |
| +}; |
| + |
| +static const u32 volt18_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, |
| +}; |
| + |
| +static const u32 vcn13_voltages[] = { |
| + 900000, 1000000, 0, 1200000, 1300000, |
| +}; |
| + |
| +static const u32 vcn33_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000, |
| +}; |
| + |
| +static const u32 vefuse_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000, |
| +}; |
| + |
| +static const u32 vxo22_voltages[] = { |
| + 1800000, 0, 0, 0, 2200000, |
| +}; |
| + |
| +static const u32 vrfck_voltages[] = { |
| + 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000, |
| +}; |
| + |
| +static const u32 vrfck_voltages_1[] = { |
| + 1240000, 1600000, |
| +}; |
| + |
| +static const u32 vio28_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, |
| +}; |
| + |
| +static const u32 vemc_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000, |
| +}; |
| + |
| +static const u32 vemc_voltages_1[] = { |
| + 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, |
| + 3300000, |
| +}; |
| + |
| +static const u32 va12_voltages[] = { |
| + 0, 0, 0, 0, 0, 0, 1200000, 1300000, |
| +}; |
| + |
| +static const u32 va09_voltages[] = { |
| + 0, 0, 800000, 900000, 0, 0, 1200000, |
| +}; |
| + |
| +static const u32 vrf18_voltages[] = { |
| + 0, 0, 0, 0, 0, 1700000, 1800000, 1810000, |
| +}; |
| + |
| +static const u32 vbbck_voltages[] = { |
| + 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000, |
| +}; |
| + |
| +static const u32 vsim2_voltages[] = { |
| + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, |
| +}; |
| + |
| +static inline unsigned int mt6359_map_mode(unsigned int mode) |
| +{ |
| + switch (mode) { |
| + case MT6359_BUCK_MODE_NORMAL: |
| + return REGULATOR_MODE_NORMAL; |
| + case MT6359_BUCK_MODE_FORCE_PWM: |
| + return REGULATOR_MODE_FAST; |
| + case MT6359_BUCK_MODE_LP: |
| + return REGULATOR_MODE_IDLE; |
| + default: |
| + return REGULATOR_MODE_INVALID; |
| + } |
| +} |
| + |
| +static int mt6359_get_linear_voltage_sel(struct regulator_dev *rdev) |
| +{ |
| + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret, regval; |
| + |
| + ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val); |
| + if (ret != 0) { |
| + dev_err(&rdev->dev, |
| + "Failed to get mt6359 Buck %s vsel reg: %d\n", |
| + info->desc.name, ret); |
| + return ret; |
| + } |
| + |
| + ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask; |
| + |
| + return ret; |
| +} |
| + |
| +static int mt6359_get_status(struct regulator_dev *rdev) |
| +{ |
| + int ret; |
| + u32 regval; |
| + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); |
| + |
| + ret = regmap_read(rdev->regmap, info->status_reg, ®val); |
| + if (ret != 0) { |
| + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if (regval & info->qi) |
| + return REGULATOR_STATUS_ON; |
| + else |
| + return REGULATOR_STATUS_OFF; |
| +} |
| + |
| +static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev) |
| +{ |
| + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret, regval; |
| + |
| + ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); |
| + if (ret != 0) { |
| + dev_err(&rdev->dev, |
| + "Failed to get mt6359 buck mode: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if ((regval & info->modeset_mask) >> info->modeset_shift == |
| + MT6359_BUCK_MODE_FORCE_PWM) |
| + return REGULATOR_MODE_FAST; |
| + |
| + ret = regmap_read(rdev->regmap, info->lp_mode_reg, ®val); |
| + if (ret != 0) { |
| + dev_err(&rdev->dev, |
| + "Failed to get mt6359 buck lp mode: %d\n", ret); |
| + return ret; |
| + } |
| + |
| + if (regval & info->lp_mode_mask) |
| + return REGULATOR_MODE_IDLE; |
| + else |
| + return REGULATOR_MODE_NORMAL; |
| +} |
| + |
| +static int mt6359_regulator_set_mode(struct regulator_dev *rdev, |
| + unsigned int mode) |
| +{ |
| + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); |
| + int ret = 0, val; |
| + int curr_mode; |
| + |
| + curr_mode = mt6359_regulator_get_mode(rdev); |
| + switch (mode) { |
| + case REGULATOR_MODE_FAST: |
| + val = MT6359_BUCK_MODE_FORCE_PWM; |
| + val <<= info->modeset_shift; |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->modeset_reg, |
| + info->modeset_mask, |
| + val); |
| + break; |
| + case REGULATOR_MODE_NORMAL: |
| + if (curr_mode == REGULATOR_MODE_FAST) { |
| + val = MT6359_BUCK_MODE_AUTO; |
| + val <<= info->modeset_shift; |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->modeset_reg, |
| + info->modeset_mask, |
| + val); |
| + } else if (curr_mode == REGULATOR_MODE_IDLE) { |
| + val = MT6359_BUCK_MODE_NORMAL; |
| + val <<= info->lp_mode_shift; |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->lp_mode_reg, |
| + info->lp_mode_mask, |
| + val); |
| + udelay(100); |
| + } |
| + break; |
| + case REGULATOR_MODE_IDLE: |
| + val = MT6359_BUCK_MODE_LP >> 1; |
| + val <<= info->lp_mode_shift; |
| + ret = regmap_update_bits(rdev->regmap, |
| + info->lp_mode_reg, |
| + info->lp_mode_mask, |
| + val); |
| + break; |
| + default: |
| + return -EINVAL; |
| + } |
| + |
| + if (ret != 0) { |
| + dev_err(&rdev->dev, |
| + "Failed to set mt6359 buck mode: %d\n", ret); |
| + } |
| + |
| + return ret; |
| +} |
| + |
| +static int mt6359p_vemc_set_voltage_sel(struct regulator_dev *rdev, |
| + unsigned int sel) |
| +{ |
| + int ret; |
| + unsigned int val = 0; |
| + |
| + sel <<= ffs(rdev->desc->vsel_mask) - 1; |
| + ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, TMA_KEY); |
| + if (ret) |
| + return ret; |
| + |
| + ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); |
| + if (ret) |
| + return ret; |
| + |
| + switch (val) { |
| + case 0: |
| + /* If HW trapping is 0, use VEMC_VOSEL_0 */ |
| + ret = regmap_update_bits(rdev->regmap, |
| + rdev->desc->vsel_reg, |
| + rdev->desc->vsel_mask, sel); |
| + break; |
| + case 1: |
| + /* If HW trapping is 1, use VEMC_VOSEL_1 */ |
| + ret = regmap_update_bits(rdev->regmap, |
| + rdev->desc->vsel_reg + 0x2, |
| + rdev->desc->vsel_mask, sel); |
| + break; |
| + default: |
| + break; |
| + } |
| + if (ret) |
| + return ret; |
| + |
| + ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, 0); |
| + return ret; |
| +} |
| + |
| +static int mt6359p_vemc_get_voltage_sel(struct regulator_dev *rdev) |
| +{ |
| + int ret; |
| + unsigned int val = 0; |
| + |
| + ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); |
| + if (ret) |
| + return ret; |
| + switch (val) { |
| + case 0: |
| + /* If HW trapping is 0, use VEMC_VOSEL_0 */ |
| + ret = regmap_read(rdev->regmap, |
| + rdev->desc->vsel_reg, &val); |
| + break; |
| + case 1: |
| + /* If HW trapping is 1, use VEMC_VOSEL_1 */ |
| + ret = regmap_read(rdev->regmap, |
| + rdev->desc->vsel_reg + 0x2, &val); |
| + break; |
| + default: |
| + return -EINVAL; |
| + } |
| + if (ret) |
| + return ret; |
| + |
| + val &= rdev->desc->vsel_mask; |
| + val >>= ffs(rdev->desc->vsel_mask) - 1; |
| + |
| + return val; |
| +} |
| + |
| +static const struct regulator_ops mt6359_volt_range_ops = { |
| + .list_voltage = regulator_list_voltage_linear_range, |
| + .map_voltage = regulator_map_voltage_linear_range, |
| + .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| + .get_voltage_sel = mt6359_get_linear_voltage_sel, |
| + .set_voltage_time_sel = regulator_set_voltage_time_sel, |
| + .enable = regulator_enable_regmap, |
| + .disable = regulator_disable_regmap, |
| + .is_enabled = regulator_is_enabled_regmap, |
| + .get_status = mt6359_get_status, |
| + .set_mode = mt6359_regulator_set_mode, |
| + .get_mode = mt6359_regulator_get_mode, |
| +}; |
| + |
| +static const struct regulator_ops mt6359_volt_table_ops = { |
| + .list_voltage = regulator_list_voltage_table, |
| + .map_voltage = regulator_map_voltage_iterate, |
| + .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| + .get_voltage_sel = regulator_get_voltage_sel_regmap, |
| + .set_voltage_time_sel = regulator_set_voltage_time_sel, |
| + .enable = regulator_enable_regmap, |
| + .disable = regulator_disable_regmap, |
| + .is_enabled = regulator_is_enabled_regmap, |
| + .get_status = mt6359_get_status, |
| +}; |
| + |
| +static const struct regulator_ops mt6359_volt_fixed_ops = { |
| + .enable = regulator_enable_regmap, |
| + .disable = regulator_disable_regmap, |
| + .is_enabled = regulator_is_enabled_regmap, |
| + .get_status = mt6359_get_status, |
| +}; |
| + |
| +static const struct regulator_ops mt6359p_vemc_ops = { |
| + .list_voltage = regulator_list_voltage_table, |
| + .map_voltage = regulator_map_voltage_iterate, |
| + .set_voltage_sel = mt6359p_vemc_set_voltage_sel, |
| + .get_voltage_sel = mt6359p_vemc_get_voltage_sel, |
| + .set_voltage_time_sel = regulator_set_voltage_time_sel, |
| + .enable = regulator_enable_regmap, |
| + .disable = regulator_disable_regmap, |
| + .is_enabled = regulator_is_enabled_regmap, |
| + .get_status = mt6359_get_status, |
| +}; |
| + |
| +/* The array is indexed by id(MT6359_ID_XXX) */ |
| +static struct mt6359_regulator_info mt6359_regulators[] = { |
| + MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, 0, |
| + mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR, |
| + MT6359_DA_VS1_EN_ADDR, MT6359_DA_VS1_VOSEL_ADDR, |
| + MT6359_DA_VS1_VOSEL_MASK, MT6359_DA_VS1_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VS1_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VS1_VOSEL_MASK << |
| + MT6359_RG_BUCK_VS1_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, |
| + MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), |
| + MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR, |
| + MT6359_DA_VGPU11_EN_ADDR, MT6359_DA_VGPU11_VOSEL_ADDR, |
| + MT6359_DA_VGPU11_VOSEL_MASK, MT6359_DA_VGPU11_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VGPU11_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VGPU11_VOSEL_MASK << |
| + MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VGPU11_LP_ADDR, |
| + MT6359_RG_BUCK_VGPU11_LP_SHIFT, |
| + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, 0, |
| + mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR, |
| + MT6359_DA_VMODEM_EN_ADDR, MT6359_DA_VMODEM_VOSEL_ADDR, |
| + MT6359_DA_VMODEM_VOSEL_MASK, MT6359_DA_VMODEM_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VMODEM_VOSEL_MASK << |
| + MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VMODEM_LP_ADDR, |
| + MT6359_RG_BUCK_VMODEM_LP_SHIFT, |
| + MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR, |
| + MT6359_DA_VPU_EN_ADDR, MT6359_DA_VPU_VOSEL_ADDR, |
| + MT6359_DA_VPU_VOSEL_MASK, MT6359_DA_VPU_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPU_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VPU_VOSEL_MASK << |
| + MT6359_RG_BUCK_VPU_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, |
| + MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vcore", VCORE, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VCORE_EN_ADDR, |
| + MT6359_DA_VCORE_EN_ADDR, MT6359_DA_VCORE_VOSEL_ADDR, |
| + MT6359_DA_VCORE_VOSEL_MASK, MT6359_DA_VCORE_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VCORE_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VCORE_VOSEL_MASK << |
| + MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, |
| + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, 0, |
| + mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR, |
| + MT6359_DA_VS2_EN_ADDR, MT6359_DA_VS2_VOSEL_ADDR, |
| + MT6359_DA_VS2_VOSEL_MASK, MT6359_DA_VS2_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VS2_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VS2_VOSEL_MASK << |
| + MT6359_RG_BUCK_VS2_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, |
| + MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), |
| + MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 0, |
| + mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR, |
| + MT6359_DA_VPA_EN_ADDR, MT6359_DA_VPA_VOSEL_ADDR, |
| + MT6359_DA_VPA_VOSEL_MASK, MT6359_DA_VPA_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPA_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VPA_VOSEL_MASK << |
| + MT6359_RG_BUCK_VPA_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, |
| + MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), |
| + MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR, |
| + MT6359_DA_VPROC2_EN_ADDR, MT6359_DA_VPROC2_VOSEL_ADDR, |
| + MT6359_DA_VPROC2_VOSEL_MASK, MT6359_DA_VPROC2_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VPROC2_VOSEL_MASK << |
| + MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPROC2_LP_ADDR, |
| + MT6359_RG_BUCK_VPROC2_LP_SHIFT, |
| + MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR, |
| + MT6359_DA_VPROC1_EN_ADDR, MT6359_DA_VPROC1_VOSEL_ADDR, |
| + MT6359_DA_VPROC1_VOSEL_MASK, MT6359_DA_VPROC1_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VPROC1_VOSEL_MASK << |
| + MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VPROC1_LP_ADDR, |
| + MT6359_RG_BUCK_VPROC1_LP_SHIFT, |
| + MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), |
| + MT6359_BUCK("buck_vcore_sshub", VCORE_SSHUB, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR, |
| + MT6359_DA_VCORE_EN_ADDR, |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK, |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR, |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK << |
| + MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT, |
| + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, |
| + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), |
| + MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359_RG_LDO_VAUD18_EN_ADDR, |
| + MT6359_DA_VAUD18_B_EN_ADDR, 1800000), |
| + MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, |
| + MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT, |
| + MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR, |
| + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, |
| + MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT, |
| + MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR, |
| + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, |
| + MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT, |
| + MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR, |
| + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT), |
| + MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR, |
| + MT6359_DA_VUSB_B_EN_ADDR, 3000000), |
| + MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1193750, 6250, |
| + 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR, |
| + MT6359_DA_VSRAM_PROC2_B_EN_ADDR, |
| + MT6359_DA_VSRAM_PROC2_VOSEL_ADDR, |
| + MT6359_DA_VSRAM_PROC2_VOSEL_MASK, |
| + MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT, |
| + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << |
| + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, |
| + MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT, |
| + MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR, |
| + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, |
| + MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT, |
| + MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR, |
| + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT), |
| + MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR, |
| + MT6359_DA_VCN18_B_EN_ADDR, 1800000), |
| + MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR, |
| + MT6359_DA_VFE28_B_EN_ADDR, 2800000), |
| + MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, |
| + MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT, |
| + MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR, |
| + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, |
| + MT6359_RG_LDO_VCN33_1_EN_0_ADDR, |
| + MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, |
| + MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR, |
| + MT6359_RG_VCN33_1_VOSEL_MASK << |
| + MT6359_RG_VCN33_1_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, |
| + MT6359_RG_LDO_VCN33_1_EN_1_ADDR, |
| + MT6359_RG_LDO_VCN33_1_EN_1_SHIFT, |
| + MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR, |
| + MT6359_RG_VCN33_1_VOSEL_MASK << |
| + MT6359_RG_VCN33_1_VOSEL_SHIFT), |
| + MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR, |
| + MT6359_DA_VAUX18_B_EN_ADDR, 1800000), |
| + MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1193750, |
| + 6250, 0, mt_volt_range6, |
| + MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR, |
| + MT6359_DA_VSRAM_OTHERS_B_EN_ADDR, |
| + MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR, |
| + MT6359_DA_VSRAM_OTHERS_VOSEL_MASK, |
| + MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT, |
| + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << |
| + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, |
| + MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT, |
| + MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR, |
| + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, |
| + MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT, |
| + MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR, |
| + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages, |
| + MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT, |
| + MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR, |
| + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT), |
| + MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR, |
| + MT6359_DA_VBIF28_B_EN_ADDR, 2800000), |
| + MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, |
| + MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT, |
| + MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR, |
| + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vemc", VEMC, vemc_voltages, |
| + MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT, |
| + MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR, |
| + MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, |
| + MT6359_RG_LDO_VCN33_2_EN_0_ADDR, |
| + MT6359_RG_LDO_VCN33_2_EN_0_SHIFT, |
| + MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR, |
| + MT6359_RG_VCN33_2_VOSEL_MASK << |
| + MT6359_RG_VCN33_2_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, |
| + MT6359_RG_LDO_VCN33_2_EN_1_ADDR, |
| + MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, |
| + MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR, |
| + MT6359_RG_VCN33_2_VOSEL_MASK << |
| + MT6359_RG_VCN33_2_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_va12", VA12, va12_voltages, |
| + MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT, |
| + MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR, |
| + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_va09", VA09, va09_voltages, |
| + MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT, |
| + MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR, |
| + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, |
| + MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT, |
| + MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR, |
| + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT), |
| + MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250, |
| + 0, mt_volt_range7, MT6359_RG_LDO_VSRAM_MD_EN_ADDR, |
| + MT6359_DA_VSRAM_MD_B_EN_ADDR, |
| + MT6359_DA_VSRAM_MD_VOSEL_ADDR, |
| + MT6359_DA_VSRAM_MD_VOSEL_MASK, |
| + MT6359_DA_VSRAM_MD_VOSEL_SHIFT, |
| + MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << |
| + MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, |
| + MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT, |
| + MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR, |
| + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vm18", VM18, volt18_voltages, |
| + MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT, |
| + MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR, |
| + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, |
| + MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT, |
| + MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR, |
| + MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT), |
| + MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1193750, 6250, |
| + 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR, |
| + MT6359_DA_VSRAM_PROC1_B_EN_ADDR, |
| + MT6359_DA_VSRAM_PROC1_VOSEL_ADDR, |
| + MT6359_DA_VSRAM_PROC1_VOSEL_MASK, |
| + MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT, |
| + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << |
| + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), |
| + MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, |
| + MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT, |
| + MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR, |
| + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT), |
| + MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, |
| + 500000, 1193750, 6250, 0, mt_volt_range6, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, |
| + MT6359_DA_VSRAM_OTHERS_B_EN_ADDR, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << |
| + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), |
| +}; |
| + |
| +static struct mt6359_regulator_info mt6359p_regulators[] = { |
| + MT6359P_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, 0, |
| + mt_volt_range1, MT6359P_RG_BUCK_VS1_EN_ADDR, |
| + MT6359P_DA_VS1_EN_ADDR, MT6359P_DA_VS1_VOSEL_ADDR, |
| + MT6359P_DA_VS1_VOSEL_MASK, MT6359P_DA_VS1_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VS1_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VS1_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VS1_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VS1_LP_ADDR, MT6359P_RG_BUCK_VS1_LP_SHIFT, |
| + MT6359P_RG_VS1_FPWM_ADDR, MT6359P_RG_VS1_FPWM_SHIFT), |
| + MT6359P_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359P_RG_BUCK_VGPU11_EN_ADDR, |
| + MT6359P_DA_VGPU11_EN_ADDR, MT6359P_DA_VGPU11_VOSEL_ADDR, |
| + MT6359P_DA_VGPU11_VOSEL_MASK, |
| + MT6359P_DA_VGPU11_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VGPU11_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VGPU11_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VGPU11_LP_ADDR, |
| + MT6359P_RG_BUCK_VGPU11_LP_SHIFT, |
| + MT6359P_RG_VGPU11_FCCM_ADDR, MT6359P_RG_VGPU11_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, 0, |
| + mt_volt_range3, MT6359P_RG_BUCK_VMODEM_EN_ADDR, |
| + MT6359P_DA_VMODEM_EN_ADDR, MT6359P_DA_VMODEM_VOSEL_ADDR, |
| + MT6359P_DA_VMODEM_VOSEL_MASK, |
| + MT6359P_DA_VMODEM_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VMODEM_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VMODEM_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VMODEM_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VMODEM_LP_ADDR, |
| + MT6359P_RG_BUCK_VMODEM_LP_SHIFT, |
| + MT6359P_RG_VMODEM_FCCM_ADDR, MT6359P_RG_VMODEM_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359P_RG_BUCK_VPU_EN_ADDR, |
| + MT6359P_DA_VPU_EN_ADDR, MT6359P_DA_VPU_VOSEL_ADDR, |
| + MT6359P_DA_VPU_VOSEL_MASK, MT6359P_DA_VPU_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPU_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VPU_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VPU_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPU_LP_ADDR, MT6359P_RG_BUCK_VPU_LP_SHIFT, |
| + MT6359P_RG_VPU_FCCM_ADDR, MT6359P_RG_VPU_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250, 0, |
| + mt_volt_range8, MT6359P_RG_BUCK_VCORE_EN_ADDR, |
| + MT6359P_DA_VCORE_EN_ADDR, MT6359P_DA_VCORE_VOSEL_ADDR, |
| + MT6359P_DA_VCORE_VOSEL_MASK, MT6359P_DA_VCORE_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VCORE_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VCORE_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VCORE_LP_ADDR, |
| + MT6359P_RG_BUCK_VCORE_LP_SHIFT, |
| + MT6359P_RG_VCORE_FCCM_ADDR, MT6359P_RG_VCORE_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, 0, |
| + mt_volt_range4, MT6359P_RG_BUCK_VS2_EN_ADDR, |
| + MT6359P_DA_VS2_EN_ADDR, MT6359P_DA_VS2_VOSEL_ADDR, |
| + MT6359P_DA_VS2_VOSEL_MASK, MT6359P_DA_VS2_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VS2_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VS2_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VS2_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VS2_LP_ADDR, MT6359P_RG_BUCK_VS2_LP_SHIFT, |
| + MT6359P_RG_VS2_FPWM_ADDR, MT6359P_RG_VS2_FPWM_SHIFT), |
| + MT6359P_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 0, |
| + mt_volt_range5, MT6359P_RG_BUCK_VPA_EN_ADDR, |
| + MT6359P_DA_VPA_EN_ADDR, MT6359P_DA_VPA_VOSEL_ADDR, |
| + MT6359P_DA_VPA_VOSEL_MASK, MT6359P_DA_VPA_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPA_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VPA_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VPA_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPA_LP_ADDR, MT6359P_RG_BUCK_VPA_LP_SHIFT, |
| + MT6359P_RG_VPA_MODESET_ADDR, MT6359P_RG_VPA_MODESET_SHIFT), |
| + MT6359P_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359P_RG_BUCK_VPROC2_EN_ADDR, |
| + MT6359P_DA_VPROC2_EN_ADDR, MT6359P_DA_VPROC2_VOSEL_ADDR, |
| + MT6359P_DA_VPROC2_VOSEL_MASK, |
| + MT6359P_DA_VPROC2_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPROC2_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VPROC2_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VPROC2_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPROC2_LP_ADDR, |
| + MT6359P_RG_BUCK_VPROC2_LP_SHIFT, |
| + MT6359P_RG_VPROC2_FCCM_ADDR, MT6359P_RG_VPROC2_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, 0, |
| + mt_volt_range2, MT6359P_RG_BUCK_VPROC1_EN_ADDR, |
| + MT6359P_DA_VPROC1_EN_ADDR, MT6359P_DA_VPROC1_VOSEL_ADDR, |
| + MT6359P_DA_VPROC1_VOSEL_MASK, |
| + MT6359P_DA_VPROC1_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPROC1_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VPROC1_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VPROC1_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VPROC1_LP_ADDR, |
| + MT6359P_RG_BUCK_VPROC1_LP_SHIFT, |
| + MT6359P_RG_VPROC1_FCCM_ADDR, MT6359P_RG_VPROC1_FCCM_SHIFT), |
| + MT6359P_BUCK("buck_vcore_sshub", VCORE_SSHUB, 506250, 1300000, 6250, 0, |
| + mt_volt_range2, MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, |
| + MT6359P_DA_VCORE_EN_ADDR, |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK, |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << |
| + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, |
| + MT6359P_RG_BUCK_VCORE_LP_ADDR, |
| + MT6359P_RG_BUCK_VCORE_LP_SHIFT, |
| + MT6359P_RG_VCORE_FCCM_ADDR, MT6359P_RG_VCORE_FCCM_SHIFT), |
| + MT6359P_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR, |
| + MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), |
| + MT6359P_LDO("ldo_vsim1", VSIM1, vsim1_voltages, |
| + MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, |
| + MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, |
| + MT6359P_RG_VSIM1_VOSEL_MASK << |
| + MT6359P_RG_VSIM1_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vibr", VIBR, vibr_voltages, |
| + MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, |
| + MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, |
| + MT6359P_RG_VIBR_VOSEL_MASK << MT6359P_RG_VIBR_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vrf12", VRF12, vrf12_voltages, |
| + MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, |
| + MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, |
| + MT6359P_RG_VRF12_VOSEL_MASK << |
| + MT6359P_RG_VRF12_VOSEL_SHIFT), |
| + MT6359P_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR, |
| + MT6359P_DA_VUSB_B_EN_ADDR, 3000000), |
| + MT6359P_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1193750, |
| + 6250, 0, mt_volt_range6, |
| + MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, |
| + MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, |
| + MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR, |
| + MT6359P_DA_VSRAM_PROC2_VOSEL_MASK, |
| + MT6359P_DA_VSRAM_PROC2_VOSEL_SHIFT, |
| + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_MASK << |
| + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vio18", VIO18, volt18_voltages, |
| + MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, |
| + MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, |
| + MT6359P_RG_VIO18_VOSEL_MASK << |
| + MT6359P_RG_VIO18_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vcamio", VCAMIO, volt18_voltages, |
| + MT6359P_RG_LDO_VCAMIO_EN_ADDR, |
| + MT6359P_RG_LDO_VCAMIO_EN_SHIFT, |
| + MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, |
| + MT6359P_RG_VCAMIO_VOSEL_MASK << |
| + MT6359P_RG_VCAMIO_VOSEL_SHIFT), |
| + MT6359P_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR, |
| + MT6359P_DA_VCN18_B_EN_ADDR, 1800000), |
| + MT6359P_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR, |
| + MT6359P_DA_VFE28_B_EN_ADDR, 2800000), |
| + MT6359P_LDO("ldo_vcn13", VCN13, vcn13_voltages, |
| + MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, |
| + MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, |
| + MT6359P_RG_VCN13_VOSEL_MASK << |
| + MT6359P_RG_VCN13_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, |
| + MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, |
| + MT6359P_RG_LDO_VCN33_1_EN_0_SHIFT, |
| + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, |
| + MT6359P_RG_VCN33_1_VOSEL_MASK << |
| + MT6359P_RG_VCN33_1_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, |
| + MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, |
| + MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT, |
| + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, |
| + MT6359P_RG_VCN33_1_VOSEL_MASK << |
| + MT6359P_RG_VCN33_1_VOSEL_SHIFT), |
| + MT6359P_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR, |
| + MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), |
| + MT6359P_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1193750, |
| + 6250, 0, mt_volt_range6, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, |
| + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, |
| + MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR, |
| + MT6359P_DA_VSRAM_OTHERS_VOSEL_MASK, |
| + MT6359P_DA_VSRAM_OTHERS_VOSEL_SHIFT, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << |
| + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, |
| + MT6359P_RG_LDO_VEFUSE_EN_ADDR, |
| + MT6359P_RG_LDO_VEFUSE_EN_SHIFT, |
| + MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, |
| + MT6359P_RG_VEFUSE_VOSEL_MASK << |
| + MT6359P_RG_VEFUSE_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vxo22", VXO22, vxo22_voltages, |
| + MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, |
| + MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, |
| + MT6359P_RG_VXO22_VOSEL_MASK << |
| + MT6359P_RG_VXO22_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1, |
| + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, |
| + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, |
| + MT6359P_RG_VRFCK_VOSEL_MASK << |
| + MT6359P_RG_VRFCK_VOSEL_SHIFT), |
| + MT6359P_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR, |
| + MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), |
| + MT6359P_LDO("ldo_vio28", VIO28, vio28_voltages, |
| + MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, |
| + MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, |
| + MT6359P_RG_VIO28_VOSEL_MASK << |
| + MT6359P_RG_VIO28_VOSEL_SHIFT), |
| + MT6359P_LDO1("ldo_vemc_1", VEMC, mt6359p_vemc_ops, vemc_voltages_1, |
| + MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, |
| + MT6359P_DA_VEMC_B_EN_ADDR, |
| + MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, |
| + MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << |
| + MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), |
| + MT6359P_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, |
| + MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, |
| + MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, |
| + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, |
| + MT6359P_RG_VCN33_2_VOSEL_MASK << |
| + MT6359P_RG_VCN33_2_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, |
| + MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, |
| + MT6359P_RG_LDO_VCN33_2_EN_1_SHIFT, |
| + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, |
| + MT6359P_RG_VCN33_2_VOSEL_MASK << |
| + MT6359P_RG_VCN33_2_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_va12", VA12, va12_voltages, |
| + MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, |
| + MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, |
| + MT6359P_RG_VA12_VOSEL_MASK << MT6359P_RG_VA12_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_va09", VA09, va09_voltages, |
| + MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, |
| + MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, |
| + MT6359P_RG_VA09_VOSEL_MASK << MT6359P_RG_VA09_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vrf18", VRF18, vrf18_voltages, |
| + MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, |
| + MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, |
| + MT6359P_RG_VRF18_VOSEL_MASK << |
| + MT6359P_RG_VRF18_VOSEL_SHIFT), |
| + MT6359P_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250, |
| + 0, mt_volt_range7, MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, |
| + MT6359P_DA_VSRAM_MD_B_EN_ADDR, |
| + MT6359P_DA_VSRAM_MD_VOSEL_ADDR, |
| + MT6359P_DA_VSRAM_MD_VOSEL_MASK, |
| + MT6359P_DA_VSRAM_MD_VOSEL_SHIFT, |
| + MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_MD_VOSEL_MASK << |
| + MT6359P_RG_LDO_VSRAM_MD_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vufs", VUFS, volt18_voltages, |
| + MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, |
| + MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, |
| + MT6359P_RG_VUFS_VOSEL_MASK << MT6359P_RG_VUFS_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vm18", VM18, volt18_voltages, |
| + MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, |
| + MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, |
| + MT6359P_RG_VM18_VOSEL_MASK << MT6359P_RG_VM18_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vbbck", VBBCK, vbbck_voltages, |
| + MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, |
| + MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, |
| + MT6359P_RG_VBBCK_VOSEL_MASK << |
| + MT6359P_RG_VBBCK_VOSEL_SHIFT), |
| + MT6359P_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1193750, |
| + 6250, 0, mt_volt_range6, |
| + MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, |
| + MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, |
| + MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR, |
| + MT6359P_DA_VSRAM_PROC1_VOSEL_MASK, |
| + MT6359P_DA_VSRAM_PROC1_VOSEL_SHIFT, |
| + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_MASK << |
| + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), |
| + MT6359P_LDO("ldo_vsim2", VSIM2, vsim2_voltages, |
| + MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, |
| + MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, |
| + MT6359P_RG_VSIM2_VOSEL_MASK << |
| + MT6359P_RG_VSIM2_VOSEL_SHIFT), |
| + MT6359P_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, |
| + 500000, 1193750, 6250, 0, mt_volt_range6, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, |
| + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << |
| + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), |
| +}; |
| + |
| +static int mt6359_regulator_probe(struct platform_device *pdev) |
| +{ |
| + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); |
| + struct regulator_config config = {}; |
| + struct regulator_dev *rdev; |
| + struct mt6359_regulator_info *mt6359_info; |
| + int i, hw_ver; |
| + |
| + regmap_read(mt6397->regmap, MT6359P_HWCID, &hw_ver); |
| + if (hw_ver == MT6359P_CHIP_VER) |
| + mt6359_info = mt6359p_regulators; |
| + else |
| + mt6359_info = mt6359_regulators; |
| + |
| + for (i = 0; i < MT6359_MAX_REGULATOR; i++, mt6359_info++) { |
| + config.dev = &pdev->dev; |
| + config.driver_data = mt6359_info; |
| + config.regmap = mt6397->regmap; |
| + |
| + rdev = devm_regulator_register(&pdev->dev, |
| + &mt6359_info->desc, |
| + &config); |
| + if (IS_ERR(rdev)) { |
| + dev_err(&pdev->dev, "failed to register %s\n", |
| + mt6359_info->desc.name); |
| + return PTR_ERR(rdev); |
| + } |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static const struct platform_device_id mt6359_platform_ids[] = { |
| + {"mt6359-regulator", 0}, |
| + { /* sentinel */ }, |
| +}; |
| +MODULE_DEVICE_TABLE(platform, mt6359_platform_ids); |
| + |
| +static struct platform_driver mt6359_regulator_driver = { |
| + .driver = { |
| + .name = "mt6359-regulator", |
| + }, |
| + .probe = mt6359_regulator_probe, |
| + .id_table = mt6359_platform_ids, |
| +}; |
| + |
| +module_platform_driver(mt6359_regulator_driver); |
| + |
| +MODULE_AUTHOR("Wen Su <wen.su@mediatek.com>"); |
| +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6359 PMIC"); |
| +MODULE_LICENSE("GPL"); |
| diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig |
| index 59a56cd790ec313347b3ba822c124de9183916e0..3f5e5cb12b05a4bdab0e19e0ef2ca6e473b12b89 100644 |
| --- a/drivers/soc/mediatek/Kconfig |
| +++ b/drivers/soc/mediatek/Kconfig |
| @@ -10,21 +10,12 @@ config MTK_CMDQ |
| depends on ARCH_MEDIATEK || COMPILE_TEST |
| select MAILBOX |
| select MTK_CMDQ_MBOX |
| - select MTK_INFRACFG |
| help |
| Say yes here to add support for the MediaTek Command Queue (CMDQ) |
| driver. The CMDQ is used to help read/write registers with critical |
| time limitation, such as updating display configuration during the |
| vblank. |
| |
| -config MTK_INFRACFG |
| - bool "MediaTek INFRACFG Support" |
| - select REGMAP |
| - help |
| - Say yes here to add support for the MediaTek INFRACFG controller. The |
| - INFRACFG controller contains various infrastructure registers not |
| - directly associated to any device. |
| - |
| config MTK_PMIC_WRAP |
| tristate "MediaTek PMIC Wrapper Support" |
| depends on RESET_CONTROLLER |
| @@ -38,7 +29,6 @@ config MTK_SCPSYS |
| bool "MediaTek SCPSYS Support" |
| default ARCH_MEDIATEK |
| select REGMAP |
| - select MTK_INFRACFG |
| select PM_GENERIC_DOMAINS if PM |
| help |
| Say yes here to add support for the MediaTek SCPSYS power domain |
| diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile |
| index 01f9f873634a50fd60be23a90417236c17d0917b..2afa7b9a1adec872b02a3eb8373a782bfb6e65c4 100644 |
| --- a/drivers/soc/mediatek/Makefile |
| +++ b/drivers/soc/mediatek/Makefile |
| @@ -1,6 +1,5 @@ |
| # SPDX-License-Identifier: GPL-2.0-only |
| obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o |
| -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o |
| obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o |
| obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o |
| obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o |
| diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c |
| deleted file mode 100644 |
| index 341c7ac250e3a235a6ebb73c6b610bb4679424da..0000000000000000000000000000000000000000 |
| --- a/drivers/soc/mediatek/mtk-infracfg.c |
| +++ /dev/null |
| @@ -1,79 +0,0 @@ |
| -// SPDX-License-Identifier: GPL-2.0-only |
| -/* |
| - * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de> |
| - */ |
| - |
| -#include <linux/export.h> |
| -#include <linux/jiffies.h> |
| -#include <linux/regmap.h> |
| -#include <linux/soc/mediatek/infracfg.h> |
| -#include <asm/processor.h> |
| - |
| -#define MTK_POLL_DELAY_US 10 |
| -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) |
| - |
| -#define INFRA_TOPAXI_PROTECTEN 0x0220 |
| -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 |
| -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 |
| -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 |
| - |
| -/** |
| - * mtk_infracfg_set_bus_protection - enable bus protection |
| - * @regmap: The infracfg regmap |
| - * @mask: The mask containing the protection bits to be enabled. |
| - * @reg_update: The boolean flag determines to set the protection bits |
| - * by regmap_update_bits with enable register(PROTECTEN) or |
| - * by regmap_write with set register(PROTECTEN_SET). |
| - * |
| - * This function enables the bus protection bits for disabled power |
| - * domains so that the system does not hang when some unit accesses the |
| - * bus while in power down. |
| - */ |
| -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, |
| - bool reg_update) |
| -{ |
| - u32 val; |
| - int ret; |
| - |
| - if (reg_update) |
| - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, |
| - mask); |
| - else |
| - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); |
| - |
| - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, |
| - val, (val & mask) == mask, |
| - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
| - |
| - return ret; |
| -} |
| - |
| -/** |
| - * mtk_infracfg_clear_bus_protection - disable bus protection |
| - * @regmap: The infracfg regmap |
| - * @mask: The mask containing the protection bits to be disabled. |
| - * @reg_update: The boolean flag determines to clear the protection bits |
| - * by regmap_update_bits with enable register(PROTECTEN) or |
| - * by regmap_write with clear register(PROTECTEN_CLR). |
| - * |
| - * This function disables the bus protection bits previously enabled with |
| - * mtk_infracfg_set_bus_protection. |
| - */ |
| - |
| -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, |
| - bool reg_update) |
| -{ |
| - int ret; |
| - u32 val; |
| - |
| - if (reg_update) |
| - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); |
| - else |
| - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); |
| - |
| - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, |
| - val, !(val & mask), |
| - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
| - |
| - return ret; |
| -} |
| diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c |
| index 05e322c9c301ad911f5bce978387553ad4262650..161d11df2b7ce7cd1c55c4acdbaa5b91fe10ab69 100644 |
| --- a/drivers/soc/mediatek/mtk-mmsys.c |
| +++ b/drivers/soc/mediatek/mtk-mmsys.c |
| @@ -33,68 +33,210 @@ |
| #define DISP_REG_CONFIG_DSI_SEL 0x050 |
| #define DISP_REG_CONFIG_DPI_SEL 0x064 |
| |
| -#define OVL0_MOUT_EN_COLOR0 0x1 |
| -#define OD_MOUT_EN_RDMA0 0x1 |
| -#define OD1_MOUT_EN_RDMA1 BIT(16) |
| -#define UFOE_MOUT_EN_DSI0 0x1 |
| -#define COLOR0_SEL_IN_OVL0 0x1 |
| -#define OVL1_MOUT_EN_COLOR1 0x1 |
| -#define GAMMA_MOUT_EN_RDMA1 0x1 |
| -#define RDMA0_SOUT_DPI0 0x2 |
| -#define RDMA0_SOUT_DPI1 0x3 |
| -#define RDMA0_SOUT_DSI1 0x1 |
| -#define RDMA0_SOUT_DSI2 0x4 |
| -#define RDMA0_SOUT_DSI3 0x5 |
| -#define RDMA1_SOUT_DPI0 0x2 |
| -#define RDMA1_SOUT_DPI1 0x3 |
| -#define RDMA1_SOUT_DSI1 0x1 |
| -#define RDMA1_SOUT_DSI2 0x4 |
| -#define RDMA1_SOUT_DSI3 0x5 |
| -#define RDMA2_SOUT_DPI0 0x2 |
| -#define RDMA2_SOUT_DPI1 0x3 |
| -#define RDMA2_SOUT_DSI1 0x1 |
| -#define RDMA2_SOUT_DSI2 0x4 |
| -#define RDMA2_SOUT_DSI3 0x5 |
| -#define DPI0_SEL_IN_RDMA1 0x1 |
| -#define DPI0_SEL_IN_RDMA2 0x3 |
| -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) |
| -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) |
| -#define DSI0_SEL_IN_RDMA1 0x1 |
| -#define DSI0_SEL_IN_RDMA2 0x4 |
| -#define DSI1_SEL_IN_RDMA1 0x1 |
| -#define DSI1_SEL_IN_RDMA2 0x4 |
| -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) |
| -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) |
| -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) |
| -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) |
| -#define COLOR1_SEL_IN_OVL1 0x1 |
| - |
| -#define OVL_MOUT_EN_RDMA 0x1 |
| -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 |
| -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 |
| -#define DSI_SEL_IN_BLS 0x0 |
| -#define DPI_SEL_IN_BLS 0x0 |
| -#define DSI_SEL_IN_RDMA 0x1 |
| +#define MT8183_DISP_OVL0_MOUT_EN 0xf00 |
| +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04 |
| +#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08 |
| +#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c |
| +#define MT8183_DISP_PATH0_SEL_IN 0xf24 |
| +#define MT8183_DISP_DSI0_SEL_IN 0xf2c |
| +#define MT8183_DISP_DPI0_SEL_IN 0xf30 |
| +#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50 |
| +#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54 |
| + |
| +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) |
| +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) |
| +#define DITHER0_MOUT_IN_DSI0 BIT(0) |
| +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 |
| +#define DSI0_SEL_IN_RDMA0 0x1 |
| +#define MT8183_DSI0_SEL_IN_RDMA1 0x3 |
| +#define MT8183_DPI0_SEL_IN_RDMA0 0x1 |
| +#define MT8183_DPI0_SEL_IN_RDMA1 0x2 |
| +#define MT8183_RDMA0_SOUT_COLOR0 0x1 |
| +#define MT8183_RDMA1_SOUT_DSI0 0x1 |
| + |
| +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 |
| +#define DISP_OVL0_GO_BLEND BIT(0) |
| +#define DISP_OVL0_GO_BG BIT(1) |
| +#define DISP_OVL0_2L_GO_BLEND BIT(2) |
| +#define DISP_OVL0_2L_GO_BG BIT(3) |
| +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 |
| +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c |
| +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) |
| +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c |
| +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 |
| +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 |
| +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 |
| +#define MT8192_CCORR0_SOUT_AAL0 0x1 |
| +#define MT8192_DISP_AAL0_SEL_IN 0xf38 |
| +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 |
| +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c |
| +#define MT8192_DITHER0_MOUT_DSI0 BIT(0) |
| +#define MT8192_DISP_DSI0_SEL_IN 0xf40 |
| +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 |
| + |
| + |
| +#define OVL0_MOUT_EN_COLOR0 0x1 |
| +#define OD_MOUT_EN_RDMA0 0x1 |
| +#define OD1_MOUT_EN_RDMA1 BIT(16) |
| +#define UFOE_MOUT_EN_DSI0 0x1 |
| +#define COLOR0_SEL_IN_OVL0 0x1 |
| +#define OVL1_MOUT_EN_COLOR1 0x1 |
| +#define GAMMA_MOUT_EN_RDMA1 0x1 |
| +#define RDMA0_SOUT_DPI0 0x2 |
| +#define RDMA0_SOUT_DPI1 0x3 |
| +#define RDMA0_SOUT_DSI1 0x1 |
| +#define RDMA0_SOUT_DSI2 0x4 |
| +#define RDMA0_SOUT_DSI3 0x5 |
| +#define RDMA1_SOUT_DPI0 0x2 |
| +#define RDMA1_SOUT_DPI1 0x3 |
| +#define RDMA1_SOUT_DSI1 0x1 |
| +#define RDMA1_SOUT_DSI2 0x4 |
| +#define RDMA1_SOUT_DSI3 0x5 |
| +#define RDMA2_SOUT_DPI0 0x2 |
| +#define RDMA2_SOUT_DPI1 0x3 |
| +#define RDMA2_SOUT_DSI1 0x1 |
| +#define RDMA2_SOUT_DSI2 0x4 |
| +#define RDMA2_SOUT_DSI3 0x5 |
| +#define DPI0_SEL_IN_RDMA1 0x1 |
| +#define DPI0_SEL_IN_RDMA2 0x3 |
| +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) |
| +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) |
| +#define DSI0_SEL_IN_RDMA1 0x1 |
| +#define DSI0_SEL_IN_RDMA2 0x4 |
| +#define DSI1_SEL_IN_RDMA1 0x1 |
| +#define DSI1_SEL_IN_RDMA2 0x4 |
| +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) |
| +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) |
| +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) |
| +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) |
| +#define COLOR1_SEL_IN_OVL1 0x1 |
| + |
| +#define OVL_MOUT_EN_RDMA 0x1 |
| +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 |
| +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 |
| +#define DSI_SEL_IN_BLS 0x0 |
| +#define DPI_SEL_IN_BLS 0x0 |
| +#define DSI_SEL_IN_RDMA 0x1 |
| + |
| +#define OVL0_MOUT_EN_OVL0_2L BIT(4) |
| + |
| +struct mtk_mmsys_reg_data { |
| + u32 ovl0_mout_en; |
| + u32 ovl0_mout_en_ovl0_2l; |
| + u32 ovl0_2l_mout_en; |
| + u32 ovl0_2l_mout_en_rdma0; |
| + u32 rdma0_sel_in; |
| + u32 rdma0_sel_in_ovl0_2l; |
| + u32 rdma0_sout_sel_in; |
| + u32 rdma0_sout_color0; |
| + u32 ccorr0_sout_sel; |
| + u32 ccorr0_sout_aal0; |
| + u32 aal0_sel_in; |
| + u32 aal0_sel_in_ccorr0; |
| + u32 dither0_mout_en; |
| + u32 dither0_mout_dsi0; |
| + u32 rdma1_sout_sel_in; |
| + u32 rdma1_sout_dpi0; |
| + u32 rdma1_sout_dsi0; |
| + u32 dpi0_sel_in; |
| + u32 dpi0_sel_in_rdma1; |
| + u32 dsi0_sel_in; |
| + u32 dsi0_sel_in_rdma0; |
| + u32 dsi0_sel_in_dither0; |
| + u32 dsi0_sel_in_rdma1; |
| + u32 mmsys_ovl_con; |
| +}; |
| |
| struct mtk_mmsys_driver_data { |
| const char *clk_driver; |
| + const struct mtk_mmsys_reg_data *reg_data; |
| +}; |
| + |
| +struct mtk_mmsys_private_data { |
| + void __iomem *config_regs; |
| + const struct mtk_mmsys_driver_data *data; |
| +}; |
| + |
| +const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = { |
| + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, |
| + .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, |
| + .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0, |
| + .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN, |
| + .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1, |
| + .dsi0_sel_in = DISP_REG_CONFIG_DSIE_SEL_IN, |
| + .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1, |
| +}; |
| + |
| +const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data = { |
| + .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, |
| + .ovl0_mout_en_ovl0_2l = OVL0_MOUT_EN_OVL0_2L, |
| + .ovl0_2l_mout_en = MT8183_DISP_OVL0_2L_MOUT_EN, |
| + .ovl0_2l_mout_en_rdma0 = OVL0_2L_MOUT_EN_DISP_PATH0, |
| + .rdma0_sel_in = MT8183_DISP_PATH0_SEL_IN, |
| + .rdma0_sel_in_ovl0_2l = DISP_PATH0_SEL_IN_OVL0_2L, |
| + .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, |
| + .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, |
| + .dither0_mout_en = MT8183_DISP_DITHER0_MOUT_EN, |
| + .dither0_mout_dsi0 = DITHER0_MOUT_IN_DSI0, |
| + .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, |
| + .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, |
| + .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, |
| + .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, |
| + .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, |
| + .dsi0_sel_in_rdma0 = DSI0_SEL_IN_RDMA0, |
| + .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, |
| +}; |
| + |
| +const struct mtk_mmsys_reg_data mt8192_mmsys_reg_data = { |
| + .ovl0_mout_en = MT8192_DISP_OVL0_MOUT_EN, |
| + .ovl0_2l_mout_en = MT8192_DISP_OVL0_2L_MOUT_EN, |
| + .ovl0_2l_mout_en_rdma0 = OVL0_MOUT_EN_DISP_RDMA0, |
| + .rdma0_sel_in = MT8192_DISP_RDMA0_SEL_IN, |
| + .rdma0_sel_in_ovl0_2l = MT8192_RDMA0_SEL_IN_OVL0_2L, |
| + .rdma0_sout_sel_in = MT8192_DISP_RDMA0_SOUT_SEL, |
| + .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, |
| + .ccorr0_sout_sel = MT8192_DISP_CCORR0_SOUT_SEL, |
| + .ccorr0_sout_aal0 = MT8192_CCORR0_SOUT_AAL0, |
| + .aal0_sel_in = MT8192_DISP_AAL0_SEL_IN, |
| + .aal0_sel_in_ccorr0 = MT8192_AAL0_SEL_IN_CCORR0, |
| + .dither0_mout_en = MT8192_DISP_DITHER0_MOUT_EN, |
| + .dither0_mout_dsi0 = DITHER0_MOUT_IN_DSI0, |
| + .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, |
| + .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, |
| + .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, |
| + .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, |
| + .dsi0_sel_in = MT8192_DISP_DSI0_SEL_IN, |
| + .dsi0_sel_in_dither0 = MT8192_DSI0_SEL_IN_DITHER0, |
| + .mmsys_ovl_con = MT8192_MMSYS_OVL_MOUT_EN, |
| }; |
| |
| static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { |
| .clk_driver = "clk-mt8173-mm", |
| + .reg_data = &mt8173_mmsys_reg_data, |
| +}; |
| + |
| +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { |
| + .clk_driver = "clk-mt8183-mm", |
| + .reg_data = &mt8183_mmsys_reg_data, |
| }; |
| |
| -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, |
| +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { |
| + .clk_driver = "clk-mt8192-mm", |
| + .reg_data = &mt8192_mmsys_reg_data, |
| +}; |
| + |
| +static unsigned int mtk_mmsys_ddp_mout_en(const struct mtk_mmsys_reg_data *data, |
| + enum mtk_ddp_comp_id cur, |
| enum mtk_ddp_comp_id next, |
| unsigned int *addr) |
| -{ |
| + { |
| unsigned int value; |
| |
| if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { |
| - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; |
| + *addr = data->ovl0_mout_en; |
| value = OVL0_MOUT_EN_COLOR0; |
| } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { |
| - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; |
| + *addr = data->ovl0_mout_en; |
| value = OVL_MOUT_EN_RDMA; |
| } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { |
| *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; |
| @@ -111,51 +253,20 @@ static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, |
| } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { |
| *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; |
| value = OD1_MOUT_EN_RDMA1; |
| - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| - value = RDMA0_SOUT_DPI0; |
| - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| - value = RDMA0_SOUT_DPI1; |
| - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| - value = RDMA0_SOUT_DSI1; |
| - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| - value = RDMA0_SOUT_DSI2; |
| - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| - value = RDMA0_SOUT_DSI3; |
| - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| - value = RDMA1_SOUT_DSI1; |
| - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| - value = RDMA1_SOUT_DSI2; |
| - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| - value = RDMA1_SOUT_DSI3; |
| - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| - value = RDMA1_SOUT_DPI0; |
| - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| - value = RDMA1_SOUT_DPI1; |
| - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| - value = RDMA2_SOUT_DPI0; |
| - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| - value = RDMA2_SOUT_DPI1; |
| - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| - value = RDMA2_SOUT_DSI1; |
| - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| - value = RDMA2_SOUT_DSI2; |
| - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { |
| - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| - value = RDMA2_SOUT_DSI3; |
| + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { |
| + *addr = data->ovl0_mout_en; |
| + value = data->ovl0_mout_en_ovl0_2l; |
| + } else if (cur == DDP_COMPONENT_OVL_2L0 && |
| + next == DDP_COMPONENT_RDMA0) { |
| + *addr = data->ovl0_2l_mout_en; |
| + value = data->ovl0_2l_mout_en_rdma0; |
| + } else if (cur == DDP_COMPONENT_OVL_2L1 && |
| + next == DDP_COMPONENT_RDMA1) { |
| + *addr = MT8183_DISP_OVL1_2L_MOUT_EN; |
| + value = OVL1_2L_MOUT_EN_RDMA1; |
| + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { |
| + *addr = data->dither0_mout_en; |
| + value = data->dither0_mout_dsi0; |
| } else { |
| value = 0; |
| } |
| @@ -163,7 +274,33 @@ static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, |
| return value; |
| } |
| |
| -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, |
| +static int mtk_mmsys_ovl_mout_en(const struct mtk_mmsys_reg_data *data, |
| + enum mtk_ddp_comp_id cur, |
| + enum mtk_ddp_comp_id next, |
| + unsigned int *addr) |
| +{ |
| + int value = -1; |
| + |
| + *addr = data->mmsys_ovl_con; |
| + if (!*addr) |
| + return value; |
| + |
| + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) |
| + value = DISP_OVL0_GO_BG; |
| + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) |
| + value = DISP_OVL0_2L_GO_BG; |
| + else if (cur == DDP_COMPONENT_OVL0) |
| + value = DISP_OVL0_GO_BLEND; |
| + else if (cur == DDP_COMPONENT_OVL_2L0) |
| + value = DISP_OVL0_2L_GO_BLEND; |
| + else |
| + value = -1; |
| + |
| + return value; |
| +} |
| + |
| +static unsigned int mtk_mmsys_ddp_sel_in(const struct mtk_mmsys_reg_data *data, |
| + enum mtk_ddp_comp_id cur, |
| enum mtk_ddp_comp_id next, |
| unsigned int *addr) |
| { |
| @@ -173,14 +310,14 @@ static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, |
| *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; |
| value = COLOR0_SEL_IN_OVL0; |
| } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { |
| - *addr = DISP_REG_CONFIG_DPI_SEL_IN; |
| - value = DPI0_SEL_IN_RDMA1; |
| + *addr = data->dpi0_sel_in; |
| + value = data->dpi0_sel_in_rdma1; |
| } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { |
| *addr = DISP_REG_CONFIG_DPI_SEL_IN; |
| value = DPI1_SEL_IN_RDMA1; |
| } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { |
| - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; |
| - value = DSI0_SEL_IN_RDMA1; |
| + *addr = data->dsi0_sel_in; |
| + value = data->dsi0_sel_in_rdma1; |
| } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { |
| *addr = DISP_REG_CONFIG_DSIO_SEL_IN; |
| value = DSI1_SEL_IN_RDMA1; |
| @@ -214,6 +351,19 @@ static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, |
| } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { |
| *addr = DISP_REG_CONFIG_DSI_SEL; |
| value = DSI_SEL_IN_BLS; |
| + } else if (cur == DDP_COMPONENT_OVL_2L0 && |
| + next == DDP_COMPONENT_RDMA0) { |
| + *addr = data->rdma0_sel_in; |
| + value = data->rdma0_sel_in_ovl0_2l; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { |
| + *addr = data->dsi0_sel_in; |
| + value = data->dsi0_sel_in_rdma0; |
| + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { |
| + *addr = data->aal0_sel_in; |
| + value = data->aal0_sel_in_ccorr0; |
| + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { |
| + *addr = data->dsi0_sel_in; |
| + value = data->dsi0_sel_in_dither0; |
| } else { |
| value = 0; |
| } |
| @@ -221,43 +371,113 @@ static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, |
| return value; |
| } |
| |
| -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, |
| - enum mtk_ddp_comp_id cur, |
| - enum mtk_ddp_comp_id next) |
| + |
| +static unsigned int mtk_mmsys_ddp_sout_sel(const struct mtk_mmsys_reg_data *data, |
| + enum mtk_ddp_comp_id cur, |
| + enum mtk_ddp_comp_id next, |
| + unsigned int *addr) |
| { |
| + unsigned int value; |
| + |
| if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { |
| - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, |
| - config_regs + DISP_REG_CONFIG_OUT_SEL); |
| + *addr = DISP_REG_CONFIG_OUT_SEL; |
| + value = BLS_TO_DSI_RDMA1_TO_DPI1; |
| } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { |
| - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, |
| - config_regs + DISP_REG_CONFIG_OUT_SEL); |
| - writel_relaxed(DSI_SEL_IN_RDMA, |
| - config_regs + DISP_REG_CONFIG_DSI_SEL); |
| - writel_relaxed(DPI_SEL_IN_BLS, |
| - config_regs + DISP_REG_CONFIG_DPI_SEL); |
| + *addr = DISP_REG_CONFIG_OUT_SEL; |
| + value = BLS_TO_DPI_RDMA1_TO_DSI; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| + value = RDMA0_SOUT_DPI0; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| + value = RDMA0_SOUT_DPI1; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| + value = RDMA0_SOUT_DSI1; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| + value = RDMA0_SOUT_DSI2; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; |
| + value = RDMA0_SOUT_DSI3; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| + value = RDMA1_SOUT_DSI1; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| + value = RDMA1_SOUT_DSI2; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| + value = RDMA1_SOUT_DSI3; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { |
| + *addr = data->rdma1_sout_sel_in; |
| + value = data->rdma1_sout_dpi0; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; |
| + value = RDMA1_SOUT_DPI1; |
| + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| + value = RDMA2_SOUT_DPI0; |
| + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| + value = RDMA2_SOUT_DPI1; |
| + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| + value = RDMA2_SOUT_DSI1; |
| + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| + value = RDMA2_SOUT_DSI2; |
| + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { |
| + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; |
| + value = RDMA2_SOUT_DSI3; |
| + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { |
| + *addr = data->rdma0_sout_sel_in; |
| + value = data->rdma0_sout_color0; |
| + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { |
| + *addr = data->rdma1_sout_sel_in; |
| + value = data->rdma1_sout_dsi0; |
| + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { |
| + *addr = data->ccorr0_sout_sel; |
| + value = data->ccorr0_sout_aal0; |
| + } else { |
| + value = 0; |
| } |
| + |
| + return value; |
| } |
| |
| + |
| void mtk_mmsys_ddp_connect(struct device *dev, |
| enum mtk_ddp_comp_id cur, |
| enum mtk_ddp_comp_id next) |
| { |
| - void __iomem *config_regs = dev_get_drvdata(dev); |
| - unsigned int addr, value, reg; |
| + struct mtk_mmsys_private_data *mmsys_priv = dev_get_drvdata(dev); |
| + const struct mtk_mmsys_reg_data *reg_data = mmsys_priv->data->reg_data; |
| + void __iomem *config_regs = mmsys_priv->config_regs; |
| + unsigned int addr, reg; |
| + int value; |
| |
| - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); |
| + value = mtk_mmsys_ddp_mout_en(reg_data, cur, next, &addr); |
| if (value) { |
| reg = readl_relaxed(config_regs + addr) | value; |
| writel_relaxed(reg, config_regs + addr); |
| } |
| |
| - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); |
| + value = mtk_mmsys_ddp_sout_sel(reg_data, cur, next, &addr); |
| + if (value) |
| + writel_relaxed(value, config_regs + addr); |
| |
| - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); |
| + value = mtk_mmsys_ddp_sel_in(reg_data, cur, next, &addr); |
| if (value) { |
| reg = readl_relaxed(config_regs + addr) | value; |
| writel_relaxed(reg, config_regs + addr); |
| } |
| + |
| + value = mtk_mmsys_ovl_mout_en(reg_data, cur, next, &addr); |
| + if (value >= 0) { |
| + reg = readl_relaxed(config_regs + addr) | value; |
| + writel_relaxed(reg, config_regs + addr); |
| + } |
| } |
| EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); |
| |
| @@ -265,16 +485,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, |
| enum mtk_ddp_comp_id cur, |
| enum mtk_ddp_comp_id next) |
| { |
| - void __iomem *config_regs = dev_get_drvdata(dev); |
| + struct mtk_mmsys_private_data *mmsys_priv = dev_get_drvdata(dev); |
| + const struct mtk_mmsys_reg_data *reg_data = mmsys_priv->data->reg_data; |
| + void __iomem *config_regs = mmsys_priv->config_regs; |
| unsigned int addr, value, reg; |
| |
| - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); |
| + value = mtk_mmsys_ddp_mout_en(reg_data, cur, next, &addr); |
| if (value) { |
| reg = readl_relaxed(config_regs + addr) & ~value; |
| writel_relaxed(reg, config_regs + addr); |
| } |
| |
| - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); |
| + value = mtk_mmsys_ddp_sel_in(reg_data, cur, next, &addr); |
| if (value) { |
| reg = readl_relaxed(config_regs + addr) & ~value; |
| writel_relaxed(reg, config_regs + addr); |
| @@ -284,28 +506,34 @@ EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); |
| |
| static int mtk_mmsys_probe(struct platform_device *pdev) |
| { |
| - const struct mtk_mmsys_driver_data *data; |
| struct device *dev = &pdev->dev; |
| struct platform_device *clks; |
| struct platform_device *drm; |
| - void __iomem *config_regs; |
| + struct mtk_mmsys_private_data *mmsys_priv; |
| struct resource *mem; |
| int ret; |
| |
| + pr_info("%s\n", __func__); |
| + pr_err("%s\n", __func__); |
| + |
| + mmsys_priv = devm_kzalloc(dev, sizeof(*mmsys_priv), GFP_KERNEL); |
| + if (!mmsys_priv) |
| + return -ENOMEM; |
| + |
| mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| - config_regs = devm_ioremap_resource(dev, mem); |
| - if (IS_ERR(config_regs)) { |
| - ret = PTR_ERR(config_regs); |
| + mmsys_priv->config_regs = devm_ioremap_resource(dev, mem); |
| + if (IS_ERR(mmsys_priv->config_regs)) { |
| + ret = PTR_ERR(mmsys_priv->config_regs); |
| dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", |
| ret); |
| return ret; |
| } |
| |
| - platform_set_drvdata(pdev, config_regs); |
| + mmsys_priv->data = of_device_get_match_data(&pdev->dev); |
| + platform_set_drvdata(pdev, mmsys_priv); |
| |
| - data = of_device_get_match_data(&pdev->dev); |
| - |
| - clks = platform_device_register_data(&pdev->dev, data->clk_driver, |
| + clks = platform_device_register_data(&pdev->dev, |
| + mmsys_priv->data->clk_driver, |
| PLATFORM_DEVID_AUTO, NULL, 0); |
| if (IS_ERR(clks)) |
| return PTR_ERR(clks); |
| @@ -315,6 +543,8 @@ static int mtk_mmsys_probe(struct platform_device *pdev) |
| if (IS_ERR(drm)) |
| return PTR_ERR(drm); |
| |
| + pr_info("%s done\n", __func__); |
| + |
| return 0; |
| } |
| |
| @@ -323,6 +553,14 @@ static const struct of_device_id of_match_mtk_mmsys[] = { |
| .compatible = "mediatek,mt8173-mmsys", |
| .data = &mt8173_mmsys_driver_data, |
| }, |
| + { |
| + .compatible = "mediatek,mt8183-mmsys", |
| + .data = &mt8183_mmsys_driver_data, |
| + }, |
| + { |
| + .compatible = "mediatek,mt8192-mmsys", |
| + .data = &mt8192_mmsys_driver_data, |
| + }, |
| { } |
| }; |
| |
| diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c |
| index 5d34e8b9c98859bfe04c8558f7d8721dc2421cff..44b6100fed0c4629d51bc8302f87b3f9e6609343 100644 |
| --- a/drivers/soc/mediatek/mtk-pmic-wrap.c |
| +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c |
| @@ -24,11 +24,13 @@ |
| #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 |
| |
| /* macro for wrapper status */ |
| +#define PWRAP_GET_SWINF_2_FSM(x) (((x) >> 1) & 0x00000007) |
| #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) |
| #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) |
| #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) |
| #define PWRAP_STATE_SYNC_IDLE0 (1 << 20) |
| #define PWRAP_STATE_INIT_DONE0 (1 << 21) |
| +#define PWRAP_STATE_INIT_DONE1 (1 << 15) |
| |
| /* macro for WACS FSM */ |
| #define PWRAP_WACS_FSM_IDLE 0x00 |
| @@ -74,6 +76,7 @@ |
| #define PWRAP_CAP_DCM BIT(2) |
| #define PWRAP_CAP_INT1_EN BIT(3) |
| #define PWRAP_CAP_WDT_SRC1 BIT(4) |
| +#define PWRAP_CAP_ARB BIT(5) |
| |
| /* defines for slave device wrapper registers */ |
| enum dew_regs { |
| @@ -348,6 +351,10 @@ enum pwrap_regs { |
| PWRAP_ADC_RDATA_ADDR1, |
| PWRAP_ADC_RDATA_ADDR2, |
| |
| + /* MT6873 only regs */ |
| + PWRAP_SWINF_2_WDATA_31_0, |
| + PWRAP_SWINF_2_RDATA_31_0, |
| + |
| /* MT7622 only regs */ |
| PWRAP_STA, |
| PWRAP_CLR, |
| @@ -627,6 +634,17 @@ static int mt6797_regs[] = { |
| [PWRAP_DCM_DBC_PRD] = 0x1D4, |
| }; |
| |
| +static int mt6873_regs[] = { |
| + [PWRAP_INIT_DONE2] = 0x0, |
| + [PWRAP_TIMER_EN] = 0x3E0, |
| + [PWRAP_INT_EN] = 0x448, |
| + [PWRAP_WACS2_CMD] = 0xC80, |
| + [PWRAP_SWINF_2_WDATA_31_0] = 0xC84, |
| + [PWRAP_SWINF_2_RDATA_31_0] = 0xC94, |
| + [PWRAP_WACS2_VLDCLR] = 0xCA4, |
| + [PWRAP_WACS2_RDATA] = 0xCA8, |
| +}; |
| + |
| static int mt7622_regs[] = { |
| [PWRAP_MUX_SEL] = 0x0, |
| [PWRAP_WRAP_EN] = 0x4, |
| @@ -1045,6 +1063,7 @@ enum pwrap_type { |
| PWRAP_MT6765, |
| PWRAP_MT6779, |
| PWRAP_MT6797, |
| + PWRAP_MT6873, |
| PWRAP_MT7622, |
| PWRAP_MT8135, |
| PWRAP_MT8173, |
| @@ -1108,16 +1127,30 @@ static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) |
| |
| static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) |
| { |
| - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); |
| + u32 val; |
| + int ret; |
| + |
| + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + ret = (PWRAP_GET_SWINF_2_FSM(val) == PWRAP_WACS_FSM_IDLE); |
| + else |
| + ret = (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE); |
| |
| - return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE; |
| + return ret; |
| } |
| |
| static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) |
| { |
| - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); |
| + u32 val; |
| + int ret; |
| |
| - return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR; |
| + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + ret = (PWRAP_GET_SWINF_2_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR); |
| + else |
| + ret = (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR); |
| + |
| + return ret; |
| } |
| |
| /* |
| @@ -1172,13 +1205,21 @@ static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) |
| return ret; |
| } |
| |
| - pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + pwrap_writel(wrp, adr, PWRAP_WACS2_CMD); |
| + else |
| + pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD); |
| |
| ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); |
| if (ret) |
| return ret; |
| |
| - *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA)); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, |
| + PWRAP_SWINF_2_RDATA_31_0)); |
| + else |
| + *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, |
| + PWRAP_WACS2_RDATA)); |
| |
| pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); |
| |
| @@ -1228,8 +1269,12 @@ static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) |
| return ret; |
| } |
| |
| - pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, |
| - PWRAP_WACS2_CMD); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { |
| + pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); |
| + pwrap_writel(wrp, (1 << 29) | adr, PWRAP_WACS2_CMD); |
| + } else |
| + pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, |
| + PWRAP_WACS2_CMD); |
| |
| return 0; |
| } |
| @@ -1485,6 +1530,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) |
| case PWRAP_MT7622: |
| pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); |
| break; |
| + case PWRAP_MT6873: |
| case PWRAP_MT8183: |
| break; |
| } |
| @@ -1921,6 +1967,19 @@ static const struct pmic_wrapper_type pwrap_mt6797 = { |
| .init_soc_specific = NULL, |
| }; |
| |
| +static struct pmic_wrapper_type pwrap_mt6873 = { |
| + .regs = mt6873_regs, |
| + .type = PWRAP_MT6873, |
| + .arb_en_all = 0x777f, |
| + .int_en_all = BIT(4) | BIT(5), |
| + .int1_en_all = 0, |
| + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, |
| + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, |
| + .caps = PWRAP_CAP_ARB, |
| + .init_reg_clock = pwrap_common_init_reg_clock, |
| + .init_soc_specific = NULL, |
| +}; |
| + |
| static const struct pmic_wrapper_type pwrap_mt7622 = { |
| .regs = mt7622_regs, |
| .type = PWRAP_MT7622, |
| @@ -1998,6 +2057,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { |
| }, { |
| .compatible = "mediatek,mt6797-pwrap", |
| .data = &pwrap_mt6797, |
| + }, { |
| + .compatible = "mediatek,mt6873-pwrap", |
| + .data = &pwrap_mt6873, |
| }, { |
| .compatible = "mediatek,mt7622-pwrap", |
| .data = &pwrap_mt7622, |
| @@ -2022,6 +2084,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); |
| static int pwrap_probe(struct platform_device *pdev) |
| { |
| int ret, irq; |
| + u32 rdata; |
| struct pmic_wrapper *wrp; |
| struct device_node *np = pdev->dev.of_node; |
| const struct of_device_id *of_slave_id = NULL; |
| @@ -2116,14 +2179,22 @@ static int pwrap_probe(struct platform_device *pdev) |
| } |
| } |
| |
| - if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) { |
| + if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + rdata = pwrap_readl(wrp, PWRAP_WACS2_RDATA) & |
| + PWRAP_STATE_INIT_DONE0; |
| + else |
| + rdata = pwrap_readl(wrp, PWRAP_WACS2_RDATA) & |
| + PWRAP_STATE_INIT_DONE1; |
| + if (!rdata) { |
| dev_dbg(wrp->dev, "initialization isn't finished\n"); |
| ret = -ENODEV; |
| goto err_out2; |
| } |
| |
| /* Initialize watchdog, may not be done by the bootloader */ |
| - pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); |
| + if (!(HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))) |
| + pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); |
| + |
| /* |
| * Since STAUPD was not used on mt8173 platform, |
| * so STAUPD of WDT_SRC which should be turned off |
| @@ -2132,7 +2203,11 @@ static int pwrap_probe(struct platform_device *pdev) |
| if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) |
| pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); |
| |
| - pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); |
| + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) |
| + pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); |
| + else |
| + pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); |
| + |
| pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); |
| /* |
| * We add INT1 interrupt to handle starvation and request exception |
| diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c |
| index f669d3754627daddc9619214150aa4ff00b5b963..dfaf375ea6fe2e5525596182a8a9bb2ad2cdd92c 100644 |
| --- a/drivers/soc/mediatek/mtk-scpsys.c |
| +++ b/drivers/soc/mediatek/mtk-scpsys.c |
| @@ -10,8 +10,9 @@ |
| #include <linux/of_device.h> |
| #include <linux/platform_device.h> |
| #include <linux/pm_domain.h> |
| +#include <linux/regmap.h> |
| #include <linux/regulator/consumer.h> |
| -#include <linux/soc/mediatek/infracfg.h> |
| +#include "scpsys.h" |
| |
| #include <dt-bindings/power/mt2701-power.h> |
| #include <dt-bindings/power/mt2712-power.h> |
| @@ -19,12 +20,14 @@ |
| #include <dt-bindings/power/mt7622-power.h> |
| #include <dt-bindings/power/mt7623a-power.h> |
| #include <dt-bindings/power/mt8173-power.h> |
| +#include <dt-bindings/power/mt8192-power.h> |
| |
| #define MTK_POLL_DELAY_US 10 |
| #define MTK_POLL_TIMEOUT USEC_PER_SEC |
| |
| #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) |
| #define MTK_SCPD_FWAIT_SRAM BIT(1) |
| +#define MTK_SCPD_SRAM_ISO BIT(2) |
| #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) |
| |
| #define SPM_VDE_PWR_CON 0x0210 |
| @@ -56,6 +59,8 @@ |
| #define PWR_ON_BIT BIT(2) |
| #define PWR_ON_2ND_BIT BIT(3) |
| #define PWR_CLK_DIS_BIT BIT(4) |
| +#define PWR_SRAM_CLKISO_BIT BIT(5) |
| +#define PWR_SRAM_ISOINT_B_BIT BIT(6) |
| |
| #define PWR_STATUS_CONN BIT(1) |
| #define PWR_STATUS_DISP BIT(3) |
| @@ -78,35 +83,8 @@ |
| #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ |
| #define PWR_STATUS_WB BIT(27) /* MT7622 */ |
| |
| -enum clk_id { |
| - CLK_NONE, |
| - CLK_MM, |
| - CLK_MFG, |
| - CLK_VENC, |
| - CLK_VENC_LT, |
| - CLK_ETHIF, |
| - CLK_VDEC, |
| - CLK_HIFSEL, |
| - CLK_JPGDEC, |
| - CLK_AUDIO, |
| - CLK_MAX, |
| -}; |
| - |
| -static const char * const clk_names[] = { |
| - NULL, |
| - "mm", |
| - "mfg", |
| - "venc", |
| - "venc_lt", |
| - "ethif", |
| - "vdec", |
| - "hif_sel", |
| - "jpgdec", |
| - "audio", |
| - NULL, |
| -}; |
| - |
| #define MAX_CLKS 3 |
| +#define MAX_SUBSYS_CLKS 10 |
| |
| /** |
| * struct scp_domain_data - scp domain data for power on/off flow |
| @@ -115,9 +93,11 @@ static const char * const clk_names[] = { |
| * @ctl_offs: The offset for main power control register. |
| * @sram_pdn_bits: The mask for sram power control bits. |
| * @sram_pdn_ack_bits: The mask for sram power control acked bits. |
| - * @bus_prot_mask: The mask for single step bus protection. |
| - * @clk_id: The basic clocks required by this power domain. |
| + * @basic_clk_name: The basic clocks required by this power domain. |
| + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled |
| + * before releasing bus protection. |
| * @caps: The flag for active wake-up action. |
| + * @bp_table: The mask table for multiple step bus protection. |
| */ |
| struct scp_domain_data { |
| const char *name; |
| @@ -125,9 +105,10 @@ struct scp_domain_data { |
| int ctl_offs; |
| u32 sram_pdn_bits; |
| u32 sram_pdn_ack_bits; |
| - u32 bus_prot_mask; |
| - enum clk_id clk_id[MAX_CLKS]; |
| + const char *basic_clk_name[MAX_CLKS]; |
| + const char *subsys_clk_prefix; |
| u8 caps; |
| + struct bus_prot bp_table[MAX_STEPS]; |
| }; |
| |
| struct scp; |
| @@ -136,6 +117,7 @@ struct scp_domain { |
| struct generic_pm_domain genpd; |
| struct scp *scp; |
| struct clk *clk[MAX_CLKS]; |
| + struct clk *subsys_clk[MAX_SUBSYS_CLKS]; |
| const struct scp_domain_data *data; |
| struct regulator *supply; |
| }; |
| @@ -151,8 +133,8 @@ struct scp { |
| struct device *dev; |
| void __iomem *base; |
| struct regmap *infracfg; |
| + struct regmap *smi_common; |
| struct scp_ctrl_reg ctrl_reg; |
| - bool bus_prot_reg_update; |
| }; |
| |
| struct scp_subdomain { |
| @@ -166,7 +148,6 @@ struct scp_soc_data { |
| const struct scp_subdomain *subdomains; |
| int num_subdomains; |
| const struct scp_ctrl_reg regs; |
| - bool bus_prot_reg_update; |
| }; |
| |
| static int scpsys_domain_is_on(struct scp_domain *scpd) |
| @@ -257,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr) |
| return ret; |
| } |
| |
| + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { |
| + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT; |
| + writel(val, ctl_addr); |
| + udelay(1); |
| + val &= ~PWR_SRAM_CLKISO_BIT; |
| + writel(val, ctl_addr); |
| + } |
| + |
| return 0; |
| } |
| |
| @@ -266,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) |
| u32 pdn_ack = scpd->data->sram_pdn_ack_bits; |
| int tmp; |
| |
| - val = readl(ctl_addr); |
| - val |= scpd->data->sram_pdn_bits; |
| + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { |
| + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT; |
| + writel(val, ctl_addr); |
| + val &= ~PWR_SRAM_ISOINT_B_BIT; |
| + writel(val, ctl_addr); |
| + udelay(1); |
| + } |
| + |
| + val = readl(ctl_addr) | scpd->data->sram_pdn_bits; |
| writel(val, ctl_addr); |
| |
| /* Either wait until SRAM_PDN_ACK all 1 or 0 */ |
| @@ -276,28 +272,114 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) |
| MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
| } |
| |
| +static int set_bus_protection(struct regmap *map, struct bus_prot *bp) |
| +{ |
| + u32 val; |
| + u32 set_ofs = bp->set_ofs; |
| + u32 en_ofs = bp->en_ofs; |
| + u32 sta_ofs = bp->sta_ofs; |
| + u32 mask = bp->mask; |
| + int ret; |
| + |
| + if (set_ofs) |
| + regmap_write(map, set_ofs, mask); |
| + else |
| + regmap_update_bits(map, en_ofs, mask, mask); |
| + |
| + ret = regmap_read_poll_timeout(map, sta_ofs, |
| + val, (val & mask) == mask, |
| + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
| + |
| + if (ret < 0) |
| + pr_err("[NG workaround] scpsys set_bus_protection val=%x, mask=%x, (val & mask)=%x\n", val, mask, (val & mask)); |
| + |
| + return 0; |
| +} |
| + |
| +static int clear_bus_protection(struct regmap *map, struct bus_prot *bp) |
| +{ |
| + u32 val; |
| + u32 clr_ofs = bp->clr_ofs; |
| + u32 en_ofs = bp->en_ofs; |
| + u32 sta_ofs = bp->sta_ofs; |
| + u32 mask = bp->mask; |
| + bool ignore_ack = bp->ignore_clr_ack; |
| + int ret; |
| + |
| + if (clr_ofs) |
| + regmap_write(map, clr_ofs, mask); |
| + else |
| + regmap_update_bits(map, en_ofs, mask, 0); |
| + |
| + if (ignore_ack) |
| + return 0; |
| + |
| + ret = regmap_read_poll_timeout(map, sta_ofs, |
| + val, !(val & mask), |
| + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
| + |
| + if (ret < 0) |
| + pr_err("[NG workaround] scpsys clear_bus_protection val=%x, mask=%x, (val & mask)=%x\n", val, mask, (val & mask)); |
| + |
| + return 0; |
| +} |
| + |
| static int scpsys_bus_protect_enable(struct scp_domain *scpd) |
| { |
| struct scp *scp = scpd->scp; |
| + const struct bus_prot *bp_table = scpd->data->bp_table; |
| + struct regmap *infracfg = scp->infracfg; |
| + struct regmap *smi_common = scp->smi_common; |
| + int i; |
| |
| - if (!scpd->data->bus_prot_mask) |
| - return 0; |
| + for (i = 0; i < MAX_STEPS; i++) { |
| + struct regmap *map = NULL; |
| + int ret; |
| + struct bus_prot bp = bp_table[i]; |
| + |
| + if (bp.type == IFR_TYPE) |
| + map = infracfg; |
| + else if (bp.type == SMI_TYPE) |
| + map = smi_common; |
| + else |
| + break; |
| + |
| + ret = set_bus_protection(map, &bp); |
| |
| - return mtk_infracfg_set_bus_protection(scp->infracfg, |
| - scpd->data->bus_prot_mask, |
| - scp->bus_prot_reg_update); |
| + if (ret) |
| + return ret; |
| + } |
| + |
| + return 0; |
| } |
| |
| static int scpsys_bus_protect_disable(struct scp_domain *scpd) |
| { |
| struct scp *scp = scpd->scp; |
| + const struct bus_prot *bp_table = scpd->data->bp_table; |
| + struct regmap *infracfg = scp->infracfg; |
| + struct regmap *smi_common = scp->smi_common; |
| + int i; |
| |
| - if (!scpd->data->bus_prot_mask) |
| - return 0; |
| + for (i = MAX_STEPS - 1; i >= 0; i--) { |
| + struct regmap *map = NULL; |
| + int ret; |
| + struct bus_prot bp = bp_table[i]; |
| + |
| + if (bp.type == IFR_TYPE) |
| + map = infracfg; |
| + else if (bp.type == SMI_TYPE) |
| + map = smi_common; |
| + else |
| + continue; |
| + |
| + ret = clear_bus_protection(map, &bp); |
| + |
| + if (ret) |
| + return ret; |
| + } |
| |
| - return mtk_infracfg_clear_bus_protection(scp->infracfg, |
| - scpd->data->bus_prot_mask, |
| - scp->bus_prot_reg_update); |
| + return 0; |
| } |
| |
| static int scpsys_power_on(struct generic_pm_domain *genpd) |
| @@ -338,16 +420,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) |
| val |= PWR_RST_B_BIT; |
| writel(val, ctl_addr); |
| |
| - ret = scpsys_sram_enable(scpd, ctl_addr); |
| + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS); |
| if (ret < 0) |
| goto err_pwr_ack; |
| |
| + ret = scpsys_sram_enable(scpd, ctl_addr); |
| + if (ret < 0) |
| + goto err_sram; |
| + |
| ret = scpsys_bus_protect_disable(scpd); |
| if (ret < 0) |
| - goto err_pwr_ack; |
| + goto err_sram; |
| |
| return 0; |
| |
| +err_sram: |
| + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS); |
| err_pwr_ack: |
| scpsys_clk_disable(scpd->clk, MAX_CLKS); |
| err_clk: |
| @@ -366,6 +454,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) |
| u32 val; |
| int ret, tmp; |
| |
| + if (1) |
| + return 0; |
| + |
| ret = scpsys_bus_protect_enable(scpd); |
| if (ret < 0) |
| goto out; |
| @@ -374,6 +465,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) |
| if (ret < 0) |
| goto out; |
| |
| + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS); |
| + |
| /* subsys power off */ |
| val = readl(ctl_addr); |
| val |= PWR_ISO_BIT; |
| @@ -411,24 +504,75 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) |
| return ret; |
| } |
| |
| -static void init_clks(struct platform_device *pdev, struct clk **clk) |
| +static int init_subsys_clks(struct platform_device *pdev, |
| + const char *prefix, struct clk **clk) |
| +{ |
| + struct device_node *node = pdev->dev.of_node; |
| + u32 prefix_len, sub_clk_cnt = 0; |
| + struct property *prop; |
| + const char *clk_name; |
| + |
| + if (!node) { |
| + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n", |
| + PTR_ERR(node)); |
| + return PTR_ERR(node); |
| + } |
| + |
| + prefix_len = strlen(prefix); |
| + |
| + of_property_for_each_string(node, "clock-names", prop, clk_name) { |
| + if (!strncmp(clk_name, prefix, prefix_len) && |
| + (clk_name[prefix_len] == '-')) { |
| + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) { |
| + dev_err(&pdev->dev, |
| + "subsys clk out of range %d\n", |
| + sub_clk_cnt); |
| + return -EINVAL; |
| + } |
| + |
| + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev, |
| + clk_name); |
| + |
| + if (IS_ERR(clk[sub_clk_cnt])) { |
| + dev_err(&pdev->dev, |
| + "Subsys clk get fail %ld\n", |
| + PTR_ERR(clk[sub_clk_cnt])); |
| + return PTR_ERR(clk[sub_clk_cnt]); |
| + } |
| + sub_clk_cnt++; |
| + } |
| + } |
| + |
| + return sub_clk_cnt; |
| +} |
| + |
| +static int init_basic_clks(struct platform_device *pdev, struct clk **clk, |
| + const char * const *name) |
| { |
| int i; |
| |
| - for (i = CLK_NONE + 1; i < CLK_MAX; i++) |
| - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]); |
| + for (i = 0; i < MAX_CLKS && name[i]; i++) { |
| + clk[i] = devm_clk_get(&pdev->dev, name[i]); |
| + |
| + if (IS_ERR(clk[i])) { |
| + dev_err(&pdev->dev, |
| + "get basic clk %s fail %ld\n", |
| + name[i], PTR_ERR(clk[i])); |
| + return PTR_ERR(clk[i]); |
| + } |
| + } |
| + |
| + return 0; |
| } |
| |
| static struct scp *init_scp(struct platform_device *pdev, |
| const struct scp_domain_data *scp_domain_data, int num, |
| - const struct scp_ctrl_reg *scp_ctrl_reg, |
| - bool bus_prot_reg_update) |
| + const struct scp_ctrl_reg *scp_ctrl_reg) |
| { |
| struct genpd_onecell_data *pd_data; |
| struct resource *res; |
| - int i, j; |
| + int i, ret; |
| struct scp *scp; |
| - struct clk *clk[CLK_MAX]; |
| |
| scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); |
| if (!scp) |
| @@ -437,8 +581,6 @@ static struct scp *init_scp(struct platform_device *pdev, |
| scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs; |
| scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs; |
| |
| - scp->bus_prot_reg_update = bus_prot_reg_update; |
| - |
| scp->dev = &pdev->dev; |
| |
| res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -466,6 +608,17 @@ static struct scp *init_scp(struct platform_device *pdev, |
| return ERR_CAST(scp->infracfg); |
| } |
| |
| + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| + "smi_comm"); |
| + |
| + if (scp->smi_common == ERR_PTR(-ENODEV)) { |
| + scp->smi_common = NULL; |
| + } else if (IS_ERR(scp->smi_common)) { |
| + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n", |
| + PTR_ERR(scp->smi_common)); |
| + return ERR_CAST(scp->smi_common); |
| + } |
| + |
| for (i = 0; i < num; i++) { |
| struct scp_domain *scpd = &scp->domains[i]; |
| const struct scp_domain_data *data = &scp_domain_data[i]; |
| @@ -481,8 +634,6 @@ static struct scp *init_scp(struct platform_device *pdev, |
| |
| pd_data->num_domains = num; |
| |
| - init_clks(pdev, clk); |
| - |
| for (i = 0; i < num; i++) { |
| struct scp_domain *scpd = &scp->domains[i]; |
| struct generic_pm_domain *genpd = &scpd->genpd; |
| @@ -493,16 +644,20 @@ static struct scp *init_scp(struct platform_device *pdev, |
| |
| scpd->data = data; |
| |
| - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { |
| - struct clk *c = clk[data->clk_id[j]]; |
| - |
| - if (IS_ERR(c)) { |
| - dev_err(&pdev->dev, "%s: clk unavailable\n", |
| + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name); |
| + if (ret) |
| + return ERR_PTR(ret); |
| + |
| + if (data->subsys_clk_prefix) { |
| + ret = init_subsys_clks(pdev, |
| + data->subsys_clk_prefix, |
| + scpd->subsys_clk); |
| + if (ret < 0) { |
| + dev_err(&pdev->dev, |
| + "%s: subsys clk unavailable\n", |
| data->name); |
| - return ERR_CAST(c); |
| + return ERR_PTR(ret); |
| } |
| - |
| - scpd->clk[j] = c; |
| } |
| |
| genpd->name = data->name; |
| @@ -558,9 +713,11 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .name = "conn", |
| .sta_mask = PWR_STATUS_CONN, |
| .ctl_offs = SPM_CONN_PWR_CON, |
| - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | |
| - MT2701_TOP_AXI_PROT_EN_CONN_S, |
| - .clk_id = {CLK_NONE}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT2701_TOP_AXI_PROT_EN_CONN_M | |
| + MT2701_TOP_AXI_PROT_EN_CONN_S), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_DISP] = { |
| @@ -568,8 +725,11 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .sta_mask = PWR_STATUS_DISP, |
| .ctl_offs = SPM_DIS_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| - .clk_id = {CLK_MM}, |
| - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, |
| + .basic_clk_name = {"mm"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT2701_TOP_AXI_PROT_EN_MM_M0), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_MFG] = { |
| @@ -578,7 +738,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .ctl_offs = SPM_MFG_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MFG}, |
| + .basic_clk_name = {"mfg"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_VDEC] = { |
| @@ -587,7 +747,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .ctl_offs = SPM_VDE_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_ISP] = { |
| @@ -596,7 +756,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .ctl_offs = SPM_ISP_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(13, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_BDP] = { |
| @@ -604,7 +764,6 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .sta_mask = PWR_STATUS_BDP, |
| .ctl_offs = SPM_BDP_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_ETH] = { |
| @@ -613,7 +772,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .ctl_offs = SPM_ETH_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_ETHIF}, |
| + .basic_clk_name = {"ethif"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_HIF] = { |
| @@ -622,14 +781,13 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { |
| .ctl_offs = SPM_HIF_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_ETHIF}, |
| + .basic_clk_name = {"ethif"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2701_POWER_DOMAIN_IFR_MSC] = { |
| .name = "ifr_msc", |
| .sta_mask = PWR_STATUS_IFR_MSC, |
| .ctl_offs = SPM_IFR_MSC_PWR_CON, |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| }; |
| @@ -644,7 +802,7 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_DIS_PWR_CON, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_VDEC] = { |
| @@ -653,7 +811,7 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_VDE_PWR_CON, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM, CLK_VDEC}, |
| + .basic_clk_name = {"mm", "vdec"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_VENC] = { |
| @@ -662,7 +820,7 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_VEN_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC}, |
| + .basic_clk_name = {"mm", "venc", "jpgdec"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_ISP] = { |
| @@ -671,7 +829,7 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_ISP_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(13, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_AUDIO] = { |
| @@ -680,7 +838,7 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_AUDIO_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_AUDIO}, |
| + .basic_clk_name = {"audio"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_USB] = { |
| @@ -689,7 +847,6 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_USB_PWR_CON, |
| .sram_pdn_bits = GENMASK(10, 8), |
| .sram_pdn_ack_bits = GENMASK(14, 12), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_USB2] = { |
| @@ -698,7 +855,6 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_USB2_PWR_CON, |
| .sram_pdn_bits = GENMASK(10, 8), |
| .sram_pdn_ack_bits = GENMASK(14, 12), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_MFG] = { |
| @@ -707,8 +863,11 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = SPM_MFG_PWR_CON, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(16, 16), |
| - .clk_id = {CLK_MFG}, |
| - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), |
| + .basic_clk_name = {"mfg"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228, |
| + BIT(14) | BIT(21) | BIT(23)), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_MFG_SC1] = { |
| @@ -717,7 +876,6 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = 0x02c0, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(16, 16), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_MFG_SC2] = { |
| @@ -726,7 +884,6 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = 0x02c4, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(16, 16), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT2712_POWER_DOMAIN_MFG_SC3] = { |
| @@ -735,7 +892,6 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { |
| .ctl_offs = 0x01f8, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(16, 16), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| }; |
| @@ -760,7 +916,7 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x300, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_VDEC}, |
| + .basic_clk_name = {"vdec"}, |
| }, |
| [MT6797_POWER_DOMAIN_VENC] = { |
| .name = "venc", |
| @@ -768,7 +924,6 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x304, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| [MT6797_POWER_DOMAIN_ISP] = { |
| .name = "isp", |
| @@ -776,7 +931,6 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x308, |
| .sram_pdn_bits = GENMASK(9, 8), |
| .sram_pdn_ack_bits = GENMASK(13, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| [MT6797_POWER_DOMAIN_MM] = { |
| .name = "mm", |
| @@ -784,8 +938,11 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x30C, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM}, |
| - .bus_prot_mask = (BIT(1) | BIT(2)), |
| + .basic_clk_name = {"mm"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + BIT(1) | BIT(2)), |
| + }, |
| }, |
| [MT6797_POWER_DOMAIN_AUDIO] = { |
| .name = "audio", |
| @@ -793,7 +950,6 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x314, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| [MT6797_POWER_DOMAIN_MFG_ASYNC] = { |
| .name = "mfg_async", |
| @@ -801,7 +957,7 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x334, |
| .sram_pdn_bits = 0, |
| .sram_pdn_ack_bits = 0, |
| - .clk_id = {CLK_MFG}, |
| + .basic_clk_name = {"mfg"}, |
| }, |
| [MT6797_POWER_DOMAIN_MJC] = { |
| .name = "mjc", |
| @@ -809,7 +965,6 @@ static const struct scp_domain_data scp_domain_data_mt6797[] = { |
| .ctl_offs = 0x310, |
| .sram_pdn_bits = GENMASK(8, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| }; |
| |
| @@ -834,8 +989,10 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = { |
| .ctl_offs = SPM_ETHSYS_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_NONE}, |
| - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT7622_TOP_AXI_PROT_EN_ETHSYS), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7622_POWER_DOMAIN_HIF0] = { |
| @@ -844,8 +1001,11 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = { |
| .ctl_offs = SPM_HIF0_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_HIFSEL}, |
| - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0, |
| + .basic_clk_name = {"hif_sel"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT7622_TOP_AXI_PROT_EN_HIF0), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7622_POWER_DOMAIN_HIF1] = { |
| @@ -854,8 +1014,11 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = { |
| .ctl_offs = SPM_HIF1_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_HIFSEL}, |
| - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1, |
| + .basic_clk_name = {"hif_sel"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT7622_TOP_AXI_PROT_EN_HIF1), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7622_POWER_DOMAIN_WB] = { |
| @@ -864,8 +1027,10 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = { |
| .ctl_offs = SPM_WB_PWR_CON, |
| .sram_pdn_bits = 0, |
| .sram_pdn_ack_bits = 0, |
| - .clk_id = {CLK_NONE}, |
| - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT7622_TOP_AXI_PROT_EN_WB), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM, |
| }, |
| }; |
| @@ -879,9 +1044,11 @@ static const struct scp_domain_data scp_domain_data_mt7623a[] = { |
| .name = "conn", |
| .sta_mask = PWR_STATUS_CONN, |
| .ctl_offs = SPM_CONN_PWR_CON, |
| - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | |
| - MT2701_TOP_AXI_PROT_EN_CONN_S, |
| - .clk_id = {CLK_NONE}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT2701_TOP_AXI_PROT_EN_CONN_M | |
| + MT2701_TOP_AXI_PROT_EN_CONN_S), |
| + }, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7623A_POWER_DOMAIN_ETH] = { |
| @@ -890,7 +1057,7 @@ static const struct scp_domain_data scp_domain_data_mt7623a[] = { |
| .ctl_offs = SPM_ETH_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_ETHIF}, |
| + .basic_clk_name = {"ethif"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7623A_POWER_DOMAIN_HIF] = { |
| @@ -899,14 +1066,13 @@ static const struct scp_domain_data scp_domain_data_mt7623a[] = { |
| .ctl_offs = SPM_HIF_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_ETHIF}, |
| + .basic_clk_name = {"ethif"}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT7623A_POWER_DOMAIN_IFR_MSC] = { |
| .name = "ifr_msc", |
| .sta_mask = PWR_STATUS_IFR_MSC, |
| .ctl_offs = SPM_IFR_MSC_PWR_CON, |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| }; |
| @@ -922,7 +1088,7 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_VDE_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| }, |
| [MT8173_POWER_DOMAIN_VENC] = { |
| .name = "venc", |
| @@ -930,7 +1096,7 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_VEN_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_MM, CLK_VENC}, |
| + .basic_clk_name = {"mm", "venc"}, |
| }, |
| [MT8173_POWER_DOMAIN_ISP] = { |
| .name = "isp", |
| @@ -938,7 +1104,7 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_ISP_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(13, 12), |
| - .clk_id = {CLK_MM}, |
| + .basic_clk_name = {"mm"}, |
| }, |
| [MT8173_POWER_DOMAIN_MM] = { |
| .name = "mm", |
| @@ -946,9 +1112,12 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_DIS_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(12, 12), |
| - .clk_id = {CLK_MM}, |
| - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | |
| - MT8173_TOP_AXI_PROT_EN_MM_M1, |
| + .basic_clk_name = {"mm"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT8173_TOP_AXI_PROT_EN_MM_M0 | |
| + MT8173_TOP_AXI_PROT_EN_MM_M1), |
| + }, |
| }, |
| [MT8173_POWER_DOMAIN_VENC_LT] = { |
| .name = "venc_lt", |
| @@ -956,7 +1125,7 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_VEN2_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_MM, CLK_VENC_LT}, |
| + .basic_clk_name = {"mm", "venc_lt"}, |
| }, |
| [MT8173_POWER_DOMAIN_AUDIO] = { |
| .name = "audio", |
| @@ -964,7 +1133,6 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_AUDIO_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| [MT8173_POWER_DOMAIN_USB] = { |
| .name = "usb", |
| @@ -972,7 +1140,6 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_USB_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(15, 12), |
| - .clk_id = {CLK_NONE}, |
| .caps = MTK_SCPD_ACTIVE_WAKEUP, |
| }, |
| [MT8173_POWER_DOMAIN_MFG_ASYNC] = { |
| @@ -981,7 +1148,7 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_MFG_ASYNC_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = 0, |
| - .clk_id = {CLK_MFG}, |
| + .basic_clk_name = {"mfg"}, |
| }, |
| [MT8173_POWER_DOMAIN_MFG_2D] = { |
| .name = "mfg_2d", |
| @@ -989,7 +1156,6 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_MFG_2D_PWR_CON, |
| .sram_pdn_bits = GENMASK(11, 8), |
| .sram_pdn_ack_bits = GENMASK(13, 12), |
| - .clk_id = {CLK_NONE}, |
| }, |
| [MT8173_POWER_DOMAIN_MFG] = { |
| .name = "mfg", |
| @@ -997,11 +1163,13 @@ static const struct scp_domain_data scp_domain_data_mt8173[] = { |
| .ctl_offs = SPM_MFG_PWR_CON, |
| .sram_pdn_bits = GENMASK(13, 8), |
| .sram_pdn_ack_bits = GENMASK(21, 16), |
| - .clk_id = {CLK_NONE}, |
| - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | |
| - MT8173_TOP_AXI_PROT_EN_MFG_M0 | |
| - MT8173_TOP_AXI_PROT_EN_MFG_M1 | |
| - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, |
| + MT8173_TOP_AXI_PROT_EN_MFG_S | |
| + MT8173_TOP_AXI_PROT_EN_MFG_M0 | |
| + MT8173_TOP_AXI_PROT_EN_MFG_M1 | |
| + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), |
| + }, |
| }, |
| }; |
| |
| @@ -1010,6 +1178,308 @@ static const struct scp_subdomain scp_subdomain_mt8173[] = { |
| {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, |
| }; |
| |
| +/* |
| + * MT8192 power domain support |
| + */ |
| + |
| +static const struct scp_domain_data scp_domain_data_mt8192[] = { |
| + [MT8192_POWER_DOMAIN_CONN] = { |
| + .name = "conn", |
| + .sta_mask = PWR_STATUS_CONN, |
| + .ctl_offs = 0x0304, |
| + .sram_pdn_bits = 0, |
| + .sram_pdn_ack_bits = 0, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, |
| + MT8192_TOP_AXI_PROT_EN_CONN), |
| + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, |
| + MT8192_TOP_AXI_PROT_EN_CONN_2ND), |
| + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, |
| + MT8192_TOP_AXI_PROT_EN_1_CONN), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG0] = { |
| + .name = "mfg", |
| + .sta_mask = BIT(2), |
| + .ctl_offs = 0x0308, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"mfg"}, |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG1] = { |
| + .name = "mfg1", |
| + .sta_mask = BIT(3), |
| + .ctl_offs = 0x030c, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, |
| + MT8192_TOP_AXI_PROT_EN_1_MFG1), |
| + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, |
| + MT8192_TOP_AXI_PROT_EN_2_MFG1), |
| + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, |
| + MT8192_TOP_AXI_PROT_EN_MFG1), |
| + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, |
| + MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG2] = { |
| + .name = "mfg2", |
| + .sta_mask = BIT(4), |
| + .ctl_offs = 0x0310, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG3] = { |
| + .name = "mfg3", |
| + .sta_mask = BIT(5), |
| + .ctl_offs = 0x0314, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG4] = { |
| + .name = "mfg4", |
| + .sta_mask = BIT(6), |
| + .ctl_offs = 0x0318, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG5] = { |
| + .name = "mfg5", |
| + .sta_mask = BIT(7), |
| + .ctl_offs = 0x031c, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + }, |
| + [MT8192_POWER_DOMAIN_MFG6] = { |
| + .name = "mfg6", |
| + .sta_mask = BIT(8), |
| + .ctl_offs = 0x0320, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + }, |
| + [MT8192_POWER_DOMAIN_DISP] = { |
| + .name = "disp", |
| + .sta_mask = BIT(20), |
| + .ctl_offs = 0x0350, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"disp"}, |
| + .subsys_clk_prefix = "disp", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_DISP), |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_DISP), |
| + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, |
| + MT8192_TOP_AXI_PROT_EN_DISP), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND), |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_ISP] = { |
| + .name = "isp", |
| + .sta_mask = BIT(12), |
| + .ctl_offs = 0x0330, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"isp"}, |
| + .subsys_clk_prefix = "isp", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_ISP), |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_ISP2] = { |
| + .name = "isp2", |
| + .sta_mask = BIT(13), |
| + .ctl_offs = 0x0334, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"isp2"}, |
| + .subsys_clk_prefix = "isp2", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_ISP2), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_IPE] = { |
| + .name = "ipe", |
| + .sta_mask = BIT(14), |
| + .ctl_offs = 0x0338, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"ipe"}, |
| + .subsys_clk_prefix = "ipe", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_IPE), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_VDEC] = { |
| + .name = "vdec", |
| + .sta_mask = BIT(15), |
| + .ctl_offs = 0x033c, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"vdec"}, |
| + .subsys_clk_prefix = "vdec", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_VDEC), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_VDEC2] = { |
| + .name = "vdec2", |
| + .sta_mask = BIT(16), |
| + .ctl_offs = 0x0340, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .subsys_clk_prefix = "vdec2", |
| + }, |
| + [MT8192_POWER_DOMAIN_VENC] = { |
| + .name = "venc", |
| + .sta_mask = BIT(17), |
| + .ctl_offs = 0x0344, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"venc"}, |
| + .subsys_clk_prefix = "venc", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_VENC), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_MDP] = { |
| + .name = "mdp", |
| + .sta_mask = BIT(19), |
| + .ctl_offs = 0x034c, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"mdp"}, |
| + .subsys_clk_prefix = "mdp", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_MDP), |
| + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, |
| + MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_AUDIO] = { |
| + .name = "audio", |
| + .sta_mask = BIT(21), |
| + .ctl_offs = 0x0354, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"audio", "audio1", "audio2"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, |
| + MT8192_TOP_AXI_PROT_EN_2_AUDIO), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_ADSP] = { |
| + .name = "adsp", |
| + .sta_mask = BIT(22), |
| + .ctl_offs = 0x0358, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"adsp"}, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, |
| + MT8192_TOP_AXI_PROT_EN_2_ADSP), |
| + }, |
| + .caps = MTK_SCPD_SRAM_ISO, |
| + }, |
| + [MT8192_POWER_DOMAIN_CAM] = { |
| + .name = "cam", |
| + .sta_mask = BIT(23), |
| + .ctl_offs = 0x035c, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .basic_clk_name = {"cam"}, |
| + .subsys_clk_prefix = "cam", |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, |
| + MT8192_TOP_AXI_PROT_EN_2_CAM), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_CAM), |
| + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, |
| + MT8192_TOP_AXI_PROT_EN_1_CAM), |
| + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, |
| + MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND), |
| + BUS_PROT(IFR_TYPE, 0xb84, 0xb88, 0xb80, 0xb90, |
| + MT8192_TOP_AXI_PROT_EN_VDNR_CAM), |
| + }, |
| + }, |
| + [MT8192_POWER_DOMAIN_CAM_RAWA] = { |
| + .name = "cam_rawa", |
| + .sta_mask = BIT(24), |
| + .ctl_offs = 0x0360, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .subsys_clk_prefix = "cam_rawa", |
| + }, |
| + [MT8192_POWER_DOMAIN_CAM_RAWB] = { |
| + .name = "cam_rawb", |
| + .sta_mask = BIT(25), |
| + .ctl_offs = 0x0364, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .subsys_clk_prefix = "cam_rawb", |
| + }, |
| + [MT8192_POWER_DOMAIN_CAM_RAWC] = { |
| + .name = "cam_rawc", |
| + .sta_mask = BIT(26), |
| + .ctl_offs = 0x0368, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = GENMASK(12, 12), |
| + .subsys_clk_prefix = "cam_rawc", |
| + }, |
| + [MT8192_POWER_DOMAIN_MSDC] = { |
| + .name = "msdc", |
| + .sta_mask = BIT(30), |
| + .ctl_offs = 0x03a4, |
| + .sram_pdn_bits = GENMASK(8, 8), |
| + .sram_pdn_ack_bits = 0, |
| + .bp_table = { |
| + BUS_PROT(IFR_TYPE, 0xb84, 0xb88, 0xb80, 0xb90, |
| + MT8192_TOP_AXI_PROT_EN_VDNR_MSDC), |
| + }, |
| + }, |
| +}; |
| + |
| +static const struct scp_subdomain scp_subdomain_mt8192[] = { |
| + {MT8192_POWER_DOMAIN_MFG0, MT8192_POWER_DOMAIN_MFG1}, |
| + {MT8192_POWER_DOMAIN_MFG1, MT8192_POWER_DOMAIN_MFG2}, |
| + {MT8192_POWER_DOMAIN_MFG1, MT8192_POWER_DOMAIN_MFG3}, |
| + {MT8192_POWER_DOMAIN_MFG1, MT8192_POWER_DOMAIN_MFG4}, |
| + {MT8192_POWER_DOMAIN_MFG1, MT8192_POWER_DOMAIN_MFG5}, |
| + {MT8192_POWER_DOMAIN_MFG1, MT8192_POWER_DOMAIN_MFG6}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_ISP}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_ISP2}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_IPE}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_VDEC}, |
| + {MT8192_POWER_DOMAIN_VDEC, MT8192_POWER_DOMAIN_VDEC2}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_VENC}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_MDP}, |
| + {MT8192_POWER_DOMAIN_DISP, MT8192_POWER_DOMAIN_CAM}, |
| + {MT8192_POWER_DOMAIN_CAM, MT8192_POWER_DOMAIN_CAM_RAWA}, |
| + {MT8192_POWER_DOMAIN_CAM, MT8192_POWER_DOMAIN_CAM_RAWB}, |
| + {MT8192_POWER_DOMAIN_CAM, MT8192_POWER_DOMAIN_CAM_RAWC}, |
| +}; |
| + |
| static const struct scp_soc_data mt2701_data = { |
| .domains = scp_domain_data_mt2701, |
| .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), |
| @@ -1017,7 +1487,6 @@ static const struct scp_soc_data mt2701_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
| }, |
| - .bus_prot_reg_update = true, |
| }; |
| |
| static const struct scp_soc_data mt2712_data = { |
| @@ -1029,7 +1498,6 @@ static const struct scp_soc_data mt2712_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
| }, |
| - .bus_prot_reg_update = false, |
| }; |
| |
| static const struct scp_soc_data mt6797_data = { |
| @@ -1041,7 +1509,6 @@ static const struct scp_soc_data mt6797_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS_MT6797, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797 |
| }, |
| - .bus_prot_reg_update = true, |
| }; |
| |
| static const struct scp_soc_data mt7622_data = { |
| @@ -1051,7 +1518,6 @@ static const struct scp_soc_data mt7622_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
| }, |
| - .bus_prot_reg_update = true, |
| }; |
| |
| static const struct scp_soc_data mt7623a_data = { |
| @@ -1061,7 +1527,6 @@ static const struct scp_soc_data mt7623a_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
| }, |
| - .bus_prot_reg_update = true, |
| }; |
| |
| static const struct scp_soc_data mt8173_data = { |
| @@ -1073,7 +1538,17 @@ static const struct scp_soc_data mt8173_data = { |
| .pwr_sta_offs = SPM_PWR_STATUS, |
| .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
| }, |
| - .bus_prot_reg_update = true, |
| +}; |
| + |
| +static const struct scp_soc_data mt8192_data = { |
| + .domains = scp_domain_data_mt8192, |
| + .num_domains = ARRAY_SIZE(scp_domain_data_mt8192), |
| + .subdomains = scp_subdomain_mt8192, |
| + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8192), |
| + .regs = { |
| + .pwr_sta_offs = 0x016c, |
| + .pwr_sta2nd_offs = 0x0170 |
| + } |
| }; |
| |
| /* |
| @@ -1099,6 +1574,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { |
| }, { |
| .compatible = "mediatek,mt8173-scpsys", |
| .data = &mt8173_data, |
| + }, { |
| + .compatible = "mediatek,mt8192-scpsys", |
| + .data = &mt8192_data, |
| }, { |
| /* sentinel */ |
| } |
| @@ -1114,8 +1592,7 @@ static int scpsys_probe(struct platform_device *pdev) |
| |
| soc = of_device_get_match_data(&pdev->dev); |
| |
| - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs, |
| - soc->bus_prot_reg_update); |
| + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs); |
| if (IS_ERR(scp)) |
| return PTR_ERR(scp); |
| |
| diff --git a/drivers/soc/mediatek/scpsys.h b/drivers/soc/mediatek/scpsys.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..a8242ccc3eb4f9afe4631836710d92099ec1056a |
| --- /dev/null |
| +++ b/drivers/soc/mediatek/scpsys.h |
| @@ -0,0 +1,100 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +#ifndef __SOC_MEDIATEK_SCPSYS_H |
| +#define __SOC_MEDIATEK_SCPSYS_H |
| + |
| +#define MAX_STEPS 5 |
| + |
| +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \ |
| + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \ |
| + .type = _type, \ |
| + .set_ofs = _set_ofs, \ |
| + .clr_ofs = _clr_ofs, \ |
| + .en_ofs = _en_ofs, \ |
| + .sta_ofs = _sta_ofs, \ |
| + .mask = _mask, \ |
| + .ignore_clr_ack = _ignore_clr_ack, \ |
| + } |
| + |
| +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \ |
| + _en_ofs, _sta_ofs, _mask) \ |
| + _BUS_PROT(_type, _set_ofs, _clr_ofs, \ |
| + _en_ofs, _sta_ofs, _mask, false) |
| + |
| +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \ |
| + _en_ofs, _sta_ofs, _mask) \ |
| + _BUS_PROT(_type, _set_ofs, _clr_ofs, \ |
| + _en_ofs, _sta_ofs, _mask, true) |
| + |
| +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) |
| +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) |
| +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) |
| + |
| +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) |
| +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) |
| +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ |
| + BIT(28)) |
| +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ |
| + BIT(7) | BIT(8)) |
| + |
| +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) |
| +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) |
| +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) |
| +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) |
| +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) |
| +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) |
| + |
| +#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23)) |
| +#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18)) |
| +#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14) |
| +#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21) |
| +#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10) |
| +#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21) |
| +#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22) |
| +#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0) |
| +#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3) |
| +#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4) |
| +#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5) |
| +#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \ |
| + BIT(10) | BIT(12) | \ |
| + BIT(14) | BIT(16) | \ |
| + BIT(24) | BIT(26)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \ |
| + BIT(15) | BIT(17) | \ |
| + BIT(25) | BIT(27)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13)) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12) |
| +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) |
| +#define MT8192_TOP_AXI_PROT_EN_VDNR_MSDC BIT(11) |
| +#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) |
| + |
| +enum regmap_type { |
| + INVALID_TYPE = 0, |
| + IFR_TYPE, |
| + SMI_TYPE, |
| +}; |
| + |
| +struct bus_prot { |
| + enum regmap_type type; |
| + u32 set_ofs; |
| + u32 clr_ofs; |
| + u32 en_ofs; |
| + u32 sta_ofs; |
| + u32 mask; |
| + bool ignore_clr_ack; |
| +}; |
| + |
| +#endif /* __SOC_MEDIATEK_SCPSYS_H */ |
| diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig |
| index a53bad541f1a34686cb5b14a60708923db823de1..418848840999b5b5fb8035dad36328c3ff51c518 100644 |
| --- a/drivers/spmi/Kconfig |
| +++ b/drivers/spmi/Kconfig |
| @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB |
| This is required for communicating with Qualcomm PMICs and |
| other devices that have the SPMI interface. |
| |
| +config SPMI_MTK_PMIF |
| + tristate "Mediatek SPMI Controller (PMIC Arbiter)" |
| + help |
| + If you say yes to this option, support will be included for the |
| + built-in SPMI PMIC Arbiter interface on Mediatek family |
| + processors. |
| + |
| + This is required for communicating with Mediatek PMICs and |
| + other devices that have the SPMI interface. |
| endif |
| diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile |
| index 55a94cadeffe4b0a955b48ef7219f53db3f8e959..91f303b96925a038f4736afc087e125de301b930 100644 |
| --- a/drivers/spmi/Makefile |
| +++ b/drivers/spmi/Makefile |
| @@ -5,3 +5,4 @@ |
| obj-$(CONFIG_SPMI) += spmi.o |
| |
| obj-$(CONFIG_SPMI_MSM_PMIC_ARB) += spmi-pmic-arb.o |
| +obj-$(CONFIG_SPMI_MTK_PMIF) += spmi-mtk-pmif.o |
| \ No newline at end of file |
| diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..12c86a6408ecde6d683b49e4140cd10553df468e |
| --- /dev/null |
| +++ b/drivers/spmi/spmi-mtk-pmif.c |
| @@ -0,0 +1,876 @@ |
| +// SPDX-License-Identifier: GPL-2.0 |
| +// |
| +// Copyright (c) 2020 MediaTek Inc. |
| + |
| +#include <linux/clk.h> |
| +#include <linux/interrupt.h> |
| +#include <linux/io.h> |
| +#include <linux/regmap.h> |
| +#include <linux/reset.h> |
| +#include <linux/delay.h> |
| +#include <linux/err.h> |
| +#include <linux/kernel.h> |
| +#include <linux/module.h> |
| +#include <linux/of.h> |
| +#include <linux/of_device.h> |
| +#include <linux/of_address.h> |
| +#include <linux/platform_device.h> |
| +#include <linux/slab.h> |
| +#include <linux/sched/clock.h> |
| +#include <linux/kthread.h> |
| +#include <linux/mutex.h> |
| +#include <linux/pm_wakeup.h> |
| +#include <linux/spmi.h> |
| +#include <dt-bindings/spmi/spmi.h> |
| + |
| +/* macro for PMIF SWINF FSM */ |
| +#define PMIF_SWINF_FSM_IDLE 0x00 |
| +#define PMIF_SWINF_FSM_REQ 0x02 |
| +#define PMIF_SWINF_FSM_WFDLE 0x04 |
| +#define PMIF_SWINF_FSM_WFVLDCLR 0x06 |
| +#define PMIF_SWINF_INIT_DONE 0x01 |
| +#define PMIF_SWINF_SYS_IDLE 0x00 |
| +#define PMIF_SWINF_SYS_BUSY 0x01 |
| + |
| +#define PMIF_GET_SWINF_FSM(x) (((x) >> 1) & 0x7) |
| + |
| +#define PMIF_CMD_REG_0 0 |
| +#define PMIF_CMD_REG 1 |
| +#define PMIF_CMD_EXT_REG 2 |
| +#define PMIF_CMD_EXT_REG_LONG 3 |
| +/* 0: SPI, 1: SPMI */ |
| +#define PMIF_PMIFID_SPI 0 |
| +#define PMIF_PMIFID_SPMI0 0 |
| +#define PMIF_PMIFID_SPMI1 1 |
| + |
| +struct pmif { |
| + void __iomem *base; |
| + const u32 *regs; |
| + void __iomem *spmimst_base; |
| + const u32 *spmimst_regs; |
| + void __iomem *infra_base; |
| + const u32 *infra_regs; |
| + void __iomem *topckgen_base; |
| + const u32 *topckgen_regs; |
| + const u32 *dbgregs; |
| + u32 swinf_ch_start; |
| + u32 ap_swinf_no; |
| + int write; |
| + int pmifid; |
| + int grpid; |
| + raw_spinlock_t lock; |
| + struct spmi_controller *spmic; |
| + struct clk *pmif_sys_ck; |
| + struct clk *pmif_tmr_ck; |
| + struct clk *spmimst_clk_mux; |
| + int (*cmd)(struct spmi_controller *ctrl, unsigned int opcode); |
| + int (*read_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| + u16 addr, u8 *buf, size_t len); |
| + int (*write_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| + u16 addr, const u8 *buf, size_t len); |
| + void (*pmif_enable_clk_set)(struct pmif *arb); |
| + void (*pmif_force_normal_mode)(struct pmif *arb); |
| + void (*pmif_enable_swinf)(struct pmif *arb, unsigned int chan_no, |
| + unsigned int swinf_no); |
| + void (*pmif_enable_cmd_issue)(struct pmif *arb, bool en); |
| + void (*pmif_enable)(struct pmif *arb); |
| + int (*is_pmif_init_done)(struct pmif *arb); |
| +}; |
| + |
| +enum pmif_regs { |
| + PMIF_INIT_DONE, |
| + PMIF_INF_EN, |
| + PMIF_ARB_EN, |
| + PMIF_CMDISSUE_EN, |
| + PMIF_TIMER_CTRL, |
| + PMIF_SPI_MODE_CTRL, |
| + PMIF_IRQ_EVENT_EN_0, |
| + PMIF_IRQ_FLAG_0, |
| + PMIF_IRQ_CLR_0, |
| + PMIF_IRQ_EVENT_EN_1, |
| + PMIF_IRQ_FLAG_1, |
| + PMIF_IRQ_CLR_1, |
| + PMIF_IRQ_EVENT_EN_2, |
| + PMIF_IRQ_FLAG_2, |
| + PMIF_IRQ_CLR_2, |
| + PMIF_IRQ_EVENT_EN_3, |
| + PMIF_IRQ_FLAG_3, |
| + PMIF_IRQ_CLR_3, |
| + PMIF_IRQ_EVENT_EN_4, |
| + PMIF_IRQ_FLAG_4, |
| + PMIF_IRQ_CLR_4, |
| + PMIF_WDT_EVENT_EN_0, |
| + PMIF_WDT_FLAG_0, |
| + PMIF_WDT_EVENT_EN_1, |
| + PMIF_WDT_FLAG_1, |
| + PMIF_SWINF_0_STA, |
| + PMIF_SWINF_0_WDATA_31_0, |
| + PMIF_SWINF_0_RDATA_31_0, |
| + PMIF_SWINF_0_ACC, |
| + PMIF_SWINF_0_VLD_CLR, |
| + PMIF_SWINF_1_STA, |
| + PMIF_SWINF_1_WDATA_31_0, |
| + PMIF_SWINF_1_RDATA_31_0, |
| + PMIF_SWINF_1_ACC, |
| + PMIF_SWINF_1_VLD_CLR, |
| + PMIF_SWINF_2_STA, |
| + PMIF_SWINF_2_WDATA_31_0, |
| + PMIF_SWINF_2_RDATA_31_0, |
| + PMIF_SWINF_2_ACC, |
| + PMIF_SWINF_2_VLD_CLR, |
| + PMIF_SWINF_3_STA, |
| + PMIF_SWINF_3_WDATA_31_0, |
| + PMIF_SWINF_3_RDATA_31_0, |
| + PMIF_SWINF_3_ACC, |
| + PMIF_SWINF_3_VLD_CLR, |
| +}; |
| + |
| +static const u32 mt6xxx_regs[] = { |
| + [PMIF_INIT_DONE] = 0x0000, |
| + [PMIF_INF_EN] = 0x0024, |
| + [PMIF_ARB_EN] = 0x0150, |
| + [PMIF_CMDISSUE_EN] = 0x03B4, |
| + [PMIF_TIMER_CTRL] = 0x03E0, |
| + [PMIF_SPI_MODE_CTRL] = 0x0400, |
| + [PMIF_IRQ_EVENT_EN_0] = 0x0418, |
| + [PMIF_IRQ_FLAG_0] = 0x0420, |
| + [PMIF_IRQ_CLR_0] = 0x0424, |
| + [PMIF_IRQ_EVENT_EN_1] = 0x0428, |
| + [PMIF_IRQ_FLAG_1] = 0x0430, |
| + [PMIF_IRQ_CLR_1] = 0x0434, |
| + [PMIF_IRQ_EVENT_EN_2] = 0x0438, |
| + [PMIF_IRQ_FLAG_2] = 0x0440, |
| + [PMIF_IRQ_CLR_2] = 0x0444, |
| + [PMIF_IRQ_EVENT_EN_3] = 0x0448, |
| + [PMIF_IRQ_FLAG_3] = 0x0450, |
| + [PMIF_IRQ_CLR_3] = 0x0454, |
| + [PMIF_IRQ_EVENT_EN_4] = 0x0458, |
| + [PMIF_IRQ_FLAG_4] = 0x0460, |
| + [PMIF_IRQ_CLR_4] = 0x0464, |
| + [PMIF_WDT_EVENT_EN_0] = 0x046C, |
| + [PMIF_WDT_FLAG_0] = 0x0470, |
| + [PMIF_WDT_EVENT_EN_1] = 0x0474, |
| + [PMIF_WDT_FLAG_1] = 0x0478, |
| + [PMIF_SWINF_0_ACC] = 0x0C00, |
| + [PMIF_SWINF_0_WDATA_31_0] = 0x0C04, |
| + [PMIF_SWINF_0_RDATA_31_0] = 0x0C14, |
| + [PMIF_SWINF_0_VLD_CLR] = 0x0C24, |
| + [PMIF_SWINF_0_STA] = 0x0C28, |
| + [PMIF_SWINF_1_ACC] = 0x0C40, |
| + [PMIF_SWINF_1_WDATA_31_0] = 0x0C44, |
| + [PMIF_SWINF_1_RDATA_31_0] = 0x0C54, |
| + [PMIF_SWINF_1_VLD_CLR] = 0x0C64, |
| + [PMIF_SWINF_1_STA] = 0x0C68, |
| + [PMIF_SWINF_2_ACC] = 0x0C80, |
| + [PMIF_SWINF_2_WDATA_31_0] = 0x0C84, |
| + [PMIF_SWINF_2_RDATA_31_0] = 0x0C94, |
| + [PMIF_SWINF_2_VLD_CLR] = 0x0CA4, |
| + [PMIF_SWINF_2_STA] = 0x0CA8, |
| + [PMIF_SWINF_3_ACC] = 0x0CC0, |
| + [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4, |
| + [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4, |
| + [PMIF_SWINF_3_VLD_CLR] = 0x0CE4, |
| + [PMIF_SWINF_3_STA] = 0x0CE8, |
| +}; |
| + |
| +enum spmi_regs { |
| + SPMI_OP_ST_CTRL, |
| + SPMI_GRP_ID_EN, |
| + SPMI_OP_ST_STA, |
| + SPMI_MST_SAMPL, |
| + SPMI_MST_REQ_EN, |
| + SPMI_REC_CTRL, |
| + SPMI_REC0, |
| + SPMI_REC1, |
| + SPMI_REC2, |
| + SPMI_REC3, |
| + SPMI_REC4, |
| + SPMI_MST_DBG, |
| +}; |
| + |
| +static const u32 mt6xxx_spmi_regs[] = { |
| + [SPMI_OP_ST_CTRL] = 0x0000, |
| + [SPMI_GRP_ID_EN] = 0x0004, |
| + [SPMI_OP_ST_STA] = 0x0008, |
| + [SPMI_MST_SAMPL] = 0x000c, |
| + [SPMI_MST_REQ_EN] = 0x0010, |
| + [SPMI_REC_CTRL] = 0x0040, |
| + [SPMI_REC0] = 0x0044, |
| + [SPMI_REC1] = 0x0048, |
| + [SPMI_REC2] = 0x004c, |
| + [SPMI_REC3] = 0x0050, |
| + [SPMI_REC4] = 0x0054, |
| + [SPMI_MST_DBG] = 0x00fc, |
| +}; |
| + |
| +enum { |
| + SPMI_OP_ST_BUSY = 1, |
| + SPMI_OP_ST_ACK = 0, |
| + SPMI_OP_ST_NACK = 1 |
| +}; |
| + |
| +enum { |
| + SPMI_RCS_SR_BIT, |
| + SPMI_RCS_A_BIT |
| +}; |
| + |
| +enum { |
| + SPMI_RCS_MST_W = 1, |
| + SPMI_RCS_SLV_W = 3 |
| +}; |
| + |
| +enum infra_regs { |
| + MODULE_SW_CG_0_SET, |
| + MODULE_SW_CG_0_CLR, |
| + MODULE_SW_CG_2_SET, |
| + MODULE_SW_CG_2_CLR, |
| + PMICW_CLOCK_CTRL, |
| + INFRA_GLOBALCON_RST2_SET, |
| + INFRA_GLOBALCON_RST2_CLR, |
| +}; |
| + |
| +static const u32 mt6xxx_infra_regs[] = { |
| + [MODULE_SW_CG_0_SET] = 0x0080, |
| + [MODULE_SW_CG_0_CLR] = 0x0084, |
| + [MODULE_SW_CG_2_SET] = 0x00a4, |
| + [MODULE_SW_CG_2_CLR] = 0x00a8, |
| + [PMICW_CLOCK_CTRL] = 0x0108, |
| + [INFRA_GLOBALCON_RST2_SET] = 0x0140, |
| + [INFRA_GLOBALCON_RST2_CLR] = 0x0144, |
| +}; |
| + |
| +enum topckgen_regs { |
| + CLK_CFG_UPDATE1, |
| + CLK_CFG_UPDATE2, |
| + WDT_SWSYSRST2, |
| + CLK_CFG_8_CLR, |
| + CLK_CFG_16, |
| + CLK_CFG_16_CLR, |
| +}; |
| + |
| +static const u32 mt6xxx_topckgen_regs[] = { |
| + [CLK_CFG_UPDATE1] = 0x0008, |
| + [CLK_CFG_UPDATE2] = 0x000c, |
| + [WDT_SWSYSRST2] = 0x0090, |
| + [CLK_CFG_8_CLR] = 0x0098, |
| + [CLK_CFG_16] = 0x0110, |
| + [CLK_CFG_16_CLR] = 0x0118, |
| +}; |
| + |
| +enum { |
| + IRQ_PMIC_CMD_ERR_PARITY_ERR = 17, |
| + IRQ_PMIF_ACC_VIO = 20, |
| + IRQ_PMIC_ACC_VIO = 21, |
| + IRQ_LAT_LIMIT_REACHED = 6, |
| + IRQ_HW_MONITOR = 7, |
| + IRQ_WDT = 8 |
| +}; |
| + |
| +/* |
| + * pmif define for FSM |
| + */ |
| +static bool pmif_is_fsm_idle(struct pmif *arb) |
| +{ |
| + u32 offset = 0, reg_rdata = 0; |
| + |
| + offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no); |
| + reg_rdata = readl(arb->base + offset); |
| + return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_IDLE; |
| +} |
| + |
| +static bool pmif_is_fsm_vldclr(struct pmif *arb) |
| +{ |
| + u32 offset = 0, reg_rdata = 0; |
| + |
| + offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no); |
| + reg_rdata = readl(arb->base + offset); |
| + return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_WFVLDCLR; |
| +} |
| +static void pmif_leave_fsm_vldclr(struct pmif *arb) |
| +{ |
| + u32 offset = 0; |
| + |
| + offset = arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no); |
| + if (pmif_is_fsm_vldclr(arb)) |
| + writel(0x1, arb->base + offset); |
| +} |
| + |
| +static int pmif_wait_for_state(struct spmi_controller *ctrl, |
| + bool (*fp)(struct pmif *)) |
| +{ |
| + struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
| + unsigned long timeout; |
| + |
| + timeout = jiffies + usecs_to_jiffies(10000); |
| + do { |
| + if (time_after(jiffies, timeout)) |
| + return fp(arb) ? 0 : -ETIMEDOUT; |
| + if (fp(arb)) |
| + return 0; |
| + } while (1); |
| +} |
| + |
| +/* |
| + * Function : pmif_readl() |
| + * Description : mtk pmif controller read api |
| + * Parameter : |
| + * Return : |
| + */ |
| +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg) |
| +{ |
| + return readl(arb->base + arb->regs[reg]); |
| +} |
| + |
| +/* |
| + * Function : pmif_writel() |
| + * Description : mtk pmif controller write api |
| + * Parameter : |
| + * Return : |
| + */ |
| +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg) |
| +{ |
| + writel(val, arb->base + arb->regs[reg]); |
| +} |
| +/* |
| + * Function : mtk_spmi_readl() |
| + * Description : mtk spmi controller read api |
| + * Parameter : |
| + * Return : |
| + */ |
| +u32 mtk_spmi_readl(struct pmif *arb, enum spmi_regs reg) |
| +{ |
| + return readl(arb->spmimst_base + arb->spmimst_regs[reg]); |
| +} |
| + |
| +/* |
| + * Function : mtk_spmi_writel() |
| + * Description : mtk spmi controller write api |
| + * Parameter : |
| + * Return : |
| + */ |
| +void mtk_spmi_writel(struct pmif *arb, u32 val, |
| + enum spmi_regs reg) |
| +{ |
| + writel(val, arb->spmimst_base + arb->spmimst_regs[reg]); |
| +} |
| + |
| +static void pmif_enable_soft_reset(struct pmif *arb) |
| +{ |
| + writel(0x1 << 14, |
| + arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_SET]); |
| + writel(0x1 << 14, |
| + arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_CLR]); |
| +} |
| + |
| +static void pmif_spmi_enable_clk_set(struct pmif *arb) |
| +{ |
| + writel((0x1 << 15) | (0x1 << 12) | (0x7 << 8), |
| + arb->topckgen_base + arb->topckgen_regs[CLK_CFG_8_CLR]); |
| + writel(0x1 << 2, |
| + arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE1]); |
| + |
| + /* sys_ck cg enable, turn off clock */ |
| + writel(0x0000000f, |
| + arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_SET]); |
| + /* turn off clock */ |
| + writel(0x00000100, |
| + arb->infra_base + arb->infra_regs[MODULE_SW_CG_2_SET]); |
| + |
| + /* toggle SPMI sw reset */ |
| + pmif_enable_soft_reset(arb); |
| + |
| + /* sys_ck cg enable, turn on clock */ |
| + writel(0x0000000f, |
| + arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_CLR]); |
| + /* turn on clock */ |
| + writel(0x00000100, |
| + arb->infra_base + arb->infra_regs[MODULE_SW_CG_2_CLR]); |
| +} |
| + |
| +static void pmif_spmi_force_normal_mode(struct pmif *arb) |
| +{ |
| + /* Force SPMI in normal mode. */ |
| + pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) & (~(0x3 << 9)), |
| + PMIF_SPI_MODE_CTRL); |
| + pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) | (0x1 << 9), |
| + PMIF_SPI_MODE_CTRL); |
| + |
| +} |
| + |
| +static void pmif_spmi_enable_swinf(struct pmif *arb, unsigned int chan_no, |
| + unsigned int swinf_no) |
| +{ |
| + /* Enable swinf */ |
| + pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_INF_EN); |
| + |
| + /* Enable arbitration */ |
| + pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_ARB_EN); |
| + |
| +} |
| + |
| +static void pmif_spmi_enable_cmd_issue(struct pmif *arb, bool en) |
| +{ |
| + /* Enable cmdIssue */ |
| + pmif_writel(arb, en, PMIF_CMDISSUE_EN); |
| + |
| +} |
| + |
| +static void pmif_spmi_enable(struct pmif *arb) |
| +{ |
| + pmif_writel(arb, 0x2F5, PMIF_INF_EN); |
| + pmif_writel(arb, 0x2F5, PMIF_ARB_EN); |
| + pmif_writel(arb, 0x3, PMIF_TIMER_CTRL); |
| + pmif_writel(arb, 0x1, PMIF_INIT_DONE); |
| + |
| +} |
| + |
| +static int mtk_spmi_ctrl_op_st(struct spmi_controller *ctrl, |
| + u8 opc, u8 sid) |
| +{ |
| + struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
| + u32 rdata = 0x0; |
| + u8 cmd = 0; |
| + |
| + /* Check the opcode */ |
| + if (opc == SPMI_CMD_RESET) |
| + cmd = 0; |
| + else if (opc == SPMI_CMD_SLEEP) |
| + cmd = 1; |
| + else if (opc == SPMI_CMD_SHUTDOWN) |
| + cmd = 2; |
| + else if (opc == SPMI_CMD_WAKEUP) |
| + cmd = 3; |
| + |
| + mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); |
| + |
| + rdata = mtk_spmi_readl(arb, SPMI_OP_ST_CTRL); |
| + pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata); |
| + |
| + do { |
| + rdata = mtk_spmi_readl(arb, SPMI_OP_ST_STA); |
| + pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata); |
| + } while ((rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY); |
| + |
| + return 0; |
| +} |
| + |
| +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) |
| +{ |
| + return mtk_spmi_ctrl_op_st(ctrl, opc, sid); |
| +} |
| + |
| +static int mtk_spmi_enable_group_id(struct pmif *arb, u8 grpid) |
| +{ |
| + mtk_spmi_writel(arb, 0x1 << grpid, SPMI_GRP_ID_EN); |
| + |
| + return 0; |
| +} |
| + |
| +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| + u16 addr, u8 *buf, size_t len) |
| +{ |
| + struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
| + int ret = 0, write = 0x0; |
| + u32 offset = 0, data = 0; |
| + u8 bc = len - 1; |
| + unsigned long flags; |
| + |
| + /* Check for argument validation. */ |
| + if ((arb->ap_swinf_no & ~(0x3)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((arb->pmifid & ~(0x1)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((sid & ~(0xf)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((bc & ~(0x1)) != 0x0) |
| + return -EINVAL; |
| + |
| + /* Check the opcode */ |
| + if (opc >= 0x60 && opc <= 0x7F) |
| + opc = PMIF_CMD_REG; |
| + else if (opc >= 0x20 && opc <= 0x2F) |
| + opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */ |
| + else if (opc >= 0x38 && opc <= 0x3F) |
| + opc = PMIF_CMD_EXT_REG_LONG; |
| + else |
| + return -EINVAL; |
| + |
| + raw_spin_lock_irqsave(&arb->lock, flags); |
| + /* Wait for Software Interface FSM state to be IDLE. */ |
| + ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle); |
| + if (ret) { |
| + pmif_leave_fsm_vldclr(arb); |
| + raw_spin_unlock_irqrestore(&arb->lock, flags); |
| + return ret; |
| + } |
| + /* Send the command. */ |
| + offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no); |
| + writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr, |
| + arb->base + offset); |
| + |
| + /* Wait for Software Interface FSM state to be WFVLDCLR, |
| + * |
| + * read the data and clear the valid flag. |
| + */ |
| + if (write == 0) { |
| + ret = pmif_wait_for_state(ctrl, pmif_is_fsm_vldclr); |
| + if (ret) { |
| + raw_spin_unlock_irqrestore(&arb->lock, flags); |
| + return ret; |
| + } |
| + offset = |
| + arb->regs[PMIF_SWINF_0_RDATA_31_0] + (0x40 * arb->ap_swinf_no); |
| + |
| + data = readl(arb->base + offset); |
| + memcpy(buf, &data, (bc & 3) + 1); |
| + offset = |
| + arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no); |
| + |
| + writel(0x1, arb->base + offset); |
| + } |
| + |
| + raw_spin_unlock_irqrestore(&arb->lock, flags); |
| + |
| + return 0x0; |
| +} |
| + |
| +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| + u16 addr, const u8 *buf, size_t len) |
| +{ |
| + struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
| + int ret = 0, write = 0x1; |
| + u32 offset = 0, data = 0; |
| + u8 bc = len - 1; |
| + unsigned long flags = 0; |
| + |
| + /* Check for argument validation. */ |
| + if ((arb->ap_swinf_no & ~(0x3)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((arb->pmifid & ~(0x1)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((sid & ~(0xf)) != 0x0) |
| + return -EINVAL; |
| + |
| + if ((bc & ~(0x1)) != 0x0) |
| + return -EINVAL; |
| + |
| + /* Check the opcode */ |
| + if (opc >= 0x40 && opc <= 0x5F) |
| + opc = PMIF_CMD_REG; |
| + else if (opc <= 0x0F) |
| + opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */ |
| + else if (opc >= 0x30 && opc <= 0x37) |
| + opc = PMIF_CMD_EXT_REG_LONG; |
| + else if (opc >= 0x80) |
| + opc = PMIF_CMD_REG_0; |
| + else |
| + return -EINVAL; |
| + |
| + raw_spin_lock_irqsave(&arb->lock, flags); |
| + /* Wait for Software Interface FSM state to be IDLE. */ |
| + ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle); |
| + if (ret) { |
| + pmif_leave_fsm_vldclr(arb); |
| + raw_spin_unlock_irqrestore(&arb->lock, flags); |
| + return ret; |
| + } |
| + /* Set the write data. */ |
| + offset = arb->regs[PMIF_SWINF_0_WDATA_31_0] + (0x40 * arb->ap_swinf_no); |
| + if (write == 1) { |
| + memcpy(&data, buf, (bc & 3) + 1); |
| + writel(data, arb->base + offset); |
| + } |
| + |
| + /* Send the command. */ |
| + offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no); |
| + writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr, |
| + arb->base + offset); |
| + raw_spin_unlock_irqrestore(&arb->lock, flags); |
| + |
| + return 0x0; |
| +} |
| + |
| +int is_pmif_spmi_init_done(struct pmif *arb) |
| +{ |
| + int ret = 0; |
| + |
| + ret = pmif_readl(arb, PMIF_INIT_DONE); |
| + if ((ret & 0x1) == 1) |
| + return 0; |
| + |
| + return -1; |
| +} |
| + |
| +static int mtk_spmi_config_master(struct pmif *arb, bool en) |
| +{ |
| + /* Software reset */ |
| + writel(0x85 << 24 | 0x1 << 4, |
| + arb->topckgen_base + arb->topckgen_regs[WDT_SWSYSRST2]); |
| + |
| + writel(0x7 | (0x1 << 4) | (0x1 << 7), |
| + arb->topckgen_base + arb->topckgen_regs[CLK_CFG_16_CLR]); |
| + writel(0x1 << 2, |
| + arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]); |
| + |
| + /* Software reset */ |
| + writel(0x85 << 24, |
| + arb->topckgen_base + arb->topckgen_regs[WDT_SWSYSRST2]); |
| + |
| + /* Enable SPMI */ |
| + mtk_spmi_writel(arb, en, SPMI_MST_REQ_EN); |
| + |
| + return 0; |
| +} |
| + |
| +static int mtk_spmi_cali_rd_clock_polarity(struct pmif *arb) |
| +{ |
| + unsigned int dly = 1, pol = 1; |
| + |
| + /* Indicate sampling clock polarity, 1: Positive 0: Negative */ |
| + mtk_spmi_writel(arb, (dly << 0x1) | pol, SPMI_MST_SAMPL); |
| + |
| + return 0; |
| +} |
| + |
| +static int mtk_spmimst_init(struct platform_device *pdev, struct pmif *arb) |
| +{ |
| + struct resource *res = NULL; |
| + int err = 0, i = 0; |
| + |
| + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spmimst"); |
| + arb->spmimst_base = devm_ioremap_resource(&pdev->dev, res); |
| + if (IS_ERR(arb->spmimst_base)) { |
| + err = PTR_ERR(arb->spmimst_base); |
| + return err; |
| + } |
| + |
| + err = of_property_read_u32(pdev->dev.of_node, "grpid", &arb->grpid); |
| + if (err) { |
| + dev_notice(&pdev->dev, "[SPMIMST]:grpid unspecified.\n"); |
| + return -EINVAL; |
| + } |
| + /* set group id */ |
| + mtk_spmi_enable_group_id(arb, arb->grpid); |
| + |
| + /* if spmimst not enabled, enable it */ |
| + if ((mtk_spmi_readl(arb, SPMI_MST_REQ_EN) & 0x1) != 0x1) { |
| + dev_info(&pdev->dev, "[SPMIMST]:enable spmimst.\n"); |
| + mtk_spmi_config_master(arb, true); |
| + for (i = 0; i < 3; i++) |
| + mtk_spmi_cali_rd_clock_polarity(arb); |
| + } |
| + pr_notice("[SPMIMST]:%s done\n", __func__); |
| + |
| + return 0; |
| +} |
| + |
| +static struct pmif mt6xxx_pmif_arb[] = { |
| + { |
| + .base = 0x0, |
| + .regs = mt6xxx_regs, |
| + .spmimst_base = 0x0, |
| + .spmimst_regs = mt6xxx_spmi_regs, |
| + .infra_base = 0x0, |
| + .infra_regs = mt6xxx_infra_regs, |
| + .topckgen_base = 0x0, |
| + .topckgen_regs = mt6xxx_topckgen_regs, |
| + .swinf_ch_start = 0, |
| + .ap_swinf_no = 0, |
| + .write = 0x0, |
| + .pmifid = PMIF_PMIFID_SPMI1, |
| + .spmic = 0x0, |
| + .read_cmd = pmif_spmi_read_cmd, |
| + .write_cmd = pmif_spmi_write_cmd, |
| + .pmif_enable_clk_set = pmif_spmi_enable_clk_set, |
| + .pmif_force_normal_mode = pmif_spmi_force_normal_mode, |
| + .pmif_enable_swinf = pmif_spmi_enable_swinf, |
| + .pmif_enable_cmd_issue = pmif_spmi_enable_cmd_issue, |
| + .pmif_enable = pmif_spmi_enable, |
| + .is_pmif_init_done = is_pmif_spmi_init_done, |
| + }, |
| +}; |
| + |
| +static const struct of_device_id pmif_match_table[] = { |
| + { |
| + .compatible = "mediatek,pmif", |
| + .data = &mt6xxx_pmif_arb, |
| + }, { |
| + /* sentinel */ |
| + }, |
| +}; |
| +MODULE_DEVICE_TABLE(of, pmif_match_table); |
| + |
| +static int pmif_probe(struct platform_device *pdev) |
| +{ |
| + struct device_node *node = NULL; |
| + const struct of_device_id *of_id = |
| + of_match_device(pmif_match_table, &pdev->dev); |
| + struct spmi_controller *ctrl = NULL; |
| + struct pmif *arb = NULL; |
| + struct resource *res = NULL; |
| + u32 swinf_ch_start = 0, ap_swinf_no = 0; |
| + int err = 0; |
| + |
| + if (!of_id) { |
| + dev_notice(&pdev->dev, "[PMIF]:Error: No device match found\n"); |
| + return -ENODEV; |
| + } |
| + |
| + ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb)); |
| + if (!ctrl) |
| + return -ENOMEM; |
| + |
| + /* re-assign of_id->data */ |
| + spmi_controller_set_drvdata(ctrl, (void *)of_id->data); |
| + arb = spmi_controller_get_drvdata(ctrl); |
| + |
| + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmif"); |
| + arb->base = devm_ioremap_resource(&pdev->dev, res); |
| + if (IS_ERR(arb->base)) { |
| + err = PTR_ERR(arb->base); |
| + goto err_put_ctrl; |
| + } |
| + |
| + /* pmif is not initialized, just init once */ |
| + node = of_find_compatible_node(NULL, NULL, |
| + "mediatek,mt8192-infracfg"); |
| + arb->infra_base = of_iomap(node, 0); |
| + dev_info(&pdev->dev, "[PMIF]:mtk-pmif arb infra ao base:0x%x\n", |
| + arb->infra_base); |
| + if (IS_ERR(arb->infra_base)) { |
| + err = PTR_ERR(arb->infra_base); |
| + goto err_put_ctrl; |
| + } |
| + |
| + node = of_find_compatible_node(NULL, NULL, |
| + "mediatek,mt8192-topckgen"); |
| + arb->topckgen_base = of_iomap(node, 0); |
| + dev_info(&pdev->dev, "[PMIF]:mtk-pmif arb topckgen base:0x%x\n", |
| + arb->topckgen_base); |
| + if (IS_ERR(arb->topckgen_base)) { |
| + err = PTR_ERR(arb->topckgen_base); |
| + goto err_put_ctrl; |
| + } |
| + |
| + /* get pmif infracfg_ao clock */ |
| + arb->pmif_sys_ck = devm_clk_get(&pdev->dev, "pmif_sys_ck"); |
| + if (IS_ERR(arb->pmif_sys_ck)) { |
| + dev_notice(&pdev->dev, "[PMIF]:failed to get ap clock: %ld\n", |
| + PTR_ERR(arb->pmif_sys_ck)); |
| + return PTR_ERR(arb->pmif_sys_ck); |
| + } |
| + |
| + arb->pmif_tmr_ck = devm_clk_get(&pdev->dev, "pmif_tmr_ck"); |
| + if (IS_ERR(arb->pmif_tmr_ck)) { |
| + dev_notice(&pdev->dev, "[PMIF]:failed to get tmr clock: %ld\n", |
| + PTR_ERR(arb->pmif_tmr_ck)); |
| + return PTR_ERR(arb->pmif_tmr_ck); |
| + } |
| + |
| + /* get spmimst topckgen clock */ |
| + arb->spmimst_clk_mux = devm_clk_get(&pdev->dev, "spmimst_clk_mux"); |
| + if (IS_ERR(arb->spmimst_clk_mux)) { |
| + dev_notice(&pdev->dev, "[SPMIMST]:failed to get clock: %ld\n", |
| + PTR_ERR(arb->spmimst_clk_mux)); |
| + return PTR_ERR(arb->spmimst_clk_mux); |
| + } |
| + |
| + err = clk_prepare_enable(arb->spmimst_clk_mux); |
| + if (err) |
| + return err; |
| + |
| + err = of_property_read_u32(pdev->dev.of_node, |
| + "swinf_ch_start", &swinf_ch_start); |
| + if (err) { |
| + dev_notice(&pdev->dev, "[PMIF]:swinf_ch_start unspecified.\n"); |
| + goto err_put_ctrl; |
| + } |
| + arb->swinf_ch_start = swinf_ch_start; |
| + |
| + err = of_property_read_u32(pdev->dev.of_node, |
| + "ap_swinf_no", &ap_swinf_no); |
| + if (err) { |
| + dev_notice(&pdev->dev, "[PMIF]:ap_swinf_no unspecified.\n"); |
| + goto err_put_ctrl; |
| + } |
| + arb->ap_swinf_no = ap_swinf_no; |
| + |
| + if (arb->is_pmif_init_done(arb) != 0) { |
| + /* pmif initialize start */ |
| + arb->pmif_enable_clk_set(arb); |
| + arb->pmif_force_normal_mode(arb); |
| + /* Enable SWINF and arbitration for AP. */ |
| + arb->pmif_enable_swinf(arb, |
| + arb->swinf_ch_start, arb->ap_swinf_no); |
| + arb->pmif_enable_cmd_issue(arb, true); |
| + |
| + arb->pmif_enable(arb); |
| + arb->is_pmif_init_done(arb); |
| + /* pmif initialize end */ |
| + } |
| + |
| + raw_spin_lock_init(&arb->lock); |
| + |
| + ctrl->cmd = pmif_arb_cmd; |
| + ctrl->read_cmd = pmif_spmi_read_cmd; |
| + ctrl->write_cmd = pmif_spmi_write_cmd; |
| + |
| + if (arb->is_pmif_init_done(arb) == 0) { |
| + /* pmif already done, call spmi master driver init */ |
| + err = mtk_spmimst_init(pdev, arb); |
| + if (err) |
| + goto err_put_ctrl; |
| + } |
| + |
| + platform_set_drvdata(pdev, ctrl); |
| + |
| + err = spmi_controller_add(ctrl); |
| + if (err) |
| + goto err_domain_remove; |
| + |
| + return 0; |
| + |
| +err_domain_remove: |
| + clk_disable_unprepare(arb->spmimst_clk_mux); |
| +err_put_ctrl: |
| + spmi_controller_put(ctrl); |
| + return err; |
| +} |
| + |
| +static int pmif_remove(struct platform_device *pdev) |
| +{ |
| + struct spmi_controller *ctrl = platform_get_drvdata(pdev); |
| + |
| + spmi_controller_remove(ctrl); |
| + spmi_controller_put(ctrl); |
| + return 0; |
| +} |
| + |
| +static struct platform_driver pmif_driver = { |
| + .probe = pmif_probe, |
| + .remove = pmif_remove, |
| + .driver = { |
| + .name = "pmif", |
| + .of_match_table = of_match_ptr(pmif_match_table), |
| + }, |
| +}; |
| + |
| +static int __init mtk_pmif_init(void) |
| +{ |
| + int ret = 0; |
| + |
| + ret = platform_driver_register(&pmif_driver); |
| + if (ret) |
| + return -ENODEV; |
| + return 0; |
| +} |
| +postcore_initcall(mtk_pmif_init); |
| + |
| +MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>"); |
| +MODULE_DESCRIPTION("SPMI Driver for MediaTek MT8192"); |
| +MODULE_LICENSE("GPL"); |
| diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c |
| index c16b60f645a4de6100a043143fb42386cbc65a7a..54a25ddac3953c2a7c3428608f5295d09e90b8d4 100644 |
| --- a/drivers/spmi/spmi.c |
| +++ b/drivers/spmi/spmi.c |
| @@ -357,6 +357,17 @@ static int spmi_drv_remove(struct device *dev) |
| return 0; |
| } |
| |
| +static void spmi_drv_shutdown(struct device *dev) |
| +{ |
| + const struct spmi_driver *sdrv = to_spmi_driver(dev->driver); |
| + |
| + if (!sdrv) |
| + return; |
| + |
| + if (sdrv->shutdown) |
| + sdrv->shutdown(to_spmi_device(dev)); |
| +} |
| + |
| static int spmi_drv_uevent(struct device *dev, struct kobj_uevent_env *env) |
| { |
| int ret; |
| @@ -373,6 +384,7 @@ static struct bus_type spmi_bus_type = { |
| .match = spmi_device_match, |
| .probe = spmi_drv_probe, |
| .remove = spmi_drv_remove, |
| + .shutdown = spmi_drv_shutdown, |
| .uevent = spmi_drv_uevent, |
| }; |
| |
| diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c |
| old mode 100644 |
| new mode 100755 |
| index b18a6baef204a60b1ac5071a55fdb25b0280aea5..e02f5a33d24499e30ad0b7b2e48d637fac3474fa |
| --- a/drivers/usb/host/xhci-mtk.c |
| +++ b/drivers/usb/host/xhci-mtk.c |
| @@ -68,11 +68,51 @@ |
| #define SSC_IP_SLEEP_EN BIT(4) |
| #define SSC_SPM_INT_EN BIT(1) |
| |
| +/* mt8192 etc */ |
| +#define SSC_IP_SLEEP_EN_V3 BIT(6) |
| + |
| enum ssusb_uwk_vers { |
| SSUSB_UWK_V1 = 1, |
| SSUSB_UWK_V2, |
| + SSUSB_UWK_V3, |
| }; |
| |
| +int xhci_mtk_runtime_ready; |
| +static void xhci_mtk_seal_work(struct work_struct *work) |
| +{ |
| + struct xhci_hcd_mtk *mtk = container_of(work, struct xhci_hcd_mtk, seal.work); |
| + struct usb_hcd *hcd = mtk->hcd; |
| + struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| + |
| + xhci_info(xhci, "spm unseals xHCI controller\n"); |
| + pm_runtime_get_sync(mtk->dev); |
| +} |
| + |
| +static irqreturn_t xhci_mtk_seal_irq (int irq, void *__hcd) |
| +{ |
| + irqreturn_t rc= IRQ_HANDLED; |
| + struct xhci_hcd_mtk *mtk = __hcd; |
| + struct usb_hcd *hcd = mtk->hcd; |
| + struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| + |
| + disable_irq_nosync(mtk->seal_irq); |
| + |
| + xhci_info(xhci, "seal irq ISR invoked\n"); |
| + schedule_delayed_work(&mtk->seal, 0); |
| + |
| + return rc; |
| +} |
| + |
| +static void xhci_mtk_seal_wakeup_enable(struct xhci_hcd_mtk *mtk, bool enable) |
| +{ |
| + if (mtk && mtk->seal_irq) { |
| + if (enable) |
| + enable_irq(mtk->seal_irq); |
| + else |
| + disable_irq(mtk->seal_irq); |
| + } |
| +} |
| + |
| static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) |
| { |
| struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; |
| @@ -305,6 +345,11 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) |
| msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; |
| val = enable ? msk : 0; |
| break; |
| + case SSUSB_UWK_V3: |
| + reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; |
| + msk = SSC_IP_SLEEP_EN_V3 | SSC_SPM_INT_EN; |
| + val = enable ? msk : 0; |
| + break; |
| default: |
| return; |
| } |
| @@ -470,10 +515,9 @@ static int xhci_mtk_probe(struct platform_device *pdev) |
| return ret; |
| } |
| |
| + pm_runtime_set_active(dev); |
| pm_runtime_enable(dev); |
| - pm_runtime_get_sync(dev); |
| - device_enable_async_suspend(dev); |
| - |
| + pm_runtime_get_noresume(dev); |
| ret = xhci_mtk_ldos_enable(mtk); |
| if (ret) |
| goto disable_pm; |
| @@ -487,6 +531,14 @@ static int xhci_mtk_probe(struct platform_device *pdev) |
| ret = irq; |
| goto disable_clk; |
| } |
| + dev_info(dev, "irq %i\n", irq); |
| + |
| + mtk->seal_irq = platform_get_irq(pdev, 1); |
| + if (mtk->seal_irq < 0) { |
| + ret = mtk->seal_irq; |
| + goto disable_clk; |
| + } |
| + dev_info(dev, "seal_irq %i\n", mtk->seal_irq); |
| |
| /* Initialize dma_mask and coherent_dma_mask to 32-bits */ |
| ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| @@ -558,6 +610,30 @@ static int xhci_mtk_probe(struct platform_device *pdev) |
| if (ret) |
| goto dealloc_usb2_hcd; |
| |
| + INIT_DELAYED_WORK(&mtk->seal, xhci_mtk_seal_work); |
| + snprintf(mtk->seal_descr, sizeof(mtk->seal_descr), "seal%s:usb%d", |
| + hcd->driver->description, hcd->self.busnum); |
| + ret = request_irq(mtk->seal_irq, &xhci_mtk_seal_irq, IRQF_SHARED, |
| + mtk->seal_descr, mtk); |
| + if (ret != 0) { |
| + dev_err(hcd->self.controller, |
| + "seal request interrupt %d failed\n", |
| + mtk->seal_irq); |
| + goto dealloc_usb2_hcd; |
| + } |
| + xhci_mtk_seal_wakeup_enable(mtk, false); |
| + |
| + pm_runtime_set_autosuspend_delay(dev, CONFIG_USB_AUTOSUSPEND_DELAY*1000); |
| + device_enable_async_suspend(dev); |
| + pm_runtime_put_noidle(dev); |
| + |
| + /* |
| + * to expert runtime pm from being on as default. |
| + */ |
| + pm_runtime_allow(dev); |
| + xhci_mtk_runtime_ready = 1; |
| + dev_info(dev, "%s: xhci_mtk_runtime_ready %i", __func__, xhci_mtk_runtime_ready); |
| + |
| return 0; |
| |
| dealloc_usb2_hcd: |
| @@ -592,6 +668,7 @@ static int xhci_mtk_remove(struct platform_device *dev) |
| struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| struct usb_hcd *shared_hcd = xhci->shared_hcd; |
| |
| + xhci_mtk_runtime_ready = 0; |
| usb_remove_hcd(shared_hcd); |
| xhci->shared_hcd = NULL; |
| device_init_wakeup(&dev->dev, false); |
| @@ -630,6 +707,7 @@ static int __maybe_unused xhci_mtk_suspend(struct device *dev) |
| xhci_mtk_host_disable(mtk); |
| xhci_mtk_clks_disable(mtk); |
| usb_wakeup_set(mtk, true); |
| + |
| return 0; |
| } |
| |
| @@ -650,10 +728,171 @@ static int __maybe_unused xhci_mtk_resume(struct device *dev) |
| usb_hcd_poll_rh_status(hcd); |
| return 0; |
| } |
| +static int __maybe_unused xhci_mtk_bus_status(struct device *dev) |
| +{ |
| + int i; |
| + int ret = 0; |
| + int num_ports; |
| + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
| + struct usb_hcd *hcd; |
| + struct xhci_hcd *xhci; |
| + struct xhci_hub *usb2_rhub; |
| + struct xhci_hub *usb3_rhub; |
| + struct xhci_bus_state *bus_state; |
| + struct xhci_port *port; |
| + u32 usb2_suspended_ports = -1; |
| + u32 usb3_suspended_ports = -1; |
| + u16 status; |
| + |
| + if (!mtk->hcd) |
| + return -ESHUTDOWN; |
| + |
| + hcd = mtk->hcd; |
| + xhci = hcd_to_xhci(hcd); |
| + if ((xhci->xhc_state & XHCI_STATE_REMOVING) || |
| + (xhci->xhc_state & XHCI_STATE_HALTED)) { |
| + return -ESHUTDOWN; |
| + } |
| + |
| + usb2_rhub = &xhci->usb2_rhub; |
| + if (usb2_rhub != NULL) { |
| + bus_state = &usb2_rhub->bus_state; |
| + num_ports = usb2_rhub->num_ports; |
| + usb2_suspended_ports = bus_state->suspended_ports; |
| + usb2_suspended_ports ^= (BIT(num_ports) - 1); |
| + usb2_suspended_ports &= (BIT(num_ports) - 1); |
| + for (i = 0; i < num_ports; i++ ) { |
| + if (usb2_suspended_ports & (1UL << i)) { |
| + port = usb2_rhub->ports[i]; |
| + status = readl(port->addr); |
| + xhci_info(xhci, "USB20: portsc[%i]: 0x%04X\n", i, status); |
| + if (!(status & PORT_CONNECT)) |
| + usb2_suspended_ports &= ~(1UL << i); |
| + } |
| + } |
| + |
| + if (usb2_suspended_ports) { |
| + ret = -EBUSY; |
| + goto ebusy; |
| + } |
| + } |
| + |
| + usb3_rhub = &xhci->usb3_rhub; |
| + if (usb3_rhub != NULL) { |
| + bus_state = &usb3_rhub->bus_state; |
| + num_ports = usb3_rhub->num_ports; |
| + usb3_suspended_ports = bus_state->suspended_ports; |
| + usb3_suspended_ports ^= (BIT(num_ports) - 1); |
| + usb3_suspended_ports &= (BIT(num_ports) - 1); |
| + for (i = 0; i < num_ports; i++ ) { |
| + if (usb3_suspended_ports & (1UL << i)) { |
| + port = usb3_rhub->ports[i]; |
| + status = readl(port->addr); |
| + xhci_info(xhci, "USB30: portsc[%i]: 0x%04X\n", i, status); |
| + if (!(status & PORT_CONNECT)) |
| + usb3_suspended_ports &= ~(1UL << i); |
| + } |
| + } |
| + |
| + if (usb3_suspended_ports) { |
| + ret = -EBUSY; |
| + goto ebusy; |
| + } |
| + } |
| + |
| +ebusy: |
| + xhci_info(xhci, "%s: USB20: 0x%08X, USB30: 0x%08X ret: %i\n", |
| + __func__, usb2_suspended_ports, usb3_suspended_ports, ret); |
| + |
| + return ret; |
| +} |
| + |
| +static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev) |
| +{ |
| + int ret = 0; |
| + bool wakeup = device_may_wakeup(dev); |
| + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
| + struct usb_hcd *hcd; |
| + struct xhci_hcd *xhci; |
| + |
| + if (!mtk->hcd) |
| + return -ESHUTDOWN; |
| + |
| + hcd = mtk->hcd; |
| + xhci = hcd_to_xhci(hcd); |
| + if ((xhci->xhc_state & XHCI_STATE_REMOVING) || |
| + (xhci->xhc_state & XHCI_STATE_HALTED)) { |
| + return -ESHUTDOWN; |
| + } |
| + |
| + ret = xhci_mtk_bus_status(dev); |
| + if (wakeup && !ret) { |
| + xhci_mtk_seal_wakeup_enable(mtk, true); |
| + xhci_mtk_suspend(dev); |
| + xhci_dbg(xhci, |
| + "%s: arm seals xHCI controller %i\n", __func__, ret); |
| + } |
| + |
| + xhci_info(xhci, "%s: seals wakeup = %i, ret = %i!\n", __func__, wakeup, ret); |
| + |
| + return ret; |
| +} |
| + |
| +static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev) |
| +{ |
| + int ret = 0; |
| + bool wakeup = device_may_wakeup(dev); |
| + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
| + struct usb_hcd *hcd; |
| + struct xhci_hcd *xhci; |
| + |
| + if (!mtk->hcd) |
| + return -ESHUTDOWN; |
| + |
| + hcd = mtk->hcd; |
| + xhci = hcd_to_xhci(hcd); |
| + if ((xhci->xhc_state & XHCI_STATE_REMOVING) || |
| + (xhci->xhc_state & XHCI_STATE_HALTED)) { |
| + return -ESHUTDOWN; |
| + } |
| + |
| + /* |
| + * Maybe need one extra interrupt to process it!!! |
| + * Who to process these module reinitilization after SPM wakeup |
| + * case 1: himself wakeup, therefore xHCI need reinitilizate also. |
| + * case 2: other-wakeup-source wakeup, therefore, xHCI need reinit |
| + * case 3: user active |
| + */ |
| + if (wakeup) { |
| + xhci_mtk_seal_wakeup_enable(mtk, false); |
| + xhci_mtk_resume(dev); |
| + xhci_dbg(xhci, |
| + "%s: arms unseals xHCI controller\n", __func__); |
| + } |
| + |
| + xhci_info(xhci, "%s: unseals wakeup = %i, ret = %i\n", __func__, wakeup, ret); |
| + |
| + return ret; |
| +} |
| + |
| +static int __maybe_unused xhci_mtk_runtime_idle(struct device *dev) |
| +{ |
| + int ret = 0; |
| + |
| + dev_info(dev, "%s: xhci_mtk_runtime_ready %i", __func__, xhci_mtk_runtime_ready); |
| + if (!xhci_mtk_runtime_ready) |
| + ret = -EAGAIN; |
| + |
| + return ret; |
| +} |
| |
| static const struct dev_pm_ops xhci_mtk_pm_ops = { |
| SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) |
| + SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend, |
| + xhci_mtk_runtime_resume, |
| + xhci_mtk_runtime_idle) |
| }; |
| + |
| #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL |
| |
| #ifdef CONFIG_OF |
| @@ -678,6 +917,7 @@ MODULE_ALIAS("platform:xhci-mtk"); |
| |
| static int __init xhci_mtk_init(void) |
| { |
| + xhci_mtk_runtime_ready = 0; |
| xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); |
| return platform_driver_register(&mtk_xhci_driver); |
| } |
| diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h |
| old mode 100644 |
| new mode 100755 |
| index 5ac458b7d2e0efa406e5db2ca57dfe3dde59e550..a391587ee6298ae1afeb28fef0ecfc8225baeb48 |
| --- a/drivers/usb/host/xhci-mtk.h |
| +++ b/drivers/usb/host/xhci-mtk.h |
| @@ -152,6 +152,9 @@ struct xhci_hcd_mtk { |
| struct regmap *uwk; |
| u32 uwk_reg_base; |
| u32 uwk_vers; |
| + int seal_irq; |
| + struct delayed_work seal; |
| + char seal_descr[32]; /* "seal" + driver + bus # */ |
| }; |
| |
| static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) |
| diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..3c4ad1f968dd792fe6ca9a7e7ec038dd282ac27b |
| --- /dev/null |
| +++ b/include/dt-bindings/clock/mt8192-clk.h |
| @@ -0,0 +1,666 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + */ |
| + |
| +#ifndef _DT_BINDINGS_CLK_MT8192_H |
| +#define _DT_BINDINGS_CLK_MT8192_H |
| + |
| +/* TOPCKGEN */ |
| + |
| +#define CLK_TOP_AXI_SEL 0 |
| +#define CLK_TOP_SPM_SEL 1 |
| +#define CLK_TOP_SCP_SEL 2 |
| +#define CLK_TOP_BUS_AXIMEM_SEL 3 |
| +#define CLK_TOP_DISP_SEL 4 |
| +#define CLK_TOP_MDP_SEL 5 |
| +#define CLK_TOP_IMG1_SEL 6 |
| +#define CLK_TOP_IMG2_SEL 7 |
| +#define CLK_TOP_IPE_SEL 8 |
| +#define CLK_TOP_DPE_SEL 9 |
| +#define CLK_TOP_CAM_SEL 10 |
| +#define CLK_TOP_CCU_SEL 11 |
| +#define CLK_TOP_DSP_SEL 12 |
| +#define CLK_TOP_DSP1_SEL 13 |
| +#define CLK_TOP_DSP1_NPUPLL_SEL 14 |
| +#define CLK_TOP_DSP2_SEL 15 |
| +#define CLK_TOP_DSP2_NPUPLL_SEL 16 |
| +#define CLK_TOP_DSP5_SEL 17 |
| +#define CLK_TOP_DSP5_APUPLL_SEL 18 |
| +#define CLK_TOP_DSP7_SEL 19 |
| +#define CLK_TOP_IPU_IF_SEL 20 |
| +#define CLK_TOP_MFG_REF_SEL 21 |
| +#define CLK_TOP_MFG_PLL_SEL 22 |
| +#define CLK_TOP_CAMTG_SEL 23 |
| +#define CLK_TOP_CAMTG2_SEL 24 |
| +#define CLK_TOP_CAMTG3_SEL 25 |
| +#define CLK_TOP_CAMTG4_SEL 26 |
| +#define CLK_TOP_CAMTG5_SEL 27 |
| +#define CLK_TOP_CAMTG6_SEL 28 |
| +#define CLK_TOP_UART_SEL 29 |
| +#define CLK_TOP_SPI_SEL 30 |
| +#define CLK_TOP_MSDC50_0_H_SEL 31 |
| +#define CLK_TOP_MSDC50_0_SEL 32 |
| +#define CLK_TOP_MSDC30_1_SEL 33 |
| +#define CLK_TOP_MSDC30_2_SEL 34 |
| +#define CLK_TOP_AUDIO_SEL 35 |
| +#define CLK_TOP_AUD_INTBUS_SEL 36 |
| +#define CLK_TOP_PWRAP_ULPOSC_SEL 37 |
| +#define CLK_TOP_ATB_SEL 38 |
| +#define CLK_TOP_SSPM_SEL 39 |
| +#define CLK_TOP_DPI_SEL 40 |
| +#define CLK_TOP_SCAM_SEL 41 |
| +#define CLK_TOP_DISP_PWM_SEL 42 |
| +#define CLK_TOP_USB_TOP_SEL 43 |
| +#define CLK_TOP_SSUSB_XHCI_SEL 44 |
| +#define CLK_TOP_I2C_SEL 45 |
| +#define CLK_TOP_SENINF_SEL 46 |
| +#define CLK_TOP_SENINF1_SEL 47 |
| +#define CLK_TOP_SENINF2_SEL 48 |
| +#define CLK_TOP_SENINF3_SEL 49 |
| +#define CLK_TOP_TL_SEL 50 |
| +#define CLK_TOP_DXCC_SEL 51 |
| +#define CLK_TOP_AUD_ENGEN1_SEL 52 |
| +#define CLK_TOP_AUD_ENGEN2_SEL 53 |
| +#define CLK_TOP_AES_UFSFDE_SEL 54 |
| +#define CLK_TOP_UFS_SEL 55 |
| +#define CLK_TOP_AUD_1_SEL 56 |
| +#define CLK_TOP_AUD_2_SEL 57 |
| +#define CLK_TOP_ADSP_SEL 58 |
| +#define CLK_TOP_DPMAIF_MAIN_SEL 59 |
| +#define CLK_TOP_VENC_SEL 60 |
| +#define CLK_TOP_VDEC_SEL 61 |
| +#define CLK_TOP_CAMTM_SEL 62 |
| +#define CLK_TOP_PWM_SEL 63 |
| +#define CLK_TOP_AUDIO_H_SEL 64 |
| +#define CLK_TOP_SPMI_MST_SEL 65 |
| +#define CLK_TOP_AES_MSDCFDE_SEL 66 |
| +#define CLK_TOP_MCUPM_SEL 67 |
| +#define CLK_TOP_SFLASH_SEL 68 |
| +#define CLK_TOP_APLL_I2S0_M_SEL 69 |
| +#define CLK_TOP_APLL_I2S1_M_SEL 70 |
| +#define CLK_TOP_APLL_I2S2_M_SEL 71 |
| +#define CLK_TOP_APLL_I2S3_M_SEL 72 |
| +#define CLK_TOP_APLL_I2S4_M_SEL 73 |
| +#define CLK_TOP_APLL_I2S5_M_SEL 74 |
| +#define CLK_TOP_APLL_I2S6_M_SEL 75 |
| +#define CLK_TOP_APLL_I2S7_M_SEL 76 |
| +#define CLK_TOP_APLL_I2S8_M_SEL 77 |
| +#define CLK_TOP_APLL_I2S9_M_SEL 78 |
| +#define CLK_TOP_MAINPLL_D3 79 |
| +#define CLK_TOP_MAINPLL_D4 80 |
| +#define CLK_TOP_MAINPLL_D4_D2 81 |
| +#define CLK_TOP_MAINPLL_D4_D4 82 |
| +#define CLK_TOP_MAINPLL_D4_D8 83 |
| +#define CLK_TOP_MAINPLL_D4_D16 84 |
| +#define CLK_TOP_MAINPLL_D5 85 |
| +#define CLK_TOP_MAINPLL_D5_D2 86 |
| +#define CLK_TOP_MAINPLL_D5_D4 87 |
| +#define CLK_TOP_MAINPLL_D5_D8 88 |
| +#define CLK_TOP_MAINPLL_D6 89 |
| +#define CLK_TOP_MAINPLL_D6_D2 90 |
| +#define CLK_TOP_MAINPLL_D6_D4 91 |
| +#define CLK_TOP_MAINPLL_D7 92 |
| +#define CLK_TOP_MAINPLL_D7_D2 93 |
| +#define CLK_TOP_MAINPLL_D7_D4 94 |
| +#define CLK_TOP_MAINPLL_D7_D8 95 |
| +#define CLK_TOP_UNIVPLL_D3 96 |
| +#define CLK_TOP_UNIVPLL_D4 97 |
| +#define CLK_TOP_UNIVPLL_D4_D2 98 |
| +#define CLK_TOP_UNIVPLL_D4_D4 99 |
| +#define CLK_TOP_UNIVPLL_D4_D8 100 |
| +#define CLK_TOP_UNIVPLL_D5 101 |
| +#define CLK_TOP_UNIVPLL_D5_D2 102 |
| +#define CLK_TOP_UNIVPLL_D5_D4 103 |
| +#define CLK_TOP_UNIVPLL_D5_D8 104 |
| +#define CLK_TOP_UNIVPLL_D6 105 |
| +#define CLK_TOP_UNIVPLL_D6_D2 106 |
| +#define CLK_TOP_UNIVPLL_D6_D4 107 |
| +#define CLK_TOP_UNIVPLL_D6_D8 108 |
| +#define CLK_TOP_UNIVPLL_D6_D16 109 |
| +#define CLK_TOP_UNIVPLL_D7 110 |
| +#define CLK_TOP_APLL1 111 |
| +#define CLK_TOP_APLL1_D2 112 |
| +#define CLK_TOP_APLL1_D4 113 |
| +#define CLK_TOP_APLL1_D8 114 |
| +#define CLK_TOP_APLL2 115 |
| +#define CLK_TOP_APLL2_D2 116 |
| +#define CLK_TOP_APLL2_D4 117 |
| +#define CLK_TOP_APLL2_D8 118 |
| +#define CLK_TOP_MMPLL_D4 119 |
| +#define CLK_TOP_MMPLL_D4_D2 120 |
| +#define CLK_TOP_MMPLL_D5 121 |
| +#define CLK_TOP_MMPLL_D5_D2 122 |
| +#define CLK_TOP_MMPLL_D6 123 |
| +#define CLK_TOP_MMPLL_D6_D2 124 |
| +#define CLK_TOP_MMPLL_D7 125 |
| +#define CLK_TOP_MMPLL_D9 126 |
| +#define CLK_TOP_APUPLL 127 |
| +#define CLK_TOP_NPUPLL 128 |
| +#define CLK_TOP_TVDPLL 129 |
| +#define CLK_TOP_TVDPLL_D2 130 |
| +#define CLK_TOP_TVDPLL_D4 131 |
| +#define CLK_TOP_TVDPLL_D8 132 |
| +#define CLK_TOP_TVDPLL_D16 133 |
| +#define CLK_TOP_MSDCPLL 134 |
| +#define CLK_TOP_MSDCPLL_D2 135 |
| +#define CLK_TOP_MSDCPLL_D4 136 |
| +#define CLK_TOP_ULPOSC 137 |
| +#define CLK_TOP_OSC_D2 138 |
| +#define CLK_TOP_OSC_D4 139 |
| +#define CLK_TOP_OSC_D8 140 |
| +#define CLK_TOP_OSC_D10 141 |
| +#define CLK_TOP_OSC_D16 142 |
| +#define CLK_TOP_OSC_D20 143 |
| +#define CLK_TOP_CSW_F26M_D2 144 |
| +#define CLK_TOP_ADSPPLL 145 |
| +#define CLK_TOP_UNIVPLL_192M 146 |
| +#define CLK_TOP_UNIVPLL_192M_D2 147 |
| +#define CLK_TOP_UNIVPLL_192M_D4 148 |
| +#define CLK_TOP_UNIVPLL_192M_D8 149 |
| +#define CLK_TOP_UNIVPLL_192M_D16 150 |
| +#define CLK_TOP_UNIVPLL_192M_D32 151 |
| +#define CLK_TOP_APLL12_DIV0 152 |
| +#define CLK_TOP_APLL12_DIV1 153 |
| +#define CLK_TOP_APLL12_DIV2 154 |
| +#define CLK_TOP_APLL12_DIV3 155 |
| +#define CLK_TOP_APLL12_DIV4 156 |
| +#define CLK_TOP_APLL12_DIVB 157 |
| +#define CLK_TOP_APLL12_DIV5 158 |
| +#define CLK_TOP_APLL12_DIV6 159 |
| +#define CLK_TOP_APLL12_DIV7 160 |
| +#define CLK_TOP_APLL12_DIV8 161 |
| +#define CLK_TOP_APLL12_DIV9 162 |
| +#define CLK_TOP_SSUSB_TOP_REF 163 |
| +#define CLK_TOP_SSUSB_PHY_REF 164 |
| +#define CLK_TOP_NR_CLK 165 |
| + |
| +/* INFRACFG */ |
| + |
| +#define CLK_INFRA_PMIC_TMR 0 |
| +#define CLK_INFRA_PMIC_AP 1 |
| +#define CLK_INFRA_PMIC_MD 2 |
| +#define CLK_INFRA_PMIC_CONN 3 |
| +#define CLK_INFRA_SCPSYS 4 |
| +#define CLK_INFRA_SEJ 5 |
| +#define CLK_INFRA_APXGPT 6 |
| +#define CLK_INFRA_MCUPM 7 |
| +#define CLK_INFRA_GCE 8 |
| +#define CLK_INFRA_GCE2 9 |
| +#define CLK_INFRA_THERM 10 |
| +#define CLK_INFRA_I2C0 11 |
| +#define CLK_INFRA_AP_DMA_PSEUDO 12 |
| +#define CLK_INFRA_I2C2 13 |
| +#define CLK_INFRA_I2C3 14 |
| +#define CLK_INFRA_PWM_H 15 |
| +#define CLK_INFRA_PWM1 16 |
| +#define CLK_INFRA_PWM2 17 |
| +#define CLK_INFRA_PWM3 18 |
| +#define CLK_INFRA_PWM4 19 |
| +#define CLK_INFRA_PWM 20 |
| +#define CLK_INFRA_UART0 21 |
| +#define CLK_INFRA_UART1 22 |
| +#define CLK_INFRA_UART2 23 |
| +#define CLK_INFRA_UART3 24 |
| +#define CLK_INFRA_GCE_26M 25 |
| +#define CLK_INFRA_CQ_DMA_FPC 26 |
| +#define CLK_INFRA_BTIF 27 |
| +#define CLK_INFRA_SPI0 28 |
| +#define CLK_INFRA_MSDC0 29 |
| +#define CLK_INFRA_MSDC1 30 |
| +#define CLK_INFRA_MSDC2 31 |
| +#define CLK_INFRA_MSDC0_SRC 32 |
| +#define CLK_INFRA_GCPU 33 |
| +#define CLK_INFRA_TRNG 34 |
| +#define CLK_INFRA_AUXADC 35 |
| +#define CLK_INFRA_CPUM 36 |
| +#define CLK_INFRA_CCIF1_AP 37 |
| +#define CLK_INFRA_CCIF1_MD 38 |
| +#define CLK_INFRA_AUXADC_MD 39 |
| +#define CLK_INFRA_PCIE_TL_26M 40 |
| +#define CLK_INFRA_MSDC1_SRC 41 |
| +#define CLK_INFRA_MSDC2_SRC 42 |
| +#define CLK_INFRA_PCIE_TL_96M 43 |
| +#define CLK_INFRA_PCIE_PL_P_250M 44 |
| +#define CLK_INFRA_DEVICE_APC 45 |
| +#define CLK_INFRA_CCIF_AP 46 |
| +#define CLK_INFRA_DEBUGSYS 47 |
| +#define CLK_INFRA_AUDIO 48 |
| +#define CLK_INFRA_CCIF_MD 49 |
| +#define CLK_INFRA_DXCC_SEC_CORE 50 |
| +#define CLK_INFRA_DXCC_AO 51 |
| +#define CLK_INFRA_DBG_TRACE 52 |
| +#define CLK_INFRA_DEVMPU_B 53 |
| +#define CLK_INFRA_DRAMC_F26M 54 |
| +#define CLK_INFRA_IRTX 55 |
| +#define CLK_INFRA_SSUSB 56 |
| +#define CLK_INFRA_DISP_PWM 57 |
| +#define CLK_INFRA_CLDMA_B 58 |
| +#define CLK_INFRA_AUDIO_26M_B 59 |
| +#define CLK_INFRA_MODEM_TEMP_SHARE 60 |
| +#define CLK_INFRA_SPI1 61 |
| +#define CLK_INFRA_I2C4 62 |
| +#define CLK_INFRA_SPI2 63 |
| +#define CLK_INFRA_SPI3 64 |
| +#define CLK_INFRA_UNIPRO_SYS 65 |
| +#define CLK_INFRA_UNIPRO_TICK 66 |
| +#define CLK_INFRA_UFS_MP_SAP_B 67 |
| +#define CLK_INFRA_MD32_B 68 |
| +#define CLK_INFRA_SSPM 69 |
| +#define CLK_INFRA_UNIPRO_MBIST 70 |
| +#define CLK_INFRA_SSPM_BUS_H 71 |
| +#define CLK_INFRA_I2C5 72 |
| +#define CLK_INFRA_I2C5_ARBITER 73 |
| +#define CLK_INFRA_I2C5_IMM 74 |
| +#define CLK_INFRA_I2C1_ARBITER 75 |
| +#define CLK_INFRA_I2C1_IMM 76 |
| +#define CLK_INFRA_I2C2_ARBITER 77 |
| +#define CLK_INFRA_I2C2_IMM 78 |
| +#define CLK_INFRA_SPI4 79 |
| +#define CLK_INFRA_SPI5 80 |
| +#define CLK_INFRA_CQ_DMA 81 |
| +#define CLK_INFRA_UFS 82 |
| +#define CLK_INFRA_AES_UFSFDE 83 |
| +#define CLK_INFRA_UFS_TICK 84 |
| +#define CLK_INFRA_SSUSB_XHCI 85 |
| +#define CLK_INFRA_MSDC0_SELF 86 |
| +#define CLK_INFRA_MSDC1_SELF 87 |
| +#define CLK_INFRA_MSDC2_SELF 88 |
| +#define CLK_INFRA_SSPM_26M_SELF 89 |
| +#define CLK_INFRA_SSPM_32K_SELF 90 |
| +#define CLK_INFRA_UFS_AXI 91 |
| +#define CLK_INFRA_I2C6 92 |
| +#define CLK_INFRA_AP_MSDC0 93 |
| +#define CLK_INFRA_MD_MSDC0 94 |
| +#define CLK_INFRA_CCIF5_AP 95 |
| +#define CLK_INFRA_CCIF5_MD 96 |
| +#define CLK_INFRA_PCIE_TOP_H_133M 97 |
| +#define CLK_INFRA_FLASHIF_TOP_H_133M 98 |
| +#define CLK_INFRA_PCIE_PERI_26M 99 |
| +#define CLK_INFRA_CCIF2_AP 100 |
| +#define CLK_INFRA_CCIF2_MD 101 |
| +#define CLK_INFRA_CCIF3_AP 102 |
| +#define CLK_INFRA_CCIF3_MD 103 |
| +#define CLK_INFRA_SEJ_F13M 104 |
| +#define CLK_INFRA_AES 105 |
| +#define CLK_INFRA_I2C7 106 |
| +#define CLK_INFRA_I2C8 107 |
| +#define CLK_INFRA_FBIST2FPC 108 |
| +#define CLK_INFRA_DEVICE_APC_SYNC 109 |
| +#define CLK_INFRA_DPMAIF_MAIN 110 |
| +#define CLK_INFRA_PCIE_TL_32K 111 |
| +#define CLK_INFRA_CCIF4_AP 112 |
| +#define CLK_INFRA_CCIF4_MD 113 |
| +#define CLK_INFRA_SPI6 114 |
| +#define CLK_INFRA_SPI7 115 |
| +#define CLK_INFRA_133M 116 |
| +#define CLK_INFRA_66M 117 |
| +#define CLK_INFRA_66M_PERI_BUS 118 |
| +#define CLK_INFRA_FREE_DCM_133M 119 |
| +#define CLK_INFRA_FREE_DCM_66M 120 |
| +#define CLK_INFRA_PERI_BUS_DCM_133M 121 |
| +#define CLK_INFRA_PERI_BUS_DCM_66M 122 |
| +#define CLK_INFRA_FLASHIF_PERI_26M 123 |
| +#define CLK_INFRA_FLASHIF_SFLASH 124 |
| +#define CLK_INFRA_AP_DMA 125 |
| +#define CLK_INFRA_NR_CLK 126 |
| + |
| +/* PERICFG */ |
| + |
| +#define CLK_PERI_PERIAXI 0 |
| +#define CLK_PERI_NR_CLK 1 |
| + |
| +/* APMIXEDSYS */ |
| + |
| +#define CLK_APMIXED_MAINPLL 0 |
| +#define CLK_APMIXED_UNIVPLL 1 |
| +#define CLK_APMIXED_USBPLL 2 |
| +#define CLK_APMIXED_MSDCPLL 3 |
| +#define CLK_APMIXED_MMPLL 4 |
| +#define CLK_APMIXED_ADSPPLL 5 |
| +#define CLK_APMIXED_MFGPLL 6 |
| +#define CLK_APMIXED_TVDPLL 7 |
| +#define CLK_APMIXED_APLL1 8 |
| +#define CLK_APMIXED_APLL2 9 |
| +#define CLK_APMIXED_APUPLL 10 |
| +#define CLK_APMIXED_NPUPLL 11 |
| +#define CLK_APMIXED_MIPID26M 12 |
| +#define CLK_APMIXED_NR_CLK 13 |
| + |
| +/* SCP_ADSP */ |
| + |
| +#define CLK_SCP_ADSP_AUDIODSP 0 |
| +#define CLK_SCP_ADSP_NR_CLK 1 |
| + |
| +/* IMP_IIC_WRAP_C */ |
| + |
| +#define CLK_IMP_IIC_WRAP_C_I2C10 0 |
| +#define CLK_IMP_IIC_WRAP_C_I2C11 1 |
| +#define CLK_IMP_IIC_WRAP_C_I2C12 2 |
| +#define CLK_IMP_IIC_WRAP_C_I2C13 3 |
| +#define CLK_IMP_IIC_WRAP_C_NR_CLK 4 |
| + |
| +/* AUDSYS */ |
| + |
| +#define CLK_AUD_AFE 0 |
| +#define CLK_AUD_22M 1 |
| +#define CLK_AUD_24M 2 |
| +#define CLK_AUD_APLL2_TUNER 3 |
| +#define CLK_AUD_APLL_TUNER 4 |
| +#define CLK_AUD_TDM 5 |
| +#define CLK_AUD_ADC 6 |
| +#define CLK_AUD_DAC 7 |
| +#define CLK_AUD_DAC_PREDIS 8 |
| +#define CLK_AUD_TML 9 |
| +#define CLK_AUD_NLE 10 |
| +#define CLK_AUD_I2S1_B 11 |
| +#define CLK_AUD_I2S2_B 12 |
| +#define CLK_AUD_I2S3_B 13 |
| +#define CLK_AUD_I2S4_B 14 |
| +#define CLK_AUD_CONNSYS_I2S_ASRC 15 |
| +#define CLK_AUD_GENERAL1_ASRC 16 |
| +#define CLK_AUD_GENERAL2_ASRC 17 |
| +#define CLK_AUD_DAC_HIRES 18 |
| +#define CLK_AUD_ADC_HIRES 19 |
| +#define CLK_AUD_ADC_HIRES_TML 20 |
| +#define CLK_AUD_ADDA6_ADC 21 |
| +#define CLK_AUD_ADDA6_ADC_HIRES 22 |
| +#define CLK_AUD_3RD_DAC 23 |
| +#define CLK_AUD_3RD_DAC_PREDIS 24 |
| +#define CLK_AUD_3RD_DAC_TML 25 |
| +#define CLK_AUD_3RD_DAC_HIRES 26 |
| +#define CLK_AUD_I2S5_B 27 |
| +#define CLK_AUD_I2S6_B 28 |
| +#define CLK_AUD_I2S7_B 29 |
| +#define CLK_AUD_I2S8_B 30 |
| +#define CLK_AUD_I2S9_B 31 |
| +#define CLK_AUD_NR_CLK 32 |
| + |
| +/* IMP_IIC_WRAP_E */ |
| + |
| +#define CLK_IMP_IIC_WRAP_E_I2C3 0 |
| +#define CLK_IMP_IIC_WRAP_E_NR_CLK 1 |
| + |
| +/* IMP_IIC_WRAP_S */ |
| + |
| +#define CLK_IMP_IIC_WRAP_S_I2C7 0 |
| +#define CLK_IMP_IIC_WRAP_S_I2C8 1 |
| +#define CLK_IMP_IIC_WRAP_S_I2C9 2 |
| +#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 |
| + |
| +/* IMP_IIC_WRAP_WS */ |
| + |
| +#define CLK_IMP_IIC_WRAP_WS_I2C1 0 |
| +#define CLK_IMP_IIC_WRAP_WS_I2C2 1 |
| +#define CLK_IMP_IIC_WRAP_WS_I2C4 2 |
| +#define CLK_IMP_IIC_WRAP_WS_NR_CLK 3 |
| + |
| +/* IMP_IIC_WRAP_W */ |
| + |
| +#define CLK_IMP_IIC_WRAP_W_I2C5 0 |
| +#define CLK_IMP_IIC_WRAP_W_NR_CLK 1 |
| + |
| +/* IMP_IIC_WRAP_N */ |
| + |
| +#define CLK_IMP_IIC_WRAP_N_I2C0 0 |
| +#define CLK_IMP_IIC_WRAP_N_I2C6 1 |
| +#define CLK_IMP_IIC_WRAP_N_NR_CLK 2 |
| + |
| +/* MSDC_TOP */ |
| + |
| +#define CLK_MSDC_TOP_AES_0P 0 |
| +#define CLK_MSDC_TOP_SRC_0P 1 |
| +#define CLK_MSDC_TOP_SRC_1P 2 |
| +#define CLK_MSDC_TOP_SRC_2P 3 |
| +#define CLK_MSDC_TOP_P_MSDC0 4 |
| +#define CLK_MSDC_TOP_P_MSDC1 5 |
| +#define CLK_MSDC_TOP_P_MSDC2 6 |
| +#define CLK_MSDC_TOP_P_CFG 7 |
| +#define CLK_MSDC_TOP_AXI 8 |
| +#define CLK_MSDC_TOP_H_MST_0P 9 |
| +#define CLK_MSDC_TOP_H_MST_1P 10 |
| +#define CLK_MSDC_TOP_H_MST_2P 11 |
| +#define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12 |
| +#define CLK_MSDC_TOP_32K 13 |
| +#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14 |
| +#define CLK_MSDC_TOP_NR_CLK 15 |
| + |
| +/* MSDC */ |
| + |
| +#define CLK_MSDC_AXI_WRAP 0 |
| +#define CLK_MSDC_NR_CLK 1 |
| + |
| +/* MFGCFG */ |
| + |
| +#define CLK_MFG_BG3D 0 |
| +#define CLK_MFG_NR_CLK 1 |
| + |
| +/* MMSYS */ |
| + |
| +#define CLK_MM_DISP_MUTEX0 0 |
| +#define CLK_MM_DISP_CONFIG 1 |
| +#define CLK_MM_DISP_OVL0 2 |
| +#define CLK_MM_DISP_RDMA0 3 |
| +#define CLK_MM_DISP_OVL0_2L 4 |
| +#define CLK_MM_DISP_WDMA0 5 |
| +#define CLK_MM_DISP_UFBC_WDMA0 6 |
| +#define CLK_MM_DISP_RSZ0 7 |
| +#define CLK_MM_DISP_AAL0 8 |
| +#define CLK_MM_DISP_CCORR0 9 |
| +#define CLK_MM_DISP_DITHER0 10 |
| +#define CLK_MM_SMI_INFRA 11 |
| +#define CLK_MM_DISP_GAMMA0 12 |
| +#define CLK_MM_DISP_POSTMASK0 13 |
| +#define CLK_MM_DISP_DSC_WRAP0 14 |
| +#define CLK_MM_DSI0 15 |
| +#define CLK_MM_DISP_COLOR0 16 |
| +#define CLK_MM_SMI_COMMON 17 |
| +#define CLK_MM_DISP_FAKE_ENG0 18 |
| +#define CLK_MM_DISP_FAKE_ENG1 19 |
| +#define CLK_MM_MDP_TDSHP4 20 |
| +#define CLK_MM_MDP_RSZ4 21 |
| +#define CLK_MM_MDP_AAL4 22 |
| +#define CLK_MM_MDP_HDR4 23 |
| +#define CLK_MM_MDP_RDMA4 24 |
| +#define CLK_MM_MDP_COLOR4 25 |
| +#define CLK_MM_DISP_Y2R0 26 |
| +#define CLK_MM_SMI_GALS 27 |
| +#define CLK_MM_DISP_OVL2_2L 28 |
| +#define CLK_MM_DISP_RDMA4 29 |
| +#define CLK_MM_DISP_DPI0 30 |
| +#define CLK_MM_SMI_IOMMU 31 |
| +#define CLK_MM_DSI_DSI0 32 |
| +#define CLK_MM_DPI_DPI0 33 |
| +#define CLK_MM_26MHZ 34 |
| +#define CLK_MM_32KHZ 35 |
| +#define CLK_MM_NR_CLK 36 |
| + |
| +/* IMGSYS */ |
| + |
| +#define CLK_IMG_LARB9 0 |
| +#define CLK_IMG_LARB10 1 |
| +#define CLK_IMG_DIP 2 |
| +#define CLK_IMG_GALS 3 |
| +#define CLK_IMG_NR_CLK 4 |
| + |
| +/* IMGSYS2 */ |
| + |
| +#define CLK_IMG2_LARB11 0 |
| +#define CLK_IMG2_LARB12 1 |
| +#define CLK_IMG2_MFB 2 |
| +#define CLK_IMG2_WPE 3 |
| +#define CLK_IMG2_MSS 4 |
| +#define CLK_IMG2_GALS 5 |
| +#define CLK_IMG2_NR_CLK 6 |
| + |
| +/* VDECSYS_SOC */ |
| + |
| +#define CLK_VDEC_SOC_LARB1 0 |
| +#define CLK_VDEC_SOC_LAT 1 |
| +#define CLK_VDEC_SOC_LAT_ACTIVE 2 |
| +#define CLK_VDEC_SOC_VDEC 3 |
| +#define CLK_VDEC_SOC_VDEC_ACTIVE 4 |
| +#define CLK_VDEC_SOC_NR_CLK 5 |
| + |
| +/* VDECSYS */ |
| + |
| +#define CLK_VDEC_LARB1 0 |
| +#define CLK_VDEC_LAT 1 |
| +#define CLK_VDEC_LAT_ACTIVE 2 |
| +#define CLK_VDEC_VDEC 3 |
| +#define CLK_VDEC_ACTIVE 4 |
| +#define CLK_VDEC_NR_CLK 5 |
| + |
| +/* VENCSYS */ |
| + |
| +#define CLK_VENC_SET0_LARB 0 |
| +#define CLK_VENC_SET1_VENC 1 |
| +#define CLK_VENC_SET2_JPGENC 2 |
| +#define CLK_VENC_SET5_GALS 3 |
| +#define CLK_VENC_NR_CLK 4 |
| + |
| +/* APU_CONN */ |
| + |
| +#define CLK_APU_CONN_APU 0 |
| +#define CLK_APU_CONN_AHB 1 |
| +#define CLK_APU_CONN_AXI 2 |
| +#define CLK_APU_CONN_ISP 3 |
| +#define CLK_APU_CONN_CAM_ADL 4 |
| +#define CLK_APU_CONN_IMG_ADL 5 |
| +#define CLK_APU_CONN_EMI_26M 6 |
| +#define CLK_APU_CONN_VPU_UDI 7 |
| +#define CLK_APU_CONN_EDMA_0 8 |
| +#define CLK_APU_CONN_EDMA_1 9 |
| +#define CLK_APU_CONN_EDMAL_0 10 |
| +#define CLK_APU_CONN_EDMAL_1 11 |
| +#define CLK_APU_CONN_MNOC 12 |
| +#define CLK_APU_CONN_TCM 13 |
| +#define CLK_APU_CONN_MD32 14 |
| +#define CLK_APU_CONN_IOMMU_0 15 |
| +#define CLK_APU_CONN_IOMMU_1 16 |
| +#define CLK_APU_CONN_MD32_32K 17 |
| +#define CLK_APU_CONN_NR_CLK 18 |
| + |
| +/* APU_VCORE */ |
| + |
| +#define CLK_APU_VCORE_AHB 0 |
| +#define CLK_APU_VCORE_AXI 1 |
| +#define CLK_APU_VCORE_ADL 2 |
| +#define CLK_APU_VCORE_QOS 3 |
| +#define CLK_APU_VCORE_NR_CLK 4 |
| + |
| +/* APU0 */ |
| + |
| +#define CLK_APU0_APU 0 |
| +#define CLK_APU0_AXI_M 1 |
| +#define CLK_APU0_JTAG 2 |
| +#define CLK_APU0_NR_CLK 3 |
| + |
| +/* APU1 */ |
| + |
| +#define CLK_APU1_APU 0 |
| +#define CLK_APU1_AXI_M 1 |
| +#define CLK_APU1_JTAG 2 |
| +#define CLK_APU1_NR_CLK 3 |
| + |
| +/* APU_MDLA0 */ |
| + |
| +#define CLK_APU_MDLA0_CG0 0 |
| +#define CLK_APU_MDLA0_CG1 1 |
| +#define CLK_APU_MDLA0_CG2 2 |
| +#define CLK_APU_MDLA0_CG3 3 |
| +#define CLK_APU_MDLA0_CG4 4 |
| +#define CLK_APU_MDLA0_CG5 5 |
| +#define CLK_APU_MDLA0_CG6 6 |
| +#define CLK_APU_MDLA0_CG7 7 |
| +#define CLK_APU_MDLA0_CG8 8 |
| +#define CLK_APU_MDLA0_CG9 9 |
| +#define CLK_APU_MDLA0_CG10 10 |
| +#define CLK_APU_MDLA0_CG11 11 |
| +#define CLK_APU_MDLA0_CG12 12 |
| +#define CLK_APU_MDLA0_APB 13 |
| +#define CLK_APU_MDLA0_AXI_M 14 |
| +#define CLK_APU_MDLA0_NR_CLK 15 |
| + |
| +/* CAMSYS */ |
| + |
| +#define CLK_CAM_LARB13 0 |
| +#define CLK_CAM_DFP_VAD 1 |
| +#define CLK_CAM_LARB14 2 |
| +#define CLK_CAM_CAM 3 |
| +#define CLK_CAM_CAMTG 4 |
| +#define CLK_CAM_SENINF 5 |
| +#define CLK_CAM_CAMSV0 6 |
| +#define CLK_CAM_CAMSV1 7 |
| +#define CLK_CAM_CAMSV2 8 |
| +#define CLK_CAM_CAMSV3 9 |
| +#define CLK_CAM_CCU0 10 |
| +#define CLK_CAM_CCU1 11 |
| +#define CLK_CAM_MRAW0 12 |
| +#define CLK_CAM_FAKE_ENG 13 |
| +#define CLK_CAM_CCU_GALS 14 |
| +#define CLK_CAM_CAM2MM_GALS 15 |
| +#define CLK_CAM_NR_CLK 16 |
| + |
| +/* CAMSYS_RAWA */ |
| + |
| +#define CLK_CAM_RAWA_LARBX 0 |
| +#define CLK_CAM_RAWA_CAM 1 |
| +#define CLK_CAM_RAWA_CAMTG 2 |
| +#define CLK_CAM_RAWA_NR_CLK 3 |
| + |
| +/* CAMSYS_RAWB */ |
| + |
| +#define CLK_CAM_RAWB_LARBX 0 |
| +#define CLK_CAM_RAWB_CAM 1 |
| +#define CLK_CAM_RAWB_CAMTG 2 |
| +#define CLK_CAM_RAWB_NR_CLK 3 |
| + |
| +/* CAMSYS_RAWC */ |
| + |
| +#define CLK_CAM_RAWC_LARBX 0 |
| +#define CLK_CAM_RAWC_CAM 1 |
| +#define CLK_CAM_RAWC_CAMTG 2 |
| +#define CLK_CAM_RAWC_NR_CLK 3 |
| + |
| +/* IPESYS */ |
| + |
| +#define CLK_IPE_LARB19 0 |
| +#define CLK_IPE_LARB20 1 |
| +#define CLK_IPE_SMI_SUBCOM 2 |
| +#define CLK_IPE_FD 3 |
| +#define CLK_IPE_FE 4 |
| +#define CLK_IPE_RSC 5 |
| +#define CLK_IPE_DPE 6 |
| +#define CLK_IPE_GALS 7 |
| +#define CLK_IPE_NR_CLK 8 |
| + |
| +/* MDPSYS */ |
| + |
| +#define CLK_MDP_RDMA0 0 |
| +#define CLK_MDP_TDSHP0 1 |
| +#define CLK_MDP_IMG_DL_ASYNC0 2 |
| +#define CLK_MDP_IMG_DL_ASYNC1 3 |
| +#define CLK_MDP_RDMA1 4 |
| +#define CLK_MDP_TDSHP1 5 |
| +#define CLK_MDP_SMI0 6 |
| +#define CLK_MDP_APB_BUS 7 |
| +#define CLK_MDP_WROT0 8 |
| +#define CLK_MDP_RSZ0 9 |
| +#define CLK_MDP_HDR0 10 |
| +#define CLK_MDP_MUTEX0 11 |
| +#define CLK_MDP_WROT1 12 |
| +#define CLK_MDP_RSZ1 13 |
| +#define CLK_MDP_HDR1 14 |
| +#define CLK_MDP_FAKE_ENG0 15 |
| +#define CLK_MDP_AAL0 16 |
| +#define CLK_MDP_AAL1 17 |
| +#define CLK_MDP_COLOR0 18 |
| +#define CLK_MDP_COLOR1 19 |
| +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20 |
| +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21 |
| +#define CLK_MDP_NR_CLK 22 |
| + |
| +#endif /* _DT_BINDINGS_CLK_MT8192_H */ |
| + |
| diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h |
| index 6f9aa7349cef340c5a0a341ee5e65de5ed65cf58..b6b2c6bf4459e1779f8289fdc65ad72c5cff7a65 100644 |
| --- a/include/dt-bindings/memory/mt2712-larb-port.h |
| +++ b/include/dt-bindings/memory/mt2712-larb-port.h |
| @@ -6,7 +6,7 @@ |
| #ifndef __DTS_IOMMU_PORT_MT2712_H |
| #define __DTS_IOMMU_PORT_MT2712_H |
| |
| -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| |
| #define M4U_LARB0_ID 0 |
| #define M4U_LARB1_ID 1 |
| diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..4fd1620623736cc3e9e293bb1142a001c15e51bb |
| --- /dev/null |
| +++ b/include/dt-bindings/memory/mt6779-larb-port.h |
| @@ -0,0 +1,215 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2019 MediaTek Inc. |
| + * Author: Chao Hao <chao.hao@mediatek.com> |
| + */ |
| + |
| +#ifndef _DTS_IOMMU_PORT_MT6779_H_ |
| +#define _DTS_IOMMU_PORT_MT6779_H_ |
| + |
| +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) |
| + |
| +#define M4U_LARB0_ID 0 |
| +#define M4U_LARB1_ID 1 |
| +#define M4U_LARB2_ID 2 |
| +#define M4U_LARB3_ID 3 |
| +#define M4U_LARB4_ID 4 |
| +#define M4U_LARB5_ID 5 |
| +#define M4U_LARB6_ID 6 |
| +#define M4U_LARB7_ID 7 |
| +#define M4U_LARB8_ID 8 |
| +#define M4U_LARB9_ID 9 |
| +#define M4U_LARB10_ID 10 |
| +#define M4U_LARB11_ID 11 |
| +#define M4U_LARB12_ID 12 |
| +#define M4U_LARB13_ID 13 |
| + |
| +/* larb0 */ |
| +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) |
| +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) |
| +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) |
| +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) |
| +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) |
| +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) |
| +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) |
| +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) |
| +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) |
| + |
| +/* larb1 */ |
| +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) |
| +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) |
| +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) |
| +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) |
| +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) |
| +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) |
| +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) |
| +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) |
| +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) |
| +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) |
| +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) |
| +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) |
| +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) |
| +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) |
| + |
| +/* larb2-VDEC */ |
| +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) |
| +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) |
| +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) |
| +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) |
| +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) |
| +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) |
| +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) |
| +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) |
| +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) |
| +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) |
| +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) |
| +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) |
| + |
| +/* larb3-VENC */ |
| +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) |
| +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) |
| +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) |
| +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) |
| +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) |
| +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) |
| +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) |
| +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) |
| +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) |
| +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) |
| +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) |
| +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) |
| +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) |
| +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) |
| +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) |
| +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) |
| +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) |
| +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) |
| +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) |
| + |
| +/* larb4-dummy */ |
| + |
| +/* larb5-IMG */ |
| +#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) |
| +#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) |
| +#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) |
| +#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) |
| +#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) |
| +#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) |
| +#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) |
| +#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) |
| +#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) |
| +#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) |
| +#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) |
| +#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) |
| +#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) |
| +#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) |
| +#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) |
| +#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) |
| +#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) |
| +#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) |
| +#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) |
| +#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) |
| +#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) |
| +#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) |
| +#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) |
| +#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) |
| +#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) |
| +#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) |
| + |
| +/* larb6-IMG-VPU */ |
| +#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) |
| +#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) |
| +#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) |
| + |
| +/* larb7-DVS */ |
| +#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) |
| +#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) |
| +#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) |
| +#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) |
| + |
| +/* larb8-IPESYS */ |
| +#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) |
| +#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) |
| +#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) |
| +#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) |
| +#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) |
| +#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) |
| +#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) |
| +#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) |
| +#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) |
| +#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) |
| + |
| +/* larb9-CAM */ |
| +#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) |
| +#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) |
| +#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) |
| +#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) |
| +#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) |
| +#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) |
| +#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) |
| +#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) |
| +#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) |
| +#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) |
| +#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) |
| +#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) |
| +#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) |
| +#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) |
| +#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) |
| +#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) |
| +#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) |
| +#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) |
| +#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) |
| +#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) |
| +#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) |
| +#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) |
| +#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) |
| +#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) |
| + |
| +/* larb10-CAM_A */ |
| +#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) |
| +#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) |
| +#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) |
| +#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) |
| +#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) |
| +#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) |
| +#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) |
| +#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) |
| +#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) |
| +#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) |
| +#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) |
| +#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) |
| +#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) |
| +#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) |
| +#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) |
| +#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) |
| +#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) |
| +#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) |
| +#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) |
| +#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) |
| +#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) |
| +#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) |
| +#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) |
| +#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) |
| +#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) |
| +#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) |
| +#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) |
| +#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) |
| +#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) |
| +#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) |
| +#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) |
| + |
| +/* larb11-CAM-VPU */ |
| +#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) |
| +#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) |
| +#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) |
| +#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) |
| +#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) |
| + |
| +#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB12_ID, 0) |
| +#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB12_ID, 1) |
| + |
| +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) |
| +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) |
| +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) |
| + |
| +#endif |
| diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h |
| index 9f31ccfeca2153e5957c589d237c5a126b7a82b8..d8c99c946053645b59552772a8eb0239b4fc0a1e 100644 |
| --- a/include/dt-bindings/memory/mt8173-larb-port.h |
| +++ b/include/dt-bindings/memory/mt8173-larb-port.h |
| @@ -6,7 +6,7 @@ |
| #ifndef __DTS_IOMMU_PORT_MT8173_H |
| #define __DTS_IOMMU_PORT_MT8173_H |
| |
| -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| |
| #define M4U_LARB0_ID 0 |
| #define M4U_LARB1_ID 1 |
| diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h |
| index 2c579f3051625bfd09b797e25b7a25286c3f3efc..275c095a6fd6055f823c18051e1297b384f9ff18 100644 |
| --- a/include/dt-bindings/memory/mt8183-larb-port.h |
| +++ b/include/dt-bindings/memory/mt8183-larb-port.h |
| @@ -6,7 +6,7 @@ |
| #ifndef __DTS_IOMMU_PORT_MT8183_H |
| #define __DTS_IOMMU_PORT_MT8183_H |
| |
| -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| |
| #define M4U_LARB0_ID 0 |
| #define M4U_LARB1_ID 1 |
| diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..c1fb83f90908cba9c1601e3d6265ad310b097eac |
| --- /dev/null |
| +++ b/include/dt-bindings/memory/mt8192-larb-port.h |
| @@ -0,0 +1,292 @@ |
| +/* SPDX-License-Identifier: GPL-2.0-only */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + * Author: Chao Hao <chao.hao@mediatek.com> |
| + * Author: Yong Wu <yong.wu@mediatek.com> |
| + */ |
| +#ifndef _DTS_IOMMU_PORT_MT8192_H_ |
| +#define _DTS_IOMMU_PORT_MT8192_H_ |
| + |
| +#include <dt-bindings/memory/mtk-smi-larb-port.h> |
| + |
| +/* |
| + * MM IOMMU: |
| + * domain 0: display: larb0, larb2. |
| + * domain 1: video: larb4, larb5, larb7, larb8. |
| + * domain 2: CAM and MDP: larb9, larb11, larb13, larb14, larb16, larb17, |
| + * larb18, larb19, larb20, |
| + * domain 3: CCU0: larb13, port9 & larb10. |
| + * domain 4: CCU1: larb14, port4 & larb5. |
| + * VPU IOMMU: |
| + * domain 0: APU CODE: larb21, port0. |
| + * domain 1: APU DATA: larb21, port1. |
| + * domain 2: APU VLM: larb21, port2. |
| + */ |
| + |
| +/* larb0 */ |
| +#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_DOM_ID(0, 0, 0) |
| +#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_DOM_ID(0, 0, 1) |
| +#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_DOM_ID(0, 0, 2) |
| +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_DOM_ID(0, 0, 3) |
| +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 0, 4) |
| +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_DOM_ID(0, 0, 5) |
| + |
| +/* larb1 */ |
| +#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(0, 1, 0) |
| +#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_DOM_ID(0, 1, 1) |
| +#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_DOM_ID(0, 1, 2) |
| +#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(0, 1, 3) |
| +#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_DOM_ID(0, 1, 4) |
| +#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_DOM_ID(0, 1, 5) |
| +#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 1, 6) |
| +#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_DOM_ID(0, 1, 7) |
| + |
| +/* larb2 */ |
| +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_DOM_ID(2, 2, 0) |
| +#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_DOM_ID(2, 2, 1) |
| +#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_DOM_ID(2, 2, 2) |
| +#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_DOM_ID(2, 2, 3) |
| +#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_DOM_ID(2, 2, 4) |
| + |
| +/* larb3: null */ |
| + |
| +/* larb4 */ |
| +#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_DOM_ID(1, 4, 0) |
| +#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_DOM_ID(1, 4, 1) |
| +#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_DOM_ID(1, 4, 2) |
| +#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_DOM_ID(1, 4, 3) |
| +#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_DOM_ID(1, 4, 4) |
| +#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_DOM_ID(1, 4, 5) |
| +#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_DOM_ID(1, 4, 6) |
| +#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_DOM_ID(1, 4, 7) |
| +#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_DOM_ID(1, 4, 8) |
| +#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_DOM_ID(1, 4, 9) |
| +#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 4, 10) |
| + |
| +/* larb5 */ |
| +#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_DOM_ID(1, 5, 0) |
| +#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_DOM_ID(1, 5, 1) |
| +#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_DOM_ID(1, 5, 2) |
| +#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_DOM_ID(1, 5, 3) |
| +#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_DOM_ID(1, 5, 4) |
| +#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_DOM_ID(1, 5, 5) |
| +#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 5, 6) |
| +#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_DOM_ID(1, 5, 7) |
| + |
| +/* larb6: null */ |
| + |
| +/* larb7 */ |
| +#define M4U_PORT_L7_VENC_RCPU MTK_M4U_DOM_ID(1, 7, 0) |
| +#define M4U_PORT_L7_VENC_REC MTK_M4U_DOM_ID(1, 7, 1) |
| +#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_DOM_ID(1, 7, 2) |
| +#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_DOM_ID(1, 7, 3) |
| +#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_DOM_ID(1, 7, 4) |
| +#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_DOM_ID(1, 7, 5) |
| +#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_DOM_ID(1, 7, 6) |
| +#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_DOM_ID(1, 7, 7) |
| +#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_DOM_ID(1, 7, 8) |
| +#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_DOM_ID(1, 7, 9) |
| +#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_DOM_ID(1, 7, 10) |
| +#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_DOM_ID(1, 7, 11) |
| +#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_DOM_ID(1, 7, 12) |
| +#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_DOM_ID(1, 7, 13) |
| +#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_DOM_ID(1, 7, 14) |
| + |
| +/* larb8 */ |
| +#define M4U_PORT_L8_VENC_RCPU MTK_M4U_DOM_ID(1, 8, 0) |
| +#define M4U_PORT_L8_VENC_RECP MTK_M4U_DOM_ID(1, 8, 1) |
| +#define M4U_PORT_L8_VENC_BSDMA MTK_M4U_DOM_ID(1, 8, 2) |
| +#define M4U_PORT_L8_VENC_SUB_W_LUMA MTK_M4U_DOM_ID(1, 8, 3) |
| +#define M4U_PORT_L8_VENC_SV_COMV MTK_M4U_DOM_ID(1, 8, 4) |
| +#define M4U_PORT_L8_VENC_RD_COMV MTK_M4U_DOM_ID(1, 8, 5) |
| +#define M4U_PORT_L8_VENC_NBM_RDMA MTK_M4U_DOM_ID(1, 8, 6) |
| +#define M4U_PORT_L8_VENC_NBM_RDMA_LITE MTK_M4U_DOM_ID(1, 8, 7) |
| +#define M4U_PORT_L8_VENC_FCS_NBM_RDMA MTK_M4U_DOM_ID(1, 8, 8) |
| +#define M4U_PORT_L8_JPGENC_Y_RDMA MTK_M4U_DOM_ID(1, 8, 9) |
| +#define M4U_PORT_L8_JPGENC_C_RDMA MTK_M4U_DOM_ID(1, 8, 10) |
| +#define M4U_PORT_L8_JPGENC_Q_TABLE MTK_M4U_DOM_ID(1, 8, 11) |
| +#define M4U_PORT_L8_JPGENC_BSDMA MTK_M4U_DOM_ID(1, 8, 12) |
| +#define M4U_PORT_L8_JPGENC_HUFF_OFFSET0 MTK_M4U_DOM_ID(1, 8, 13) |
| +#define M4U_PORT_L8_JPGENC_WDMA0 MTK_M4U_DOM_ID(1, 8, 14) |
| +#define M4U_PORT_L8_JPGENC_BSDMA0 MTK_M4U_DOM_ID(1, 8, 15) |
| +#define M4U_PORT_L8_JPGENC_HUFF_OFFSET1 MTK_M4U_DOM_ID(1, 8, 16) |
| +#define M4U_PORT_L8_JPGENC_WDMA1 MTK_M4U_DOM_ID(1, 8, 17) |
| +#define M4U_PORT_L8_JPGENC_BSDMA1 MTK_M4U_DOM_ID(1, 8, 18) |
| +#define M4U_PORT_L8_VENC_NBM_WDMA MTK_M4U_DOM_ID(1, 8, 19) |
| +#define M4U_PORT_L8_VENC_NBM_WDMA_LITE MTK_M4U_DOM_ID(1, 8, 20) |
| +#define M4U_PORT_L8_VENC_FCS_NBM_WDMA MTK_M4U_DOM_ID(1, 8, 21) |
| +#define M4U_PORT_L8_VENC_SUB_R_LUMA MTK_M4U_DOM_ID(1, 8, 22) |
| +#define M4U_PORT_L8_VENC_CUR_LUMA MTK_M4U_DOM_ID(1, 8, 23) |
| +#define M4U_PORT_L8_VENC_CUR_CHROMA MTK_M4U_DOM_ID(1, 8, 24) |
| +#define M4U_PORT_L8_VENC_REF_LUMA MTK_M4U_DOM_ID(1, 8, 25) |
| +#define M4U_PORT_L8_VENC_REF_CHROMA MTK_M4U_DOM_ID(1, 8, 26) |
| + |
| +/* larb9 */ |
| +/* port0~port14 is used, port15~port28 is not used */ |
| +#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 9, 0) |
| +#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 9, 1) |
| +#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 9, 2) |
| +#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 9, 3) |
| +#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 9, 4) |
| +#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 9, 5) |
| +#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 9, 6) |
| +#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 9, 7) |
| +#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 9, 8) |
| +#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 9, 9) |
| +#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 9, 10) |
| +#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 9, 11) |
| +#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 9, 12) |
| +#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 9, 13) |
| +#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 9, 14) |
| +#define M4U_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_DOM_ID(2, 9, 15) |
| +#define M4U_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_DOM_ID(2, 9, 16) |
| +#define M4U_PORT_L9_IMG_WPE_WDMA MTK_M4U_DOM_ID(2, 9, 17) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_DOM_ID(2, 9, 18) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_DOM_ID(2, 9, 19) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_DOM_ID(2, 9, 20) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_DOM_ID(2, 9, 21) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_DOM_ID(2, 9, 22) |
| +#define M4U_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_DOM_ID(2, 9, 23) |
| +#define M4U_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_DOM_ID(2, 9, 24) |
| +#define M4U_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_DOM_ID(2, 9, 25) |
| +#define M4U_PORT_L9_IMG_RESERVE6 MTK_M4U_DOM_ID(2, 9, 26) |
| +#define M4U_PORT_L9_IMG_RESERVE7 MTK_M4U_DOM_ID(2, 9, 27) |
| +#define M4U_PORT_L9_IMG_RESERVE8 MTK_M4U_DOM_ID(2, 9, 28) |
| + |
| +/* larb10: apu null */ |
| + |
| +/* larb11 */ |
| +/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */ |
| +#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 11, 0) |
| +#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 11, 1) |
| +#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 11, 2) |
| +#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 11, 3) |
| +#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 11, 4) |
| +#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 11, 5) |
| +#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 11, 6) |
| +#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 11, 7) |
| +#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 11, 8) |
| +#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 11, 9) |
| +#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 11, 10) |
| +#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 11, 11) |
| +#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 11, 12) |
| +#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 11, 13) |
| +#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 11, 14) |
| +#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_DOM_ID(2, 11, 15) |
| +#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_DOM_ID(2, 11, 16) |
| +#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_DOM_ID(2, 11, 17) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_DOM_ID(2, 11, 18) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_DOM_ID(2, 11, 19) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_DOM_ID(2, 11, 20) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_DOM_ID(2, 11, 21) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_DOM_ID(2, 11, 22) |
| +#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_DOM_ID(2, 11, 23) |
| +#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_DOM_ID(2, 11, 24) |
| +#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_DOM_ID(2, 11, 25) |
| +#define M4U_PORT_L11_IMG_RESERVE6 MTK_M4U_DOM_ID(2, 11, 26) |
| +#define M4U_PORT_L11_IMG_RESERVE7 MTK_M4U_DOM_ID(2, 11, 27) |
| +#define M4U_PORT_L11_IMG_RESERVE8 MTK_M4U_DOM_ID(2, 11, 28) |
| + |
| +/* larb12: apu null */ |
| + |
| +/* larb13 */ |
| +#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_DOM_ID(2, 13, 0) |
| +#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_DOM_ID(2, 13, 1) |
| +#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_DOM_ID(2, 13, 2) |
| +#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_DOM_ID(2, 13, 3) |
| +#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_DOM_ID(2, 13, 4) |
| +#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_DOM_ID(2, 13, 5) |
| +#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_DOM_ID(2, 13, 6) |
| +#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_DOM_ID(2, 13, 7) |
| +#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_DOM_ID(2, 13, 8) |
| +#define M4U_PORT_L13_CAM_CCUI MTK_M4U_DOM_ID(3, 13, 9) |
| +#define M4U_PORT_L13_CAM_CCUO MTK_M4U_DOM_ID(3, 13, 10) |
| +#define M4U_PORT_L13_CAM_FAKE MTK_M4U_DOM_ID(2, 13, 11) |
| + |
| +/* larb14 */ |
| +#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_DOM_ID(2, 14, 0) |
| +#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_DOM_ID(2, 14, 1) |
| +#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_DOM_ID(2, 14, 2) |
| +#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_DOM_ID(2, 14, 3) |
| +#define M4U_PORT_L14_CAM_CCUI MTK_M4U_DOM_ID(4, 14, 4) |
| +#define M4U_PORT_L14_CAM_CCUO MTK_M4U_DOM_ID(4, 14, 5) |
| + |
| +/* larb15: apu null */ |
| + |
| +/* larb16 */ |
| +#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_DOM_ID(2, 16, 0) |
| +#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_DOM_ID(2, 16, 1) |
| +#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_DOM_ID(2, 16, 2) |
| +#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_DOM_ID(2, 16, 3) |
| +#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_DOM_ID(2, 16, 4) |
| +#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_DOM_ID(2, 16, 5) |
| +#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_DOM_ID(2, 16, 6) |
| +#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_DOM_ID(2, 16, 7) |
| +#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_DOM_ID(2, 16, 8) |
| +#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_DOM_ID(2, 16, 9) |
| +#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_DOM_ID(2, 16, 10) |
| +#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_DOM_ID(2, 16, 11) |
| +#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_DOM_ID(2, 16, 12) |
| +#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_DOM_ID(2, 16, 13) |
| +#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_DOM_ID(2, 16, 14) |
| +#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_DOM_ID(2, 16, 15) |
| +#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_DOM_ID(2, 16, 16) |
| + |
| +/* larb17 */ |
| +#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_DOM_ID(2, 17, 0) |
| +#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_DOM_ID(2, 17, 1) |
| +#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_DOM_ID(2, 17, 2) |
| +#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_DOM_ID(2, 17, 3) |
| +#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_DOM_ID(2, 17, 4) |
| +#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_DOM_ID(2, 17, 5) |
| +#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_DOM_ID(2, 17, 6) |
| +#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_DOM_ID(2, 17, 7) |
| +#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_DOM_ID(2, 17, 8) |
| +#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_DOM_ID(2, 17, 9) |
| +#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_DOM_ID(2, 17, 10) |
| +#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_DOM_ID(2, 17, 11) |
| +#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_DOM_ID(2, 17, 12) |
| +#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_DOM_ID(2, 17, 13) |
| +#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_DOM_ID(2, 17, 14) |
| +#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_DOM_ID(2, 17, 15) |
| +#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_DOM_ID(2, 17, 16) |
| + |
| +/* larb18 */ |
| +#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_DOM_ID(2, 18, 0) |
| +#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_DOM_ID(2, 18, 1) |
| +#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_DOM_ID(2, 18, 2) |
| +#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_DOM_ID(2, 18, 3) |
| +#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_DOM_ID(2, 18, 4) |
| +#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_DOM_ID(2, 18, 5) |
| +#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_DOM_ID(2, 18, 6) |
| +#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_DOM_ID(2, 18, 7) |
| +#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_DOM_ID(2, 18, 8) |
| +#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_DOM_ID(2, 18, 9) |
| +#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_DOM_ID(2, 18, 10) |
| +#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_DOM_ID(2, 18, 11) |
| +#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_DOM_ID(2, 18, 12) |
| +#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_DOM_ID(2, 18, 13) |
| +#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_DOM_ID(2, 18, 14) |
| +#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_DOM_ID(2, 18, 15) |
| +#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_DOM_ID(2, 18, 16) |
| + |
| +/* larb19 */ |
| +#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_DOM_ID(2, 19, 0) |
| +#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_DOM_ID(2, 19, 1) |
| +#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_DOM_ID(2, 19, 2) |
| +#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_DOM_ID(2, 19, 3) |
| + |
| +/* larb20 */ |
| +#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_DOM_ID(2, 20, 0) |
| +#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_DOM_ID(2, 20, 1) |
| +#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_DOM_ID(2, 20, 2) |
| +#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_DOM_ID(2, 20, 3) |
| +#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_DOM_ID(2, 20, 4) |
| +#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_DOM_ID(2, 20, 5) |
| + |
| +/* VPU: Fake larb21 */ |
| +#define M4U_PORT_L21_APU_CODE MTK_M4U_DOM_ID(0, 21, 0) |
| +#define M4U_PORT_L21_APU_DATA MTK_M4U_DOM_ID(1, 21, 1) |
| +#define M4U_PORT_L21_APU_VLM MTK_M4U_DOM_ID(2, 21, 2) |
| + |
| +#endif |
| diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..584fc5b0f0d8bd69cbbd9664a433fc3f79abeb29 |
| --- /dev/null |
| +++ b/include/dt-bindings/memory/mtk-smi-larb-port.h |
| @@ -0,0 +1,21 @@ |
| +/* SPDX-License-Identifier: GPL-2.0-only */ |
| +/* |
| + * Copyright (c) 2015-2016 MediaTek Inc. |
| + * Author: Yong Wu <yong.wu@mediatek.com> |
| + */ |
| +#ifndef __DTS_MTK_IOMMU_PORT_H_ |
| +#define __DTS_MTK_IOMMU_PORT_H_ |
| + |
| +#define MTK_LARB_NR_MAX 32 |
| +#define MTK_M4U_DOM_NR_MAX 8 |
| + |
| +#define MTK_M4U_DOM_ID(dom, larb, port) ((dom & 0x7) << 16 |\ |
| + ((larb & 0x1f) << 5) | (port & 0x1f)) |
| + |
| +/* The default dom is 0. */ |
| +#define MTK_M4U_ID(larb, port) MTK_M4U_DOM_ID(0, larb, port) |
| +#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) |
| +#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) |
| +#define MTK_M4U_TO_DOM(id) (((id) >> 16) & 0x7) |
| + |
| +#endif |
| diff --git a/include/dt-bindings/pinctrl/mt6873-pinfunc.h b/include/dt-bindings/pinctrl/mt6873-pinfunc.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..f2131f48c02e06f434bd7fb53e917c721f8c5f88 |
| --- /dev/null |
| +++ b/include/dt-bindings/pinctrl/mt6873-pinfunc.h |
| @@ -0,0 +1,1344 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (C) 2019 MediaTek Inc. |
| + * Author: Andy Teng <andy.teng@mediatek.com> |
| + * |
| + */ |
| + |
| +#ifndef __MT6873_PINFUNC_H |
| +#define __MT6873_PINFUNC_H |
| + |
| +#include "mt65xx.h" |
| + |
| +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) |
| +#define PINMUX_GPIO0__FUNC_SPI6_CLK (MTK_PIN_NO(0) | 1) |
| +#define PINMUX_GPIO0__FUNC_I2S5_MCK (MTK_PIN_NO(0) | 2) |
| +#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 3) |
| +#define PINMUX_GPIO0__FUNC_TDM_LRCK (MTK_PIN_NO(0) | 4) |
| +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 5) |
| +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 6) |
| + |
| +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) |
| +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) |
| +#define PINMUX_GPIO1__FUNC_I2S5_BCK (MTK_PIN_NO(1) | 2) |
| +#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 3) |
| +#define PINMUX_GPIO1__FUNC_TDM_BCK (MTK_PIN_NO(1) | 4) |
| +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 5) |
| +#define PINMUX_GPIO1__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(1) | 6) |
| +#define PINMUX_GPIO1__FUNC_DBG_MON_A9 (MTK_PIN_NO(1) | 7) |
| + |
| +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) |
| +#define PINMUX_GPIO2__FUNC_SPI6_MI (MTK_PIN_NO(2) | 1) |
| +#define PINMUX_GPIO2__FUNC_I2S5_LRCK (MTK_PIN_NO(2) | 2) |
| +#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 3) |
| +#define PINMUX_GPIO2__FUNC_TDM_MCK (MTK_PIN_NO(2) | 4) |
| +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 5) |
| +#define PINMUX_GPIO2__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(2) | 6) |
| +#define PINMUX_GPIO2__FUNC_DBG_MON_A10 (MTK_PIN_NO(2) | 7) |
| + |
| +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) |
| +#define PINMUX_GPIO3__FUNC_SPI6_MO (MTK_PIN_NO(3) | 1) |
| +#define PINMUX_GPIO3__FUNC_I2S5_DO (MTK_PIN_NO(3) | 2) |
| +#define PINMUX_GPIO3__FUNC_PWM_3 (MTK_PIN_NO(3) | 3) |
| +#define PINMUX_GPIO3__FUNC_TDM_DATA0 (MTK_PIN_NO(3) | 4) |
| +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 5) |
| +#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 6) |
| +#define PINMUX_GPIO3__FUNC_DBG_MON_A11 (MTK_PIN_NO(3) | 7) |
| + |
| +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) |
| +#define PINMUX_GPIO4__FUNC_SPI4_A_CLK (MTK_PIN_NO(4) | 1) |
| +#define PINMUX_GPIO4__FUNC_I2S2_MCK (MTK_PIN_NO(4) | 2) |
| +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 3) |
| +#define PINMUX_GPIO4__FUNC_TDM_DATA1 (MTK_PIN_NO(4) | 4) |
| +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 5) |
| +#define PINMUX_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 6) |
| +#define PINMUX_GPIO4__FUNC_IDDIG (MTK_PIN_NO(4) | 7) |
| + |
| +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) |
| +#define PINMUX_GPIO5__FUNC_SPI4_A_CSB (MTK_PIN_NO(5) | 1) |
| +#define PINMUX_GPIO5__FUNC_I2S2_BCK (MTK_PIN_NO(5) | 2) |
| +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 3) |
| +#define PINMUX_GPIO5__FUNC_TDM_DATA2 (MTK_PIN_NO(5) | 4) |
| +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 5) |
| +#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 6) |
| +#define PINMUX_GPIO5__FUNC_USB_DRVVBUS (MTK_PIN_NO(5) | 7) |
| + |
| +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) |
| +#define PINMUX_GPIO6__FUNC_SPI4_A_MI (MTK_PIN_NO(6) | 1) |
| +#define PINMUX_GPIO6__FUNC_I2S2_LRCK (MTK_PIN_NO(6) | 2) |
| +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 3) |
| +#define PINMUX_GPIO6__FUNC_TDM_DATA3 (MTK_PIN_NO(6) | 4) |
| +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 5) |
| +#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 6) |
| + |
| +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) |
| +#define PINMUX_GPIO7__FUNC_SPI4_A_MO (MTK_PIN_NO(7) | 1) |
| +#define PINMUX_GPIO7__FUNC_I2S2_DI (MTK_PIN_NO(7) | 2) |
| +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 3) |
| +#define PINMUX_GPIO7__FUNC_WIFI_TXD (MTK_PIN_NO(7) | 4) |
| +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 5) |
| +#define PINMUX_GPIO7__FUNC_PCM1_DO0 (MTK_PIN_NO(7) | 6) |
| + |
| +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) |
| +#define PINMUX_GPIO8__FUNC_SRCLKENAI1 (MTK_PIN_NO(8) | 1) |
| +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) |
| +#define PINMUX_GPIO8__FUNC_KPCOL2 (MTK_PIN_NO(8) | 3) |
| +#define PINMUX_GPIO8__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(8) | 4) |
| +#define PINMUX_GPIO8__FUNC_CLKM1 (MTK_PIN_NO(8) | 5) |
| +#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 6) |
| +#define PINMUX_GPIO8__FUNC_DBG_MON_A12 (MTK_PIN_NO(8) | 7) |
| + |
| +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) |
| +#define PINMUX_GPIO9__FUNC_SRCLKENAI0 (MTK_PIN_NO(9) | 1) |
| +#define PINMUX_GPIO9__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(9) | 2) |
| +#define PINMUX_GPIO9__FUNC_KPROW2 (MTK_PIN_NO(9) | 3) |
| +#define PINMUX_GPIO9__FUNC_CMMCLK4 (MTK_PIN_NO(9) | 4) |
| +#define PINMUX_GPIO9__FUNC_CLKM3 (MTK_PIN_NO(9) | 5) |
| +#define PINMUX_GPIO9__FUNC_PCM1_DO2 (MTK_PIN_NO(9) | 6) |
| +#define PINMUX_GPIO9__FUNC_DBG_MON_A13 (MTK_PIN_NO(9) | 7) |
| + |
| +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) |
| +#define PINMUX_GPIO10__FUNC_MSDC2_CLK (MTK_PIN_NO(10) | 1) |
| +#define PINMUX_GPIO10__FUNC_SPI4_B_CLK (MTK_PIN_NO(10) | 2) |
| +#define PINMUX_GPIO10__FUNC_I2S8_MCK (MTK_PIN_NO(10) | 3) |
| +#define PINMUX_GPIO10__FUNC_MD_INT0 (MTK_PIN_NO(10) | 5) |
| +#define PINMUX_GPIO10__FUNC_TP_GPIO8_AO (MTK_PIN_NO(10) | 6) |
| + |
| +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) |
| +#define PINMUX_GPIO11__FUNC_MSDC2_CMD (MTK_PIN_NO(11) | 1) |
| +#define PINMUX_GPIO11__FUNC_SPI4_B_CSB (MTK_PIN_NO(11) | 2) |
| +#define PINMUX_GPIO11__FUNC_I2S8_BCK (MTK_PIN_NO(11) | 3) |
| +#define PINMUX_GPIO11__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(11) | 4) |
| +#define PINMUX_GPIO11__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(11) | 5) |
| +#define PINMUX_GPIO11__FUNC_TP_GPIO9_AO (MTK_PIN_NO(11) | 6) |
| + |
| +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) |
| +#define PINMUX_GPIO12__FUNC_MSDC2_DAT3 (MTK_PIN_NO(12) | 1) |
| +#define PINMUX_GPIO12__FUNC_SPI4_B_MI (MTK_PIN_NO(12) | 2) |
| +#define PINMUX_GPIO12__FUNC_I2S8_LRCK (MTK_PIN_NO(12) | 3) |
| +#define PINMUX_GPIO12__FUNC_DMIC1_CLK (MTK_PIN_NO(12) | 4) |
| +#define PINMUX_GPIO12__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(12) | 5) |
| +#define PINMUX_GPIO12__FUNC_TP_GPIO10_AO (MTK_PIN_NO(12) | 6) |
| + |
| +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) |
| +#define PINMUX_GPIO13__FUNC_MSDC2_DAT0 (MTK_PIN_NO(13) | 1) |
| +#define PINMUX_GPIO13__FUNC_SPI4_B_MO (MTK_PIN_NO(13) | 2) |
| +#define PINMUX_GPIO13__FUNC_I2S8_DI (MTK_PIN_NO(13) | 3) |
| +#define PINMUX_GPIO13__FUNC_DMIC1_DAT (MTK_PIN_NO(13) | 4) |
| +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 5) |
| +#define PINMUX_GPIO13__FUNC_TP_GPIO11_AO (MTK_PIN_NO(13) | 6) |
| + |
| +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) |
| +#define PINMUX_GPIO14__FUNC_MSDC2_DAT2 (MTK_PIN_NO(14) | 1) |
| +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 2) |
| +#define PINMUX_GPIO14__FUNC_SCL_6306 (MTK_PIN_NO(14) | 3) |
| +#define PINMUX_GPIO14__FUNC_PCIE_PERESET_N (MTK_PIN_NO(14) | 4) |
| +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 5) |
| +#define PINMUX_GPIO14__FUNC_TP_GPIO12_AO (MTK_PIN_NO(14) | 6) |
| + |
| +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) |
| +#define PINMUX_GPIO15__FUNC_MSDC2_DAT1 (MTK_PIN_NO(15) | 1) |
| +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 2) |
| +#define PINMUX_GPIO15__FUNC_SDA_6306 (MTK_PIN_NO(15) | 3) |
| +#define PINMUX_GPIO15__FUNC_PCIE_WAKE_N (MTK_PIN_NO(15) | 4) |
| +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 5) |
| +#define PINMUX_GPIO15__FUNC_TP_GPIO13_AO (MTK_PIN_NO(15) | 6) |
| + |
| +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) |
| +#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1) |
| +#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 2) |
| +#define PINMUX_GPIO16__FUNC_TP_GPIO14_AO (MTK_PIN_NO(16) | 3) |
| +#define PINMUX_GPIO16__FUNC_KPCOL2 (MTK_PIN_NO(16) | 4) |
| +#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 5) |
| +#define PINMUX_GPIO16__FUNC_SPI7_A_MI (MTK_PIN_NO(16) | 6) |
| +#define PINMUX_GPIO16__FUNC_DBG_MON_A0 (MTK_PIN_NO(16) | 7) |
| + |
| +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) |
| +#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1) |
| +#define PINMUX_GPIO17__FUNC_USB_DRVVBUS (MTK_PIN_NO(17) | 2) |
| +#define PINMUX_GPIO17__FUNC_TP_GPIO15_AO (MTK_PIN_NO(17) | 3) |
| +#define PINMUX_GPIO17__FUNC_KPROW2 (MTK_PIN_NO(17) | 4) |
| +#define PINMUX_GPIO17__FUNC_SPI7_A_MO (MTK_PIN_NO(17) | 6) |
| +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) |
| + |
| +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) |
| +#define PINMUX_GPIO18__FUNC_SRCLKENAI0 (MTK_PIN_NO(18) | 1) |
| +#define PINMUX_GPIO18__FUNC_SPI4_C_MI (MTK_PIN_NO(18) | 2) |
| +#define PINMUX_GPIO18__FUNC_SPI1_B_MI (MTK_PIN_NO(18) | 3) |
| +#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 4) |
| +#define PINMUX_GPIO18__FUNC_ANT_SEL10 (MTK_PIN_NO(18) | 5) |
| +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 6) |
| +#define PINMUX_GPIO18__FUNC_DBG_MON_B2 (MTK_PIN_NO(18) | 7) |
| + |
| +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) |
| +#define PINMUX_GPIO19__FUNC_SRCLKENAI1 (MTK_PIN_NO(19) | 1) |
| +#define PINMUX_GPIO19__FUNC_SPI4_C_MO (MTK_PIN_NO(19) | 2) |
| +#define PINMUX_GPIO19__FUNC_SPI1_B_MO (MTK_PIN_NO(19) | 3) |
| +#define PINMUX_GPIO19__FUNC_ANT_SEL11 (MTK_PIN_NO(19) | 5) |
| +#define PINMUX_GPIO19__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(19) | 6) |
| +#define PINMUX_GPIO19__FUNC_DBG_MON_B3 (MTK_PIN_NO(19) | 7) |
| + |
| +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) |
| +#define PINMUX_GPIO20__FUNC_SRCLKENAI0 (MTK_PIN_NO(20) | 1) |
| +#define PINMUX_GPIO20__FUNC_SPI4_C_CLK (MTK_PIN_NO(20) | 2) |
| +#define PINMUX_GPIO20__FUNC_SPI1_B_CLK (MTK_PIN_NO(20) | 3) |
| +#define PINMUX_GPIO20__FUNC_PWM_3 (MTK_PIN_NO(20) | 4) |
| +#define PINMUX_GPIO20__FUNC_ANT_SEL12 (MTK_PIN_NO(20) | 5) |
| +#define PINMUX_GPIO20__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(20) | 6) |
| +#define PINMUX_GPIO20__FUNC_DBG_MON_B4 (MTK_PIN_NO(20) | 7) |
| + |
| +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) |
| +#define PINMUX_GPIO21__FUNC_SPI4_C_CSB (MTK_PIN_NO(21) | 2) |
| +#define PINMUX_GPIO21__FUNC_SPI1_B_CSB (MTK_PIN_NO(21) | 3) |
| +#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 6) |
| +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) |
| + |
| +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) |
| +#define PINMUX_GPIO22__FUNC_SPI0_C_CLK (MTK_PIN_NO(22) | 2) |
| +#define PINMUX_GPIO22__FUNC_SPI7_B_CLK (MTK_PIN_NO(22) | 3) |
| +#define PINMUX_GPIO22__FUNC_I2S7_BCK (MTK_PIN_NO(22) | 4) |
| +#define PINMUX_GPIO22__FUNC_I2S9_BCK (MTK_PIN_NO(22) | 5) |
| +#define PINMUX_GPIO22__FUNC_SCL_6306 (MTK_PIN_NO(22) | 6) |
| + |
| +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) |
| +#define PINMUX_GPIO23__FUNC_SPI0_C_CSB (MTK_PIN_NO(23) | 2) |
| +#define PINMUX_GPIO23__FUNC_SPI7_B_CSB (MTK_PIN_NO(23) | 3) |
| +#define PINMUX_GPIO23__FUNC_I2S7_LRCK (MTK_PIN_NO(23) | 4) |
| +#define PINMUX_GPIO23__FUNC_I2S9_LRCK (MTK_PIN_NO(23) | 5) |
| +#define PINMUX_GPIO23__FUNC_SDA_6306 (MTK_PIN_NO(23) | 6) |
| + |
| +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) |
| +#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 1) |
| +#define PINMUX_GPIO24__FUNC_SPI0_C_MI (MTK_PIN_NO(24) | 2) |
| +#define PINMUX_GPIO24__FUNC_SPI7_B_MI (MTK_PIN_NO(24) | 3) |
| +#define PINMUX_GPIO24__FUNC_I2S6_DI (MTK_PIN_NO(24) | 4) |
| +#define PINMUX_GPIO24__FUNC_I2S8_DI (MTK_PIN_NO(24) | 5) |
| +#define PINMUX_GPIO24__FUNC_SPINOR_CS (MTK_PIN_NO(24) | 6) |
| + |
| +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) |
| +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) |
| +#define PINMUX_GPIO25__FUNC_SPI0_C_MO (MTK_PIN_NO(25) | 2) |
| +#define PINMUX_GPIO25__FUNC_SPI7_B_MO (MTK_PIN_NO(25) | 3) |
| +#define PINMUX_GPIO25__FUNC_I2S7_DO (MTK_PIN_NO(25) | 4) |
| +#define PINMUX_GPIO25__FUNC_I2S9_DO (MTK_PIN_NO(25) | 5) |
| +#define PINMUX_GPIO25__FUNC_SPINOR_CK (MTK_PIN_NO(25) | 6) |
| + |
| +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) |
| +#define PINMUX_GPIO26__FUNC_PWM_2 (MTK_PIN_NO(26) | 1) |
| +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 2) |
| +#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3) |
| +#define PINMUX_GPIO26__FUNC_SPI5_C_MI (MTK_PIN_NO(26) | 4) |
| +#define PINMUX_GPIO26__FUNC_I2S9_BCK (MTK_PIN_NO(26) | 5) |
| + |
| +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) |
| +#define PINMUX_GPIO27__FUNC_PWM_3 (MTK_PIN_NO(27) | 1) |
| +#define PINMUX_GPIO27__FUNC_CLKM1 (MTK_PIN_NO(27) | 2) |
| +#define PINMUX_GPIO27__FUNC_SPI5_C_MO (MTK_PIN_NO(27) | 4) |
| +#define PINMUX_GPIO27__FUNC_I2S9_LRCK (MTK_PIN_NO(27) | 5) |
| +#define PINMUX_GPIO27__FUNC_SPINOR_IO0 (MTK_PIN_NO(27) | 6) |
| + |
| +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) |
| +#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 1) |
| +#define PINMUX_GPIO28__FUNC_CLKM2 (MTK_PIN_NO(28) | 2) |
| +#define PINMUX_GPIO28__FUNC_SPI5_C_CSB (MTK_PIN_NO(28) | 4) |
| +#define PINMUX_GPIO28__FUNC_I2S9_MCK (MTK_PIN_NO(28) | 5) |
| +#define PINMUX_GPIO28__FUNC_SPINOR_IO1 (MTK_PIN_NO(28) | 6) |
| + |
| +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) |
| +#define PINMUX_GPIO29__FUNC_PWM_1 (MTK_PIN_NO(29) | 1) |
| +#define PINMUX_GPIO29__FUNC_CLKM3 (MTK_PIN_NO(29) | 2) |
| +#define PINMUX_GPIO29__FUNC_SPI5_C_CLK (MTK_PIN_NO(29) | 4) |
| +#define PINMUX_GPIO29__FUNC_I2S9_DO (MTK_PIN_NO(29) | 5) |
| +#define PINMUX_GPIO29__FUNC_SPINOR_IO2 (MTK_PIN_NO(29) | 6) |
| + |
| +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) |
| +#define PINMUX_GPIO30__FUNC_PWM_2 (MTK_PIN_NO(30) | 1) |
| +#define PINMUX_GPIO30__FUNC_CLKM0 (MTK_PIN_NO(30) | 2) |
| +#define PINMUX_GPIO30__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(30) | 3) |
| +#define PINMUX_GPIO30__FUNC_I2S7_MCK (MTK_PIN_NO(30) | 4) |
| +#define PINMUX_GPIO30__FUNC_I2S9_MCK (MTK_PIN_NO(30) | 5) |
| +#define PINMUX_GPIO30__FUNC_SPINOR_IO3 (MTK_PIN_NO(30) | 6) |
| + |
| +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) |
| +#define PINMUX_GPIO31__FUNC_I2S3_MCK (MTK_PIN_NO(31) | 1) |
| +#define PINMUX_GPIO31__FUNC_I2S1_MCK (MTK_PIN_NO(31) | 2) |
| +#define PINMUX_GPIO31__FUNC_I2S5_MCK (MTK_PIN_NO(31) | 3) |
| +#define PINMUX_GPIO31__FUNC_SRCLKENAI0 (MTK_PIN_NO(31) | 4) |
| +#define PINMUX_GPIO31__FUNC_I2S0_MCK (MTK_PIN_NO(31) | 5) |
| + |
| +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) |
| +#define PINMUX_GPIO32__FUNC_I2S3_BCK (MTK_PIN_NO(32) | 1) |
| +#define PINMUX_GPIO32__FUNC_I2S1_BCK (MTK_PIN_NO(32) | 2) |
| +#define PINMUX_GPIO32__FUNC_I2S5_BCK (MTK_PIN_NO(32) | 3) |
| +#define PINMUX_GPIO32__FUNC_PCM0_CLK (MTK_PIN_NO(32) | 4) |
| +#define PINMUX_GPIO32__FUNC_I2S0_BCK (MTK_PIN_NO(32) | 5) |
| + |
| +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) |
| +#define PINMUX_GPIO33__FUNC_I2S3_LRCK (MTK_PIN_NO(33) | 1) |
| +#define PINMUX_GPIO33__FUNC_I2S1_LRCK (MTK_PIN_NO(33) | 2) |
| +#define PINMUX_GPIO33__FUNC_I2S5_LRCK (MTK_PIN_NO(33) | 3) |
| +#define PINMUX_GPIO33__FUNC_PCM0_SYNC (MTK_PIN_NO(33) | 4) |
| +#define PINMUX_GPIO33__FUNC_I2S0_LRCK (MTK_PIN_NO(33) | 5) |
| + |
| +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) |
| +#define PINMUX_GPIO34__FUNC_I2S0_DI (MTK_PIN_NO(34) | 1) |
| +#define PINMUX_GPIO34__FUNC_I2S2_DI (MTK_PIN_NO(34) | 2) |
| +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) |
| +#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 4) |
| +#define PINMUX_GPIO34__FUNC_I2S0_DI_A (MTK_PIN_NO(34) | 5) |
| + |
| +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) |
| +#define PINMUX_GPIO35__FUNC_I2S3_DO (MTK_PIN_NO(35) | 1) |
| +#define PINMUX_GPIO35__FUNC_I2S1_DO (MTK_PIN_NO(35) | 2) |
| +#define PINMUX_GPIO35__FUNC_I2S5_DO (MTK_PIN_NO(35) | 3) |
| +#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 4) |
| + |
| +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) |
| +#define PINMUX_GPIO36__FUNC_SPI5_A_CLK (MTK_PIN_NO(36) | 1) |
| +#define PINMUX_GPIO36__FUNC_DMIC1_CLK (MTK_PIN_NO(36) | 2) |
| +#define PINMUX_GPIO36__FUNC_MD_URXD0 (MTK_PIN_NO(36) | 4) |
| +#define PINMUX_GPIO36__FUNC_UCTS0 (MTK_PIN_NO(36) | 5) |
| +#define PINMUX_GPIO36__FUNC_URXD1 (MTK_PIN_NO(36) | 6) |
| + |
| +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) |
| +#define PINMUX_GPIO37__FUNC_SPI5_A_CSB (MTK_PIN_NO(37) | 1) |
| +#define PINMUX_GPIO37__FUNC_DMIC1_DAT (MTK_PIN_NO(37) | 2) |
| +#define PINMUX_GPIO37__FUNC_MD_UTXD0 (MTK_PIN_NO(37) | 4) |
| +#define PINMUX_GPIO37__FUNC_URTS0 (MTK_PIN_NO(37) | 5) |
| +#define PINMUX_GPIO37__FUNC_UTXD1 (MTK_PIN_NO(37) | 6) |
| + |
| +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) |
| +#define PINMUX_GPIO38__FUNC_SPI5_A_MI (MTK_PIN_NO(38) | 1) |
| +#define PINMUX_GPIO38__FUNC_DMIC_CLK (MTK_PIN_NO(38) | 2) |
| +#define PINMUX_GPIO38__FUNC_MD_URXD1 (MTK_PIN_NO(38) | 4) |
| +#define PINMUX_GPIO38__FUNC_URXD0 (MTK_PIN_NO(38) | 5) |
| +#define PINMUX_GPIO38__FUNC_UCTS1 (MTK_PIN_NO(38) | 6) |
| + |
| +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) |
| +#define PINMUX_GPIO39__FUNC_SPI5_A_MO (MTK_PIN_NO(39) | 1) |
| +#define PINMUX_GPIO39__FUNC_DMIC_DAT (MTK_PIN_NO(39) | 2) |
| +#define PINMUX_GPIO39__FUNC_MD_UTXD1 (MTK_PIN_NO(39) | 4) |
| +#define PINMUX_GPIO39__FUNC_UTXD0 (MTK_PIN_NO(39) | 5) |
| +#define PINMUX_GPIO39__FUNC_URTS1 (MTK_PIN_NO(39) | 6) |
| + |
| +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) |
| +#define PINMUX_GPIO40__FUNC_DISP_PWM (MTK_PIN_NO(40) | 1) |
| +#define PINMUX_GPIO40__FUNC_DBG_MON_A6 (MTK_PIN_NO(40) | 7) |
| + |
| +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) |
| +#define PINMUX_GPIO41__FUNC_DSI_TE (MTK_PIN_NO(41) | 1) |
| +#define PINMUX_GPIO41__FUNC_DBG_MON_A7 (MTK_PIN_NO(41) | 7) |
| + |
| +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) |
| +#define PINMUX_GPIO42__FUNC_LCM_RST (MTK_PIN_NO(42) | 1) |
| +#define PINMUX_GPIO42__FUNC_DBG_MON_A8 (MTK_PIN_NO(42) | 7) |
| + |
| +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) |
| +#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 1) |
| +#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 2) |
| +#define PINMUX_GPIO43__FUNC_SCL_6306 (MTK_PIN_NO(43) | 3) |
| +#define PINMUX_GPIO43__FUNC_ADSP_URXD0 (MTK_PIN_NO(43) | 4) |
| +#define PINMUX_GPIO43__FUNC_PTA_RXD (MTK_PIN_NO(43) | 5) |
| +#define PINMUX_GPIO43__FUNC_SSPM_URXD_AO (MTK_PIN_NO(43) | 6) |
| +#define PINMUX_GPIO43__FUNC_DBG_MON_B0 (MTK_PIN_NO(43) | 7) |
| + |
| +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) |
| +#define PINMUX_GPIO44__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(44) | 1) |
| +#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 2) |
| +#define PINMUX_GPIO44__FUNC_SDA_6306 (MTK_PIN_NO(44) | 3) |
| +#define PINMUX_GPIO44__FUNC_ADSP_UTXD0 (MTK_PIN_NO(44) | 4) |
| +#define PINMUX_GPIO44__FUNC_PTA_TXD (MTK_PIN_NO(44) | 5) |
| +#define PINMUX_GPIO44__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(44) | 6) |
| +#define PINMUX_GPIO44__FUNC_DBG_MON_B1 (MTK_PIN_NO(44) | 7) |
| + |
| +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) |
| +#define PINMUX_GPIO45__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(45) | 1) |
| +#define PINMUX_GPIO45__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(45) | 2) |
| +#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(45) | 3) |
| +#define PINMUX_GPIO45__FUNC_APU_JTAG_TDI (MTK_PIN_NO(45) | 4) |
| +#define PINMUX_GPIO45__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(45) | 5) |
| +#define PINMUX_GPIO45__FUNC_LVTS_SCK (MTK_PIN_NO(45) | 6) |
| +#define PINMUX_GPIO45__FUNC_CONN_DSP_JDI (MTK_PIN_NO(45) | 7) |
| + |
| +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) |
| +#define PINMUX_GPIO46__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(46) | 1) |
| +#define PINMUX_GPIO46__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(46) | 2) |
| +#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(46) | 3) |
| +#define PINMUX_GPIO46__FUNC_APU_JTAG_TMS (MTK_PIN_NO(46) | 4) |
| +#define PINMUX_GPIO46__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(46) | 5) |
| +#define PINMUX_GPIO46__FUNC_LVTS_SDI (MTK_PIN_NO(46) | 6) |
| +#define PINMUX_GPIO46__FUNC_CONN_DSP_JMS (MTK_PIN_NO(46) | 7) |
| + |
| +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) |
| +#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 1) |
| +#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 2) |
| +#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(47) | 3) |
| +#define PINMUX_GPIO47__FUNC_APU_JTAG_TDO (MTK_PIN_NO(47) | 4) |
| +#define PINMUX_GPIO47__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(47) | 5) |
| +#define PINMUX_GPIO47__FUNC_LVTS_SCF (MTK_PIN_NO(47) | 6) |
| +#define PINMUX_GPIO47__FUNC_CONN_DSP_JDO (MTK_PIN_NO(47) | 7) |
| + |
| +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) |
| +#define PINMUX_GPIO48__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(48) | 1) |
| +#define PINMUX_GPIO48__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(48) | 2) |
| +#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(48) | 3) |
| +#define PINMUX_GPIO48__FUNC_APU_JTAG_TRST (MTK_PIN_NO(48) | 4) |
| +#define PINMUX_GPIO48__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(48) | 5) |
| +#define PINMUX_GPIO48__FUNC_LVTS_FOUT (MTK_PIN_NO(48) | 6) |
| +#define PINMUX_GPIO48__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(48) | 7) |
| + |
| +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) |
| +#define PINMUX_GPIO49__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(49) | 1) |
| +#define PINMUX_GPIO49__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(49) | 2) |
| +#define PINMUX_GPIO49__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(49) | 3) |
| +#define PINMUX_GPIO49__FUNC_APU_JTAG_TCK (MTK_PIN_NO(49) | 4) |
| +#define PINMUX_GPIO49__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(49) | 5) |
| +#define PINMUX_GPIO49__FUNC_LVTS_SDO (MTK_PIN_NO(49) | 6) |
| +#define PINMUX_GPIO49__FUNC_CONN_DSP_JCK (MTK_PIN_NO(49) | 7) |
| + |
| +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) |
| +#define PINMUX_GPIO50__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(50) | 1) |
| +#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2) |
| +#define PINMUX_GPIO50__FUNC_LVTS_26M (MTK_PIN_NO(50) | 6) |
| + |
| +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) |
| +#define PINMUX_GPIO51__FUNC_MSDC1_CLK (MTK_PIN_NO(51) | 1) |
| +#define PINMUX_GPIO51__FUNC_PCM1_CLK (MTK_PIN_NO(51) | 2) |
| +#define PINMUX_GPIO51__FUNC_CONN_DSP_JCK (MTK_PIN_NO(51) | 3) |
| +#define PINMUX_GPIO51__FUNC_UDI_TCK (MTK_PIN_NO(51) | 4) |
| +#define PINMUX_GPIO51__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(51) | 5) |
| +#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 6) |
| +#define PINMUX_GPIO51__FUNC_JTCK_SEL3 (MTK_PIN_NO(51) | 7) |
| + |
| +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) |
| +#define PINMUX_GPIO52__FUNC_MSDC1_CMD (MTK_PIN_NO(52) | 1) |
| +#define PINMUX_GPIO52__FUNC_PCM1_SYNC (MTK_PIN_NO(52) | 2) |
| +#define PINMUX_GPIO52__FUNC_CONN_DSP_JMS (MTK_PIN_NO(52) | 3) |
| +#define PINMUX_GPIO52__FUNC_UDI_TMS (MTK_PIN_NO(52) | 4) |
| +#define PINMUX_GPIO52__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(52) | 5) |
| +#define PINMUX_GPIO52__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(52) | 6) |
| +#define PINMUX_GPIO52__FUNC_JTMS_SEL3 (MTK_PIN_NO(52) | 7) |
| + |
| +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) |
| +#define PINMUX_GPIO53__FUNC_MSDC1_DAT3 (MTK_PIN_NO(53) | 1) |
| +#define PINMUX_GPIO53__FUNC_PCM1_DI (MTK_PIN_NO(53) | 2) |
| +#define PINMUX_GPIO53__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(53) | 3) |
| +#define PINMUX_GPIO53__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(53) | 4) |
| + |
| +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) |
| +#define PINMUX_GPIO54__FUNC_MSDC1_DAT0 (MTK_PIN_NO(54) | 1) |
| +#define PINMUX_GPIO54__FUNC_PCM1_DO0 (MTK_PIN_NO(54) | 2) |
| +#define PINMUX_GPIO54__FUNC_CONN_DSP_JDI (MTK_PIN_NO(54) | 3) |
| +#define PINMUX_GPIO54__FUNC_UDI_TDI (MTK_PIN_NO(54) | 4) |
| +#define PINMUX_GPIO54__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(54) | 5) |
| +#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(54) | 6) |
| +#define PINMUX_GPIO54__FUNC_JTDI_SEL3 (MTK_PIN_NO(54) | 7) |
| + |
| +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) |
| +#define PINMUX_GPIO55__FUNC_MSDC1_DAT2 (MTK_PIN_NO(55) | 1) |
| +#define PINMUX_GPIO55__FUNC_PCM1_DO2 (MTK_PIN_NO(55) | 2) |
| +#define PINMUX_GPIO55__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(55) | 3) |
| +#define PINMUX_GPIO55__FUNC_UDI_NTRST (MTK_PIN_NO(55) | 4) |
| +#define PINMUX_GPIO55__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(55) | 5) |
| +#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(55) | 6) |
| +#define PINMUX_GPIO55__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(55) | 7) |
| + |
| +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) |
| +#define PINMUX_GPIO56__FUNC_MSDC1_DAT1 (MTK_PIN_NO(56) | 1) |
| +#define PINMUX_GPIO56__FUNC_PCM1_DO1 (MTK_PIN_NO(56) | 2) |
| +#define PINMUX_GPIO56__FUNC_CONN_DSP_JDO (MTK_PIN_NO(56) | 3) |
| +#define PINMUX_GPIO56__FUNC_UDI_TDO (MTK_PIN_NO(56) | 4) |
| +#define PINMUX_GPIO56__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(56) | 5) |
| +#define PINMUX_GPIO56__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(56) | 6) |
| +#define PINMUX_GPIO56__FUNC_JTDO_SEL3 (MTK_PIN_NO(56) | 7) |
| + |
| +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) |
| +#define PINMUX_GPIO57__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(57) | 1) |
| + |
| +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) |
| +#define PINMUX_GPIO58__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(58) | 1) |
| + |
| +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) |
| +#define PINMUX_GPIO59__FUNC_MIPI_M_SCLK (MTK_PIN_NO(59) | 1) |
| + |
| +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) |
| +#define PINMUX_GPIO60__FUNC_MIPI_M_SDATA (MTK_PIN_NO(60) | 1) |
| + |
| +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) |
| +#define PINMUX_GPIO61__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(61) | 1) |
| + |
| +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) |
| +#define PINMUX_GPIO62__FUNC_DIGRF_IRQ (MTK_PIN_NO(62) | 1) |
| + |
| +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) |
| +#define PINMUX_GPIO63__FUNC_BPI_BUS0 (MTK_PIN_NO(63) | 1) |
| +#define PINMUX_GPIO63__FUNC_PCIE_WAKE_N (MTK_PIN_NO(63) | 3) |
| + |
| +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) |
| +#define PINMUX_GPIO64__FUNC_BPI_BUS1 (MTK_PIN_NO(64) | 1) |
| +#define PINMUX_GPIO64__FUNC_PCIE_PERESET_N (MTK_PIN_NO(64) | 3) |
| + |
| +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) |
| +#define PINMUX_GPIO65__FUNC_BPI_BUS2 (MTK_PIN_NO(65) | 1) |
| +#define PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(65) | 3) |
| + |
| +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) |
| +#define PINMUX_GPIO66__FUNC_BPI_BUS3 (MTK_PIN_NO(66) | 1) |
| + |
| +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) |
| +#define PINMUX_GPIO67__FUNC_BPI_BUS4 (MTK_PIN_NO(67) | 1) |
| + |
| +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) |
| +#define PINMUX_GPIO68__FUNC_BPI_BUS5 (MTK_PIN_NO(68) | 1) |
| + |
| +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) |
| +#define PINMUX_GPIO69__FUNC_BPI_BUS6 (MTK_PIN_NO(69) | 1) |
| +#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(69) | 2) |
| + |
| +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) |
| +#define PINMUX_GPIO70__FUNC_BPI_BUS7 (MTK_PIN_NO(70) | 1) |
| +#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(70) | 2) |
| + |
| +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) |
| +#define PINMUX_GPIO71__FUNC_BPI_BUS8 (MTK_PIN_NO(71) | 1) |
| +#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(71) | 2) |
| + |
| +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) |
| +#define PINMUX_GPIO72__FUNC_BPI_BUS9 (MTK_PIN_NO(72) | 1) |
| +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(72) | 2) |
| + |
| +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) |
| +#define PINMUX_GPIO73__FUNC_BPI_BUS10 (MTK_PIN_NO(73) | 1) |
| +#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(73) | 2) |
| + |
| +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) |
| +#define PINMUX_GPIO74__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 1) |
| +#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 2) |
| + |
| +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) |
| +#define PINMUX_GPIO75__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 1) |
| +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 2) |
| + |
| +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) |
| +#define PINMUX_GPIO76__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 1) |
| +#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 2) |
| + |
| +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) |
| +#define PINMUX_GPIO77__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 1) |
| +#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 2) |
| + |
| +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) |
| +#define PINMUX_GPIO78__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 1) |
| +#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 2) |
| + |
| +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) |
| +#define PINMUX_GPIO79__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 1) |
| +#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 2) |
| + |
| +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) |
| +#define PINMUX_GPIO80__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 1) |
| +#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 2) |
| +#define PINMUX_GPIO80__FUNC_PCIE_WAKE_N (MTK_PIN_NO(80) | 3) |
| + |
| +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) |
| +#define PINMUX_GPIO81__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 1) |
| +#define PINMUX_GPIO81__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 2) |
| +#define PINMUX_GPIO81__FUNC_PCIE_PERESET_N (MTK_PIN_NO(81) | 3) |
| + |
| +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) |
| +#define PINMUX_GPIO82__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 1) |
| +#define PINMUX_GPIO82__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 2) |
| +#define PINMUX_GPIO82__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(82) | 3) |
| + |
| +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) |
| +#define PINMUX_GPIO83__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 1) |
| +#define PINMUX_GPIO83__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 2) |
| + |
| +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) |
| +#define PINMUX_GPIO84__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 1) |
| +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 2) |
| + |
| +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) |
| +#define PINMUX_GPIO85__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(85) | 1) |
| +#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2) |
| + |
| +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) |
| +#define PINMUX_GPIO86__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(86) | 1) |
| +#define PINMUX_GPIO86__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(86) | 2) |
| + |
| +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) |
| +#define PINMUX_GPIO87__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(87) | 1) |
| +#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(87) | 2) |
| + |
| +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) |
| +#define PINMUX_GPIO88__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(88) | 1) |
| +#define PINMUX_GPIO88__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(88) | 2) |
| + |
| +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) |
| +#define PINMUX_GPIO89__FUNC_SPMI_SCL (MTK_PIN_NO(89) | 1) |
| +#define PINMUX_GPIO89__FUNC_SCL10 (MTK_PIN_NO(89) | 2) |
| + |
| +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) |
| +#define PINMUX_GPIO90__FUNC_SPMI_SDA (MTK_PIN_NO(90) | 1) |
| +#define PINMUX_GPIO90__FUNC_SDA10 (MTK_PIN_NO(90) | 2) |
| + |
| +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) |
| +#define PINMUX_GPIO91__FUNC_AP_GOOD (MTK_PIN_NO(91) | 1) |
| + |
| +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) |
| +#define PINMUX_GPIO92__FUNC_URXD0 (MTK_PIN_NO(92) | 1) |
| +#define PINMUX_GPIO92__FUNC_MD_URXD0 (MTK_PIN_NO(92) | 2) |
| +#define PINMUX_GPIO92__FUNC_MD_URXD1 (MTK_PIN_NO(92) | 3) |
| +#define PINMUX_GPIO92__FUNC_SSPM_URXD_AO (MTK_PIN_NO(92) | 4) |
| +#define PINMUX_GPIO92__FUNC_CONN_UART0_RXD (MTK_PIN_NO(92) | 5) |
| + |
| +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) |
| +#define PINMUX_GPIO93__FUNC_UTXD0 (MTK_PIN_NO(93) | 1) |
| +#define PINMUX_GPIO93__FUNC_MD_UTXD0 (MTK_PIN_NO(93) | 2) |
| +#define PINMUX_GPIO93__FUNC_MD_UTXD1 (MTK_PIN_NO(93) | 3) |
| +#define PINMUX_GPIO93__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(93) | 4) |
| +#define PINMUX_GPIO93__FUNC_CONN_UART0_TXD (MTK_PIN_NO(93) | 5) |
| +#define PINMUX_GPIO93__FUNC_WIFI_TXD (MTK_PIN_NO(93) | 6) |
| + |
| +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) |
| +#define PINMUX_GPIO94__FUNC_URXD1 (MTK_PIN_NO(94) | 1) |
| +#define PINMUX_GPIO94__FUNC_ADSP_URXD0 (MTK_PIN_NO(94) | 2) |
| +#define PINMUX_GPIO94__FUNC_MD32_0_RXD (MTK_PIN_NO(94) | 3) |
| +#define PINMUX_GPIO94__FUNC_SSPM_URXD_AO (MTK_PIN_NO(94) | 4) |
| +#define PINMUX_GPIO94__FUNC_TP_URXD1_AO (MTK_PIN_NO(94) | 5) |
| +#define PINMUX_GPIO94__FUNC_TP_URXD2_AO (MTK_PIN_NO(94) | 6) |
| +#define PINMUX_GPIO94__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(94) | 7) |
| + |
| +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) |
| +#define PINMUX_GPIO95__FUNC_UTXD1 (MTK_PIN_NO(95) | 1) |
| +#define PINMUX_GPIO95__FUNC_ADSP_UTXD0 (MTK_PIN_NO(95) | 2) |
| +#define PINMUX_GPIO95__FUNC_MD32_0_TXD (MTK_PIN_NO(95) | 3) |
| +#define PINMUX_GPIO95__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(95) | 4) |
| +#define PINMUX_GPIO95__FUNC_TP_UTXD1_AO (MTK_PIN_NO(95) | 5) |
| +#define PINMUX_GPIO95__FUNC_TP_UTXD2_AO (MTK_PIN_NO(95) | 6) |
| +#define PINMUX_GPIO95__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(95) | 7) |
| + |
| +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) |
| +#define PINMUX_GPIO96__FUNC_TDM_LRCK (MTK_PIN_NO(96) | 1) |
| +#define PINMUX_GPIO96__FUNC_I2S7_LRCK (MTK_PIN_NO(96) | 2) |
| +#define PINMUX_GPIO96__FUNC_I2S9_LRCK (MTK_PIN_NO(96) | 3) |
| +#define PINMUX_GPIO96__FUNC_DPI_D0 (MTK_PIN_NO(96) | 4) |
| +#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(96) | 5) |
| +#define PINMUX_GPIO96__FUNC_IO_JTAG_TDI (MTK_PIN_NO(96) | 7) |
| + |
| +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) |
| +#define PINMUX_GPIO97__FUNC_TDM_BCK (MTK_PIN_NO(97) | 1) |
| +#define PINMUX_GPIO97__FUNC_I2S7_BCK (MTK_PIN_NO(97) | 2) |
| +#define PINMUX_GPIO97__FUNC_I2S9_BCK (MTK_PIN_NO(97) | 3) |
| +#define PINMUX_GPIO97__FUNC_DPI_D1 (MTK_PIN_NO(97) | 4) |
| +#define PINMUX_GPIO97__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(97) | 5) |
| +#define PINMUX_GPIO97__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(97) | 7) |
| + |
| +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) |
| +#define PINMUX_GPIO98__FUNC_TDM_MCK (MTK_PIN_NO(98) | 1) |
| +#define PINMUX_GPIO98__FUNC_I2S7_MCK (MTK_PIN_NO(98) | 2) |
| +#define PINMUX_GPIO98__FUNC_I2S9_MCK (MTK_PIN_NO(98) | 3) |
| +#define PINMUX_GPIO98__FUNC_DPI_D2 (MTK_PIN_NO(98) | 4) |
| +#define PINMUX_GPIO98__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(98) | 5) |
| +#define PINMUX_GPIO98__FUNC_IO_JTAG_TCK (MTK_PIN_NO(98) | 7) |
| + |
| +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) |
| +#define PINMUX_GPIO99__FUNC_TDM_DATA0 (MTK_PIN_NO(99) | 1) |
| +#define PINMUX_GPIO99__FUNC_I2S6_DI (MTK_PIN_NO(99) | 2) |
| +#define PINMUX_GPIO99__FUNC_I2S8_DI (MTK_PIN_NO(99) | 3) |
| +#define PINMUX_GPIO99__FUNC_DPI_D3 (MTK_PIN_NO(99) | 4) |
| +#define PINMUX_GPIO99__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(99) | 5) |
| +#define PINMUX_GPIO99__FUNC_IO_JTAG_TDO (MTK_PIN_NO(99) | 7) |
| + |
| +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) |
| +#define PINMUX_GPIO100__FUNC_TDM_DATA1 (MTK_PIN_NO(100) | 1) |
| +#define PINMUX_GPIO100__FUNC_I2S7_DO (MTK_PIN_NO(100) | 2) |
| +#define PINMUX_GPIO100__FUNC_I2S9_DO (MTK_PIN_NO(100) | 3) |
| +#define PINMUX_GPIO100__FUNC_DPI_D4 (MTK_PIN_NO(100) | 4) |
| +#define PINMUX_GPIO100__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(100) | 5) |
| +#define PINMUX_GPIO100__FUNC_IO_JTAG_TMS (MTK_PIN_NO(100) | 7) |
| + |
| +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) |
| +#define PINMUX_GPIO101__FUNC_TDM_DATA2 (MTK_PIN_NO(101) | 1) |
| +#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 2) |
| +#define PINMUX_GPIO101__FUNC_SRCLKENAI0 (MTK_PIN_NO(101) | 3) |
| +#define PINMUX_GPIO101__FUNC_DPI_D5 (MTK_PIN_NO(101) | 4) |
| +#define PINMUX_GPIO101__FUNC_CLKM0 (MTK_PIN_NO(101) | 5) |
| +#define PINMUX_GPIO101__FUNC_DAP_MD32_SWD (MTK_PIN_NO(101) | 7) |
| + |
| +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) |
| +#define PINMUX_GPIO102__FUNC_TDM_DATA3 (MTK_PIN_NO(102) | 1) |
| +#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 2) |
| +#define PINMUX_GPIO102__FUNC_SRCLKENAI1 (MTK_PIN_NO(102) | 3) |
| +#define PINMUX_GPIO102__FUNC_DPI_D6 (MTK_PIN_NO(102) | 4) |
| +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 6) |
| +#define PINMUX_GPIO102__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(102) | 7) |
| + |
| +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) |
| +#define PINMUX_GPIO103__FUNC_SPI0_A_MI (MTK_PIN_NO(103) | 1) |
| +#define PINMUX_GPIO103__FUNC_SCP_SPI0_MI (MTK_PIN_NO(103) | 2) |
| +#define PINMUX_GPIO103__FUNC_DPI_D7 (MTK_PIN_NO(103) | 4) |
| +#define PINMUX_GPIO103__FUNC_DFD_TDO (MTK_PIN_NO(103) | 5) |
| +#define PINMUX_GPIO103__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(103) | 6) |
| +#define PINMUX_GPIO103__FUNC_JTDO_SEL1 (MTK_PIN_NO(103) | 7) |
| + |
| +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) |
| +#define PINMUX_GPIO104__FUNC_SPI0_A_CSB (MTK_PIN_NO(104) | 1) |
| +#define PINMUX_GPIO104__FUNC_SCP_SPI0_CS (MTK_PIN_NO(104) | 2) |
| +#define PINMUX_GPIO104__FUNC_DPI_D8 (MTK_PIN_NO(104) | 4) |
| +#define PINMUX_GPIO104__FUNC_DFD_TMS (MTK_PIN_NO(104) | 5) |
| +#define PINMUX_GPIO104__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(104) | 6) |
| +#define PINMUX_GPIO104__FUNC_JTMS_SEL1 (MTK_PIN_NO(104) | 7) |
| + |
| +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) |
| +#define PINMUX_GPIO105__FUNC_SPI0_A_MO (MTK_PIN_NO(105) | 1) |
| +#define PINMUX_GPIO105__FUNC_SCP_SPI0_MO (MTK_PIN_NO(105) | 2) |
| +#define PINMUX_GPIO105__FUNC_SCP_SDA0 (MTK_PIN_NO(105) | 3) |
| +#define PINMUX_GPIO105__FUNC_DPI_D9 (MTK_PIN_NO(105) | 4) |
| +#define PINMUX_GPIO105__FUNC_DFD_TDI (MTK_PIN_NO(105) | 5) |
| +#define PINMUX_GPIO105__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(105) | 6) |
| +#define PINMUX_GPIO105__FUNC_JTDI_SEL1 (MTK_PIN_NO(105) | 7) |
| + |
| +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) |
| +#define PINMUX_GPIO106__FUNC_SPI0_A_CLK (MTK_PIN_NO(106) | 1) |
| +#define PINMUX_GPIO106__FUNC_SCP_SPI0_CK (MTK_PIN_NO(106) | 2) |
| +#define PINMUX_GPIO106__FUNC_SCP_SCL0 (MTK_PIN_NO(106) | 3) |
| +#define PINMUX_GPIO106__FUNC_DPI_D10 (MTK_PIN_NO(106) | 4) |
| +#define PINMUX_GPIO106__FUNC_DFD_TCK_XI (MTK_PIN_NO(106) | 5) |
| +#define PINMUX_GPIO106__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(106) | 6) |
| +#define PINMUX_GPIO106__FUNC_JTCK_SEL1 (MTK_PIN_NO(106) | 7) |
| + |
| +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) |
| +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) |
| +#define PINMUX_GPIO107__FUNC_PWM_0 (MTK_PIN_NO(107) | 2) |
| +#define PINMUX_GPIO107__FUNC_CLKM2 (MTK_PIN_NO(107) | 3) |
| +#define PINMUX_GPIO107__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(107) | 6) |
| +#define PINMUX_GPIO107__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(107) | 7) |
| + |
| +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) |
| +#define PINMUX_GPIO108__FUNC_DMIC_DAT (MTK_PIN_NO(108) | 1) |
| +#define PINMUX_GPIO108__FUNC_PWM_1 (MTK_PIN_NO(108) | 2) |
| +#define PINMUX_GPIO108__FUNC_CLKM3 (MTK_PIN_NO(108) | 3) |
| +#define PINMUX_GPIO108__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(108) | 7) |
| + |
| +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) |
| +#define PINMUX_GPIO109__FUNC_I2S1_MCK (MTK_PIN_NO(109) | 1) |
| +#define PINMUX_GPIO109__FUNC_I2S3_MCK (MTK_PIN_NO(109) | 2) |
| +#define PINMUX_GPIO109__FUNC_I2S2_MCK (MTK_PIN_NO(109) | 3) |
| +#define PINMUX_GPIO109__FUNC_DPI_DE (MTK_PIN_NO(109) | 4) |
| +#define PINMUX_GPIO109__FUNC_I2S2_MCK_A (MTK_PIN_NO(109) | 5) |
| +#define PINMUX_GPIO109__FUNC_SRCLKENAI0 (MTK_PIN_NO(109) | 6) |
| +#define PINMUX_GPIO109__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(109) | 7) |
| + |
| +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) |
| +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 1) |
| +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 2) |
| +#define PINMUX_GPIO110__FUNC_I2S2_BCK (MTK_PIN_NO(110) | 3) |
| +#define PINMUX_GPIO110__FUNC_DPI_D11 (MTK_PIN_NO(110) | 4) |
| +#define PINMUX_GPIO110__FUNC_I2S2_BCK_A (MTK_PIN_NO(110) | 5) |
| +#define PINMUX_GPIO110__FUNC_CONN_MCU_TDO (MTK_PIN_NO(110) | 6) |
| + |
| +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) |
| +#define PINMUX_GPIO111__FUNC_I2S1_LRCK (MTK_PIN_NO(111) | 1) |
| +#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 2) |
| +#define PINMUX_GPIO111__FUNC_I2S2_LRCK (MTK_PIN_NO(111) | 3) |
| +#define PINMUX_GPIO111__FUNC_DPI_VSYNC (MTK_PIN_NO(111) | 4) |
| +#define PINMUX_GPIO111__FUNC_I2S2_LRCK_A (MTK_PIN_NO(111) | 5) |
| +#define PINMUX_GPIO111__FUNC_CONN_MCU_TDI (MTK_PIN_NO(111) | 6) |
| + |
| +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) |
| +#define PINMUX_GPIO112__FUNC_I2S2_DI (MTK_PIN_NO(112) | 1) |
| +#define PINMUX_GPIO112__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) |
| +#define PINMUX_GPIO112__FUNC_I2S2_DI2 (MTK_PIN_NO(112) | 3) |
| +#define PINMUX_GPIO112__FUNC_DPI_CK (MTK_PIN_NO(112) | 4) |
| +#define PINMUX_GPIO112__FUNC_I2S2_DI_A (MTK_PIN_NO(112) | 5) |
| +#define PINMUX_GPIO112__FUNC_CONN_MCU_TMS (MTK_PIN_NO(112) | 6) |
| + |
| +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) |
| +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 1) |
| +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 2) |
| +#define PINMUX_GPIO113__FUNC_I2S5_DO (MTK_PIN_NO(113) | 3) |
| +#define PINMUX_GPIO113__FUNC_DPI_HSYNC (MTK_PIN_NO(113) | 4) |
| +#define PINMUX_GPIO113__FUNC_I2S2_DI2 (MTK_PIN_NO(113) | 5) |
| +#define PINMUX_GPIO113__FUNC_CONN_MCU_TCK (MTK_PIN_NO(113) | 6) |
| + |
| +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) |
| +#define PINMUX_GPIO114__FUNC_SPI2_MI (MTK_PIN_NO(114) | 1) |
| +#define PINMUX_GPIO114__FUNC_SCP_SPI2_MI (MTK_PIN_NO(114) | 2) |
| +#define PINMUX_GPIO114__FUNC_PCM0_DI (MTK_PIN_NO(114) | 4) |
| +#define PINMUX_GPIO114__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(114) | 6) |
| + |
| +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) |
| +#define PINMUX_GPIO115__FUNC_SPI2_CSB (MTK_PIN_NO(115) | 1) |
| +#define PINMUX_GPIO115__FUNC_SCP_SPI2_CS (MTK_PIN_NO(115) | 2) |
| +#define PINMUX_GPIO115__FUNC_PCM0_SYNC (MTK_PIN_NO(115) | 4) |
| +#define PINMUX_GPIO115__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(115) | 6) |
| + |
| +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) |
| +#define PINMUX_GPIO116__FUNC_SPI2_MO (MTK_PIN_NO(116) | 1) |
| +#define PINMUX_GPIO116__FUNC_SCP_SPI2_MO (MTK_PIN_NO(116) | 2) |
| +#define PINMUX_GPIO116__FUNC_SCP_SDA1 (MTK_PIN_NO(116) | 3) |
| +#define PINMUX_GPIO116__FUNC_PCM0_DO (MTK_PIN_NO(116) | 4) |
| +#define PINMUX_GPIO116__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(116) | 6) |
| + |
| +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) |
| +#define PINMUX_GPIO117__FUNC_SPI2_CLK (MTK_PIN_NO(117) | 1) |
| +#define PINMUX_GPIO117__FUNC_SCP_SPI2_CK (MTK_PIN_NO(117) | 2) |
| +#define PINMUX_GPIO117__FUNC_SCP_SCL1 (MTK_PIN_NO(117) | 3) |
| +#define PINMUX_GPIO117__FUNC_PCM0_CLK (MTK_PIN_NO(117) | 4) |
| + |
| +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) |
| +#define PINMUX_GPIO118__FUNC_SCL1 (MTK_PIN_NO(118) | 1) |
| +#define PINMUX_GPIO118__FUNC_SCP_SCL0 (MTK_PIN_NO(118) | 2) |
| +#define PINMUX_GPIO118__FUNC_SCP_SCL1 (MTK_PIN_NO(118) | 3) |
| + |
| +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) |
| +#define PINMUX_GPIO119__FUNC_SDA1 (MTK_PIN_NO(119) | 1) |
| +#define PINMUX_GPIO119__FUNC_SCP_SDA0 (MTK_PIN_NO(119) | 2) |
| +#define PINMUX_GPIO119__FUNC_SCP_SDA1 (MTK_PIN_NO(119) | 3) |
| + |
| +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) |
| +#define PINMUX_GPIO120__FUNC_SCL9 (MTK_PIN_NO(120) | 1) |
| +#define PINMUX_GPIO120__FUNC_SCP_SCL0 (MTK_PIN_NO(120) | 2) |
| + |
| +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) |
| +#define PINMUX_GPIO121__FUNC_SDA9 (MTK_PIN_NO(121) | 1) |
| +#define PINMUX_GPIO121__FUNC_SCP_SDA0 (MTK_PIN_NO(121) | 2) |
| + |
| +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) |
| +#define PINMUX_GPIO122__FUNC_SCL8 (MTK_PIN_NO(122) | 1) |
| +#define PINMUX_GPIO122__FUNC_SCP_SDA0 (MTK_PIN_NO(122) | 2) |
| + |
| +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) |
| +#define PINMUX_GPIO123__FUNC_SDA8 (MTK_PIN_NO(123) | 1) |
| +#define PINMUX_GPIO123__FUNC_SCP_SCL0 (MTK_PIN_NO(123) | 2) |
| + |
| +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) |
| +#define PINMUX_GPIO124__FUNC_SCL7 (MTK_PIN_NO(124) | 1) |
| +#define PINMUX_GPIO124__FUNC_DMIC1_CLK (MTK_PIN_NO(124) | 2) |
| + |
| +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) |
| +#define PINMUX_GPIO125__FUNC_SDA7 (MTK_PIN_NO(125) | 1) |
| +#define PINMUX_GPIO125__FUNC_DMIC1_DAT (MTK_PIN_NO(125) | 2) |
| + |
| +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) |
| +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 1) |
| +#define PINMUX_GPIO126__FUNC_PWM_2 (MTK_PIN_NO(126) | 2) |
| +#define PINMUX_GPIO126__FUNC_TP_UCTS1_AO (MTK_PIN_NO(126) | 3) |
| +#define PINMUX_GPIO126__FUNC_UCTS0 (MTK_PIN_NO(126) | 4) |
| +#define PINMUX_GPIO126__FUNC_SCL11 (MTK_PIN_NO(126) | 5) |
| +#define PINMUX_GPIO126__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(126) | 6) |
| +#define PINMUX_GPIO126__FUNC_DBG_MON_A14 (MTK_PIN_NO(126) | 7) |
| + |
| +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) |
| +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 1) |
| +#define PINMUX_GPIO127__FUNC_PWM_3 (MTK_PIN_NO(127) | 2) |
| +#define PINMUX_GPIO127__FUNC_TP_URTS1_AO (MTK_PIN_NO(127) | 3) |
| +#define PINMUX_GPIO127__FUNC_URTS0 (MTK_PIN_NO(127) | 4) |
| +#define PINMUX_GPIO127__FUNC_SDA11 (MTK_PIN_NO(127) | 5) |
| +#define PINMUX_GPIO127__FUNC_DBG_MON_A15 (MTK_PIN_NO(127) | 7) |
| + |
| +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) |
| +#define PINMUX_GPIO128__FUNC_CMFLASH2 (MTK_PIN_NO(128) | 1) |
| +#define PINMUX_GPIO128__FUNC_PWM_0 (MTK_PIN_NO(128) | 2) |
| +#define PINMUX_GPIO128__FUNC_TP_UCTS2_AO (MTK_PIN_NO(128) | 3) |
| +#define PINMUX_GPIO128__FUNC_UCTS1 (MTK_PIN_NO(128) | 4) |
| +#define PINMUX_GPIO128__FUNC_SCL_6306 (MTK_PIN_NO(128) | 5) |
| +#define PINMUX_GPIO128__FUNC_DBG_MON_A16 (MTK_PIN_NO(128) | 7) |
| + |
| +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) |
| +#define PINMUX_GPIO129__FUNC_CMFLASH3 (MTK_PIN_NO(129) | 1) |
| +#define PINMUX_GPIO129__FUNC_PWM_1 (MTK_PIN_NO(129) | 2) |
| +#define PINMUX_GPIO129__FUNC_TP_URTS2_AO (MTK_PIN_NO(129) | 3) |
| +#define PINMUX_GPIO129__FUNC_URTS1 (MTK_PIN_NO(129) | 4) |
| +#define PINMUX_GPIO129__FUNC_SDA_6306 (MTK_PIN_NO(129) | 5) |
| +#define PINMUX_GPIO129__FUNC_DBG_MON_A17 (MTK_PIN_NO(129) | 7) |
| + |
| +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) |
| +#define PINMUX_GPIO130__FUNC_CMVREF0 (MTK_PIN_NO(130) | 1) |
| +#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2) |
| +#define PINMUX_GPIO130__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(130) | 3) |
| +#define PINMUX_GPIO130__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(130) | 4) |
| +#define PINMUX_GPIO130__FUNC_SCL11 (MTK_PIN_NO(130) | 5) |
| +#define PINMUX_GPIO130__FUNC_SPI5_B_CLK (MTK_PIN_NO(130) | 6) |
| +#define PINMUX_GPIO130__FUNC_DBG_MON_A22 (MTK_PIN_NO(130) | 7) |
| + |
| +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) |
| +#define PINMUX_GPIO131__FUNC_CMVREF1 (MTK_PIN_NO(131) | 1) |
| +#define PINMUX_GPIO131__FUNC_ANT_SEL11 (MTK_PIN_NO(131) | 2) |
| +#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(131) | 3) |
| +#define PINMUX_GPIO131__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(131) | 4) |
| +#define PINMUX_GPIO131__FUNC_SDA11 (MTK_PIN_NO(131) | 5) |
| +#define PINMUX_GPIO131__FUNC_SPI5_B_MO (MTK_PIN_NO(131) | 6) |
| +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) |
| + |
| +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) |
| +#define PINMUX_GPIO132__FUNC_CMVREF2 (MTK_PIN_NO(132) | 1) |
| +#define PINMUX_GPIO132__FUNC_ANT_SEL12 (MTK_PIN_NO(132) | 2) |
| +#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(132) | 3) |
| +#define PINMUX_GPIO132__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(132) | 4) |
| +#define PINMUX_GPIO132__FUNC_DBG_MON_A28 (MTK_PIN_NO(132) | 7) |
| + |
| +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) |
| +#define PINMUX_GPIO133__FUNC_CMVREF3 (MTK_PIN_NO(133) | 1) |
| +#define PINMUX_GPIO133__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(133) | 2) |
| +#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(133) | 3) |
| +#define PINMUX_GPIO133__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(133) | 4) |
| +#define PINMUX_GPIO133__FUNC_SPI5_B_CSB (MTK_PIN_NO(133) | 6) |
| +#define PINMUX_GPIO133__FUNC_DBG_MON_A23 (MTK_PIN_NO(133) | 7) |
| + |
| +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) |
| +#define PINMUX_GPIO134__FUNC_CMVREF4 (MTK_PIN_NO(134) | 1) |
| +#define PINMUX_GPIO134__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(134) | 3) |
| +#define PINMUX_GPIO134__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(134) | 4) |
| +#define PINMUX_GPIO134__FUNC_DBG_MON_A26 (MTK_PIN_NO(134) | 7) |
| + |
| +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) |
| +#define PINMUX_GPIO135__FUNC_PWM_0 (MTK_PIN_NO(135) | 1) |
| +#define PINMUX_GPIO135__FUNC_SRCLKENAI1 (MTK_PIN_NO(135) | 2) |
| +#define PINMUX_GPIO135__FUNC_MD_URXD0 (MTK_PIN_NO(135) | 3) |
| +#define PINMUX_GPIO135__FUNC_MD32_0_RXD (MTK_PIN_NO(135) | 4) |
| +#define PINMUX_GPIO135__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(135) | 5) |
| +#define PINMUX_GPIO135__FUNC_DBG_MON_A29 (MTK_PIN_NO(135) | 7) |
| + |
| +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) |
| +#define PINMUX_GPIO136__FUNC_CMMCLK3 (MTK_PIN_NO(136) | 1) |
| +#define PINMUX_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 2) |
| +#define PINMUX_GPIO136__FUNC_MD_UTXD0 (MTK_PIN_NO(136) | 3) |
| +#define PINMUX_GPIO136__FUNC_MD32_0_TXD (MTK_PIN_NO(136) | 4) |
| +#define PINMUX_GPIO136__FUNC_SPI5_B_MI (MTK_PIN_NO(136) | 6) |
| +#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) |
| + |
| +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) |
| +#define PINMUX_GPIO137__FUNC_CMMCLK4 (MTK_PIN_NO(137) | 1) |
| +#define PINMUX_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 2) |
| +#define PINMUX_GPIO137__FUNC_MD_URXD1 (MTK_PIN_NO(137) | 3) |
| +#define PINMUX_GPIO137__FUNC_CONN_UART0_RXD (MTK_PIN_NO(137) | 6) |
| +#define PINMUX_GPIO137__FUNC_DBG_MON_A27 (MTK_PIN_NO(137) | 7) |
| + |
| +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) |
| +#define PINMUX_GPIO138__FUNC_CMMCLK5 (MTK_PIN_NO(138) | 1) |
| +#define PINMUX_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 2) |
| +#define PINMUX_GPIO138__FUNC_MD_UTXD1 (MTK_PIN_NO(138) | 3) |
| +#define PINMUX_GPIO138__FUNC_CONN_UART0_TXD (MTK_PIN_NO(138) | 6) |
| +#define PINMUX_GPIO138__FUNC_DBG_MON_A30 (MTK_PIN_NO(138) | 7) |
| + |
| +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) |
| +#define PINMUX_GPIO139__FUNC_SCL4 (MTK_PIN_NO(139) | 1) |
| +#define PINMUX_GPIO139__FUNC_DBG_MON_A21 (MTK_PIN_NO(139) | 7) |
| + |
| +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) |
| +#define PINMUX_GPIO140__FUNC_SDA4 (MTK_PIN_NO(140) | 1) |
| +#define PINMUX_GPIO140__FUNC_DBG_MON_A20 (MTK_PIN_NO(140) | 7) |
| + |
| +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) |
| +#define PINMUX_GPIO141__FUNC_SCL2 (MTK_PIN_NO(141) | 1) |
| +#define PINMUX_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) |
| + |
| +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) |
| +#define PINMUX_GPIO142__FUNC_SDA2 (MTK_PIN_NO(142) | 1) |
| +#define PINMUX_GPIO142__FUNC_DBG_MON_A19 (MTK_PIN_NO(142) | 7) |
| + |
| +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) |
| +#define PINMUX_GPIO143__FUNC_CMVREF0 (MTK_PIN_NO(143) | 1) |
| +#define PINMUX_GPIO143__FUNC_SPI3_CLK (MTK_PIN_NO(143) | 2) |
| +#define PINMUX_GPIO143__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(143) | 3) |
| +#define PINMUX_GPIO143__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(143) | 4) |
| +#define PINMUX_GPIO143__FUNC_DBG_MON_A31 (MTK_PIN_NO(143) | 7) |
| + |
| +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) |
| +#define PINMUX_GPIO144__FUNC_CMVREF1 (MTK_PIN_NO(144) | 1) |
| +#define PINMUX_GPIO144__FUNC_SPI3_CSB (MTK_PIN_NO(144) | 2) |
| +#define PINMUX_GPIO144__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(144) | 3) |
| +#define PINMUX_GPIO144__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(144) | 4) |
| + |
| +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) |
| +#define PINMUX_GPIO145__FUNC_CMVREF2 (MTK_PIN_NO(145) | 1) |
| +#define PINMUX_GPIO145__FUNC_SPI3_MI (MTK_PIN_NO(145) | 2) |
| +#define PINMUX_GPIO145__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(145) | 3) |
| +#define PINMUX_GPIO145__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(145) | 4) |
| + |
| +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) |
| +#define PINMUX_GPIO146__FUNC_CMVREF3 (MTK_PIN_NO(146) | 1) |
| +#define PINMUX_GPIO146__FUNC_SPI3_MO (MTK_PIN_NO(146) | 2) |
| +#define PINMUX_GPIO146__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(146) | 3) |
| +#define PINMUX_GPIO146__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(146) | 4) |
| +#define PINMUX_GPIO146__FUNC_DBG_MON_A32 (MTK_PIN_NO(146) | 7) |
| + |
| +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) |
| +#define PINMUX_GPIO147__FUNC_CMVREF4 (MTK_PIN_NO(147) | 1) |
| +#define PINMUX_GPIO147__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(147) | 2) |
| +#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(147) | 3) |
| +#define PINMUX_GPIO147__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(147) | 4) |
| + |
| +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) |
| +#define PINMUX_GPIO148__FUNC_PWM_1 (MTK_PIN_NO(148) | 1) |
| +#define PINMUX_GPIO148__FUNC_AGPS_SYNC (MTK_PIN_NO(148) | 2) |
| +#define PINMUX_GPIO148__FUNC_CMMCLK5 (MTK_PIN_NO(148) | 3) |
| + |
| +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) |
| +#define PINMUX_GPIO149__FUNC_CMMCLK0 (MTK_PIN_NO(149) | 1) |
| +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) |
| +#define PINMUX_GPIO149__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(149) | 3) |
| + |
| +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) |
| +#define PINMUX_GPIO150__FUNC_CMMCLK1 (MTK_PIN_NO(150) | 1) |
| +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) |
| +#define PINMUX_GPIO150__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(150) | 3) |
| +#define PINMUX_GPIO150__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(150) | 7) |
| + |
| +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) |
| +#define PINMUX_GPIO151__FUNC_CMMCLK2 (MTK_PIN_NO(151) | 1) |
| +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) |
| +#define PINMUX_GPIO151__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(151) | 3) |
| +#define PINMUX_GPIO151__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(151) | 7) |
| + |
| +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) |
| +#define PINMUX_GPIO152__FUNC_KPROW1 (MTK_PIN_NO(152) | 1) |
| +#define PINMUX_GPIO152__FUNC_PWM_2 (MTK_PIN_NO(152) | 2) |
| +#define PINMUX_GPIO152__FUNC_IDDIG (MTK_PIN_NO(152) | 3) |
| +#define PINMUX_GPIO152__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(152) | 6) |
| +#define PINMUX_GPIO152__FUNC_DBG_MON_B9 (MTK_PIN_NO(152) | 7) |
| + |
| +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) |
| +#define PINMUX_GPIO153__FUNC_KPROW0 (MTK_PIN_NO(153) | 1) |
| +#define PINMUX_GPIO153__FUNC_DBG_MON_B8 (MTK_PIN_NO(153) | 7) |
| + |
| +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) |
| +#define PINMUX_GPIO154__FUNC_KPCOL0 (MTK_PIN_NO(154) | 1) |
| +#define PINMUX_GPIO154__FUNC_DBG_MON_B6 (MTK_PIN_NO(154) | 7) |
| + |
| +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) |
| +#define PINMUX_GPIO155__FUNC_KPCOL1 (MTK_PIN_NO(155) | 1) |
| +#define PINMUX_GPIO155__FUNC_PWM_3 (MTK_PIN_NO(155) | 2) |
| +#define PINMUX_GPIO155__FUNC_USB_DRVVBUS (MTK_PIN_NO(155) | 3) |
| +#define PINMUX_GPIO155__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(155) | 4) |
| +#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 6) |
| +#define PINMUX_GPIO155__FUNC_DBG_MON_B7 (MTK_PIN_NO(155) | 7) |
| + |
| +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) |
| +#define PINMUX_GPIO156__FUNC_SPI1_A_CLK (MTK_PIN_NO(156) | 1) |
| +#define PINMUX_GPIO156__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(156) | 2) |
| +#define PINMUX_GPIO156__FUNC_MRG_CLK (MTK_PIN_NO(156) | 3) |
| +#define PINMUX_GPIO156__FUNC_AGPS_SYNC (MTK_PIN_NO(156) | 4) |
| +#define PINMUX_GPIO156__FUNC_MD_URXD0 (MTK_PIN_NO(156) | 5) |
| +#define PINMUX_GPIO156__FUNC_UDI_TMS (MTK_PIN_NO(156) | 6) |
| +#define PINMUX_GPIO156__FUNC_DBG_MON_B10 (MTK_PIN_NO(156) | 7) |
| + |
| +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) |
| +#define PINMUX_GPIO157__FUNC_SPI1_A_CSB (MTK_PIN_NO(157) | 1) |
| +#define PINMUX_GPIO157__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(157) | 2) |
| +#define PINMUX_GPIO157__FUNC_MRG_SYNC (MTK_PIN_NO(157) | 3) |
| +#define PINMUX_GPIO157__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(157) | 4) |
| +#define PINMUX_GPIO157__FUNC_MD_UTXD0 (MTK_PIN_NO(157) | 5) |
| +#define PINMUX_GPIO157__FUNC_UDI_TCK (MTK_PIN_NO(157) | 6) |
| +#define PINMUX_GPIO157__FUNC_DBG_MON_B11 (MTK_PIN_NO(157) | 7) |
| + |
| +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) |
| +#define PINMUX_GPIO158__FUNC_SPI1_A_MI (MTK_PIN_NO(158) | 1) |
| +#define PINMUX_GPIO158__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(158) | 2) |
| +#define PINMUX_GPIO158__FUNC_MRG_DI (MTK_PIN_NO(158) | 3) |
| +#define PINMUX_GPIO158__FUNC_PTA_RXD (MTK_PIN_NO(158) | 4) |
| +#define PINMUX_GPIO158__FUNC_MD_URXD1 (MTK_PIN_NO(158) | 5) |
| +#define PINMUX_GPIO158__FUNC_UDI_TDO (MTK_PIN_NO(158) | 6) |
| +#define PINMUX_GPIO158__FUNC_DBG_MON_B12 (MTK_PIN_NO(158) | 7) |
| + |
| +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) |
| +#define PINMUX_GPIO159__FUNC_SPI1_A_MO (MTK_PIN_NO(159) | 1) |
| +#define PINMUX_GPIO159__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(159) | 2) |
| +#define PINMUX_GPIO159__FUNC_MRG_DO (MTK_PIN_NO(159) | 3) |
| +#define PINMUX_GPIO159__FUNC_PTA_TXD (MTK_PIN_NO(159) | 4) |
| +#define PINMUX_GPIO159__FUNC_MD_UTXD1 (MTK_PIN_NO(159) | 5) |
| +#define PINMUX_GPIO159__FUNC_UDI_NTRST (MTK_PIN_NO(159) | 6) |
| +#define PINMUX_GPIO159__FUNC_DBG_MON_B13 (MTK_PIN_NO(159) | 7) |
| + |
| +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) |
| +#define PINMUX_GPIO160__FUNC_SCL3 (MTK_PIN_NO(160) | 1) |
| +#define PINMUX_GPIO160__FUNC_SCP_SCL1 (MTK_PIN_NO(160) | 3) |
| +#define PINMUX_GPIO160__FUNC_DBG_MON_B14 (MTK_PIN_NO(160) | 7) |
| + |
| +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) |
| +#define PINMUX_GPIO161__FUNC_SDA3 (MTK_PIN_NO(161) | 1) |
| +#define PINMUX_GPIO161__FUNC_SCP_SDA1 (MTK_PIN_NO(161) | 3) |
| +#define PINMUX_GPIO161__FUNC_DBG_MON_B15 (MTK_PIN_NO(161) | 7) |
| + |
| +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) |
| +#define PINMUX_GPIO162__FUNC_ANT_SEL0 (MTK_PIN_NO(162) | 1) |
| +#define PINMUX_GPIO162__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(162) | 2) |
| +#define PINMUX_GPIO162__FUNC_UDI_TDI (MTK_PIN_NO(162) | 6) |
| +#define PINMUX_GPIO162__FUNC_DBG_MON_B16 (MTK_PIN_NO(162) | 7) |
| + |
| +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) |
| +#define PINMUX_GPIO163__FUNC_ANT_SEL1 (MTK_PIN_NO(163) | 1) |
| +#define PINMUX_GPIO163__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(163) | 2) |
| +#define PINMUX_GPIO163__FUNC_DBG_MON_B17 (MTK_PIN_NO(163) | 7) |
| + |
| +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) |
| +#define PINMUX_GPIO164__FUNC_ANT_SEL2 (MTK_PIN_NO(164) | 1) |
| +#define PINMUX_GPIO164__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(164) | 2) |
| +#define PINMUX_GPIO164__FUNC_TP_URXD1_AO (MTK_PIN_NO(164) | 3) |
| +#define PINMUX_GPIO164__FUNC_UCTS0 (MTK_PIN_NO(164) | 5) |
| +#define PINMUX_GPIO164__FUNC_DBG_MON_B18 (MTK_PIN_NO(164) | 7) |
| + |
| +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) |
| +#define PINMUX_GPIO165__FUNC_ANT_SEL3 (MTK_PIN_NO(165) | 1) |
| +#define PINMUX_GPIO165__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(165) | 2) |
| +#define PINMUX_GPIO165__FUNC_TP_UTXD1_AO (MTK_PIN_NO(165) | 3) |
| +#define PINMUX_GPIO165__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(165) | 4) |
| +#define PINMUX_GPIO165__FUNC_URTS0 (MTK_PIN_NO(165) | 5) |
| +#define PINMUX_GPIO165__FUNC_DBG_MON_B19 (MTK_PIN_NO(165) | 7) |
| + |
| +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) |
| +#define PINMUX_GPIO166__FUNC_ANT_SEL4 (MTK_PIN_NO(166) | 1) |
| +#define PINMUX_GPIO166__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(166) | 2) |
| +#define PINMUX_GPIO166__FUNC_TP_URXD2_AO (MTK_PIN_NO(166) | 3) |
| +#define PINMUX_GPIO166__FUNC_SRCLKENAI1 (MTK_PIN_NO(166) | 4) |
| +#define PINMUX_GPIO166__FUNC_UCTS1 (MTK_PIN_NO(166) | 5) |
| +#define PINMUX_GPIO166__FUNC_DBG_MON_B20 (MTK_PIN_NO(166) | 7) |
| + |
| +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) |
| +#define PINMUX_GPIO167__FUNC_ANT_SEL5 (MTK_PIN_NO(167) | 1) |
| +#define PINMUX_GPIO167__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(167) | 2) |
| +#define PINMUX_GPIO167__FUNC_TP_UTXD2_AO (MTK_PIN_NO(167) | 3) |
| +#define PINMUX_GPIO167__FUNC_SRCLKENAI0 (MTK_PIN_NO(167) | 4) |
| +#define PINMUX_GPIO167__FUNC_URTS1 (MTK_PIN_NO(167) | 5) |
| +#define PINMUX_GPIO167__FUNC_DBG_MON_B21 (MTK_PIN_NO(167) | 7) |
| + |
| +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) |
| +#define PINMUX_GPIO168__FUNC_ANT_SEL6 (MTK_PIN_NO(168) | 1) |
| +#define PINMUX_GPIO168__FUNC_SPI0_B_CLK (MTK_PIN_NO(168) | 2) |
| +#define PINMUX_GPIO168__FUNC_TP_UCTS1_AO (MTK_PIN_NO(168) | 3) |
| +#define PINMUX_GPIO168__FUNC_KPCOL2 (MTK_PIN_NO(168) | 4) |
| +#define PINMUX_GPIO168__FUNC_MD_UCTS0 (MTK_PIN_NO(168) | 5) |
| +#define PINMUX_GPIO168__FUNC_SCL11 (MTK_PIN_NO(168) | 6) |
| +#define PINMUX_GPIO168__FUNC_DBG_MON_B22 (MTK_PIN_NO(168) | 7) |
| + |
| +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) |
| +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 1) |
| +#define PINMUX_GPIO169__FUNC_SPI0_B_CSB (MTK_PIN_NO(169) | 2) |
| +#define PINMUX_GPIO169__FUNC_TP_URTS1_AO (MTK_PIN_NO(169) | 3) |
| +#define PINMUX_GPIO169__FUNC_KPROW2 (MTK_PIN_NO(169) | 4) |
| +#define PINMUX_GPIO169__FUNC_MD_URTS0 (MTK_PIN_NO(169) | 5) |
| +#define PINMUX_GPIO169__FUNC_SDA11 (MTK_PIN_NO(169) | 6) |
| +#define PINMUX_GPIO169__FUNC_DBG_MON_B23 (MTK_PIN_NO(169) | 7) |
| + |
| +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) |
| +#define PINMUX_GPIO170__FUNC_ANT_SEL8 (MTK_PIN_NO(170) | 1) |
| +#define PINMUX_GPIO170__FUNC_SPI0_B_MI (MTK_PIN_NO(170) | 2) |
| +#define PINMUX_GPIO170__FUNC_TP_UCTS2_AO (MTK_PIN_NO(170) | 3) |
| +#define PINMUX_GPIO170__FUNC_SRCLKENAI1 (MTK_PIN_NO(170) | 4) |
| +#define PINMUX_GPIO170__FUNC_MD_UCTS1 (MTK_PIN_NO(170) | 5) |
| +#define PINMUX_GPIO170__FUNC_DBG_MON_B24 (MTK_PIN_NO(170) | 7) |
| + |
| +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) |
| +#define PINMUX_GPIO171__FUNC_ANT_SEL9 (MTK_PIN_NO(171) | 1) |
| +#define PINMUX_GPIO171__FUNC_SPI0_B_MO (MTK_PIN_NO(171) | 2) |
| +#define PINMUX_GPIO171__FUNC_TP_URTS2_AO (MTK_PIN_NO(171) | 3) |
| +#define PINMUX_GPIO171__FUNC_SRCLKENAI0 (MTK_PIN_NO(171) | 4) |
| +#define PINMUX_GPIO171__FUNC_MD_URTS1 (MTK_PIN_NO(171) | 5) |
| +#define PINMUX_GPIO171__FUNC_DBG_MON_B25 (MTK_PIN_NO(171) | 7) |
| + |
| +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) |
| +#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1) |
| +#define PINMUX_GPIO172__FUNC_AUXIF_CLK0 (MTK_PIN_NO(172) | 2) |
| +#define PINMUX_GPIO172__FUNC_DBG_MON_B29 (MTK_PIN_NO(172) | 7) |
| + |
| +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) |
| +#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1) |
| +#define PINMUX_GPIO173__FUNC_AUXIF_ST0 (MTK_PIN_NO(173) | 2) |
| +#define PINMUX_GPIO173__FUNC_DBG_MON_B30 (MTK_PIN_NO(173) | 7) |
| + |
| +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) |
| +#define PINMUX_GPIO174__FUNC_CONN_HRST_B (MTK_PIN_NO(174) | 1) |
| +#define PINMUX_GPIO174__FUNC_DBG_MON_B28 (MTK_PIN_NO(174) | 7) |
| + |
| +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) |
| +#define PINMUX_GPIO175__FUNC_CONN_WB_PTA (MTK_PIN_NO(175) | 1) |
| +#define PINMUX_GPIO175__FUNC_DBG_MON_B31 (MTK_PIN_NO(175) | 7) |
| + |
| +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) |
| +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) |
| +#define PINMUX_GPIO176__FUNC_AUXIF_CLK1 (MTK_PIN_NO(176) | 2) |
| +#define PINMUX_GPIO176__FUNC_DBG_MON_B26 (MTK_PIN_NO(176) | 7) |
| + |
| +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) |
| +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) |
| +#define PINMUX_GPIO177__FUNC_AUXIF_ST1 (MTK_PIN_NO(177) | 2) |
| +#define PINMUX_GPIO177__FUNC_DBG_MON_B27 (MTK_PIN_NO(177) | 7) |
| + |
| +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) |
| +#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1) |
| + |
| +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) |
| +#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1) |
| +#define PINMUX_GPIO179__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(179) | 2) |
| + |
| +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) |
| +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1) |
| +#define PINMUX_GPIO180__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(180) | 2) |
| + |
| +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) |
| +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1) |
| + |
| +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) |
| +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1) |
| + |
| +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) |
| +#define PINMUX_GPIO183__FUNC_MSDC0_CMD (MTK_PIN_NO(183) | 1) |
| + |
| +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) |
| +#define PINMUX_GPIO184__FUNC_MSDC0_DAT0 (MTK_PIN_NO(184) | 1) |
| + |
| +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) |
| +#define PINMUX_GPIO185__FUNC_MSDC0_DAT2 (MTK_PIN_NO(185) | 1) |
| + |
| +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) |
| +#define PINMUX_GPIO186__FUNC_MSDC0_DAT4 (MTK_PIN_NO(186) | 1) |
| + |
| +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) |
| +#define PINMUX_GPIO187__FUNC_MSDC0_DAT6 (MTK_PIN_NO(187) | 1) |
| + |
| +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) |
| +#define PINMUX_GPIO188__FUNC_MSDC0_DAT1 (MTK_PIN_NO(188) | 1) |
| + |
| +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) |
| +#define PINMUX_GPIO189__FUNC_MSDC0_DAT5 (MTK_PIN_NO(189) | 1) |
| + |
| +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) |
| +#define PINMUX_GPIO190__FUNC_MSDC0_DAT7 (MTK_PIN_NO(190) | 1) |
| + |
| +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) |
| +#define PINMUX_GPIO191__FUNC_MSDC0_DSL (MTK_PIN_NO(191) | 1) |
| +#define PINMUX_GPIO191__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(191) | 2) |
| +#define PINMUX_GPIO191__FUNC_IDDIG (MTK_PIN_NO(191) | 3) |
| +#define PINMUX_GPIO191__FUNC_DMIC_CLK (MTK_PIN_NO(191) | 4) |
| + |
| +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) |
| +#define PINMUX_GPIO192__FUNC_MSDC0_CLK (MTK_PIN_NO(192) | 1) |
| +#define PINMUX_GPIO192__FUNC_USB_DRVVBUS (MTK_PIN_NO(192) | 3) |
| +#define PINMUX_GPIO192__FUNC_DMIC_DAT (MTK_PIN_NO(192) | 4) |
| + |
| +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) |
| +#define PINMUX_GPIO193__FUNC_MSDC0_DAT3 (MTK_PIN_NO(193) | 1) |
| + |
| +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) |
| +#define PINMUX_GPIO194__FUNC_MSDC0_RSTB (MTK_PIN_NO(194) | 1) |
| + |
| +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) |
| +#define PINMUX_GPIO195__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(195) | 1) |
| +#define PINMUX_GPIO195__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(195) | 2) |
| + |
| +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) |
| +#define PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(196) | 1) |
| + |
| +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) |
| +#define PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(197) | 1) |
| +#define PINMUX_GPIO197__FUNC_AUD_CLK_MISO (MTK_PIN_NO(197) | 2) |
| +#define PINMUX_GPIO197__FUNC_I2S2_MCK (MTK_PIN_NO(197) | 3) |
| +#define PINMUX_GPIO197__FUNC_I2S6_MCK (MTK_PIN_NO(197) | 4) |
| +#define PINMUX_GPIO197__FUNC_I2S8_MCK (MTK_PIN_NO(197) | 5) |
| + |
| +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) |
| +#define PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(198) | 1) |
| +#define PINMUX_GPIO198__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(198) | 2) |
| +#define PINMUX_GPIO198__FUNC_I2S2_BCK (MTK_PIN_NO(198) | 3) |
| +#define PINMUX_GPIO198__FUNC_I2S6_BCK (MTK_PIN_NO(198) | 4) |
| +#define PINMUX_GPIO198__FUNC_I2S8_BCK (MTK_PIN_NO(198) | 5) |
| + |
| +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) |
| +#define PINMUX_GPIO199__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(199) | 1) |
| +#define PINMUX_GPIO199__FUNC_I2S2_DI2 (MTK_PIN_NO(199) | 3) |
| + |
| +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) |
| +#define PINMUX_GPIO200__FUNC_SCL6 (MTK_PIN_NO(200) | 1) |
| +#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 3) |
| +#define PINMUX_GPIO200__FUNC_SCL_6306 (MTK_PIN_NO(200) | 4) |
| +#define PINMUX_GPIO200__FUNC_DBG_MON_A4 (MTK_PIN_NO(200) | 7) |
| + |
| +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) |
| +#define PINMUX_GPIO201__FUNC_SDA6 (MTK_PIN_NO(201) | 1) |
| +#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 3) |
| +#define PINMUX_GPIO201__FUNC_SDA_6306 (MTK_PIN_NO(201) | 4) |
| +#define PINMUX_GPIO201__FUNC_DBG_MON_A5 (MTK_PIN_NO(201) | 7) |
| + |
| +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) |
| +#define PINMUX_GPIO202__FUNC_SCL5 (MTK_PIN_NO(202) | 1) |
| + |
| +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) |
| +#define PINMUX_GPIO203__FUNC_SDA5 (MTK_PIN_NO(203) | 1) |
| + |
| +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) |
| +#define PINMUX_GPIO204__FUNC_SCL0 (MTK_PIN_NO(204) | 1) |
| +#define PINMUX_GPIO204__FUNC_SPI7_A_CLK (MTK_PIN_NO(204) | 6) |
| +#define PINMUX_GPIO204__FUNC_DBG_MON_A2 (MTK_PIN_NO(204) | 7) |
| + |
| +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) |
| +#define PINMUX_GPIO205__FUNC_SDA0 (MTK_PIN_NO(205) | 1) |
| +#define PINMUX_GPIO205__FUNC_SPI7_A_CSB (MTK_PIN_NO(205) | 6) |
| +#define PINMUX_GPIO205__FUNC_DBG_MON_A3 (MTK_PIN_NO(205) | 7) |
| + |
| +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) |
| +#define PINMUX_GPIO206__FUNC_SRCLKENA0 (MTK_PIN_NO(206) | 1) |
| + |
| +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) |
| +#define PINMUX_GPIO207__FUNC_SRCLKENA1 (MTK_PIN_NO(207) | 1) |
| + |
| +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) |
| +#define PINMUX_GPIO208__FUNC_WATCHDOG (MTK_PIN_NO(208) | 1) |
| + |
| +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) |
| +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(209) | 1) |
| +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(209) | 2) |
| + |
| +#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) |
| +#define PINMUX_GPIO210__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(210) | 1) |
| + |
| +#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) |
| +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(211) | 1) |
| +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(211) | 2) |
| + |
| +#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) |
| +#define PINMUX_GPIO212__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(212) | 1) |
| + |
| +#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) |
| +#define PINMUX_GPIO213__FUNC_RTC32K_CK (MTK_PIN_NO(213) | 1) |
| + |
| +#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) |
| +#define PINMUX_GPIO214__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(214) | 1) |
| +#define PINMUX_GPIO214__FUNC_I2S1_MCK (MTK_PIN_NO(214) | 3) |
| +#define PINMUX_GPIO214__FUNC_I2S7_MCK (MTK_PIN_NO(214) | 4) |
| +#define PINMUX_GPIO214__FUNC_I2S9_MCK (MTK_PIN_NO(214) | 5) |
| + |
| +#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) |
| +#define PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(215) | 1) |
| +#define PINMUX_GPIO215__FUNC_I2S1_BCK (MTK_PIN_NO(215) | 3) |
| +#define PINMUX_GPIO215__FUNC_I2S7_BCK (MTK_PIN_NO(215) | 4) |
| +#define PINMUX_GPIO215__FUNC_I2S9_BCK (MTK_PIN_NO(215) | 5) |
| + |
| +#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) |
| +#define PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(216) | 1) |
| +#define PINMUX_GPIO216__FUNC_I2S1_LRCK (MTK_PIN_NO(216) | 3) |
| +#define PINMUX_GPIO216__FUNC_I2S7_LRCK (MTK_PIN_NO(216) | 4) |
| +#define PINMUX_GPIO216__FUNC_I2S9_LRCK (MTK_PIN_NO(216) | 5) |
| + |
| +#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) |
| +#define PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(217) | 1) |
| +#define PINMUX_GPIO217__FUNC_I2S1_DO (MTK_PIN_NO(217) | 3) |
| +#define PINMUX_GPIO217__FUNC_I2S7_DO (MTK_PIN_NO(217) | 4) |
| +#define PINMUX_GPIO217__FUNC_I2S9_DO (MTK_PIN_NO(217) | 5) |
| + |
| +#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) |
| +#define PINMUX_GPIO218__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(218) | 1) |
| +#define PINMUX_GPIO218__FUNC_VOW_DAT_MISO (MTK_PIN_NO(218) | 2) |
| +#define PINMUX_GPIO218__FUNC_I2S2_LRCK (MTK_PIN_NO(218) | 3) |
| +#define PINMUX_GPIO218__FUNC_I2S6_LRCK (MTK_PIN_NO(218) | 4) |
| +#define PINMUX_GPIO218__FUNC_I2S8_LRCK (MTK_PIN_NO(218) | 5) |
| + |
| +#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) |
| +#define PINMUX_GPIO219__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(219) | 1) |
| +#define PINMUX_GPIO219__FUNC_VOW_CLK_MISO (MTK_PIN_NO(219) | 2) |
| +#define PINMUX_GPIO219__FUNC_I2S2_DI (MTK_PIN_NO(219) | 3) |
| +#define PINMUX_GPIO219__FUNC_I2S6_DI (MTK_PIN_NO(219) | 4) |
| +#define PINMUX_GPIO219__FUNC_I2S8_DI (MTK_PIN_NO(219) | 5) |
| + |
| +#endif /* __MT6873_PINFUNC_H */ |
| diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..14e4508eb4cfc44350b376d4356713441cfb5821 |
| --- /dev/null |
| +++ b/include/dt-bindings/power/mt8192-power.h |
| @@ -0,0 +1,34 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 |
| + * |
| + * Copyright (c) 2020 MediaTek Inc. |
| + * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| + */ |
| + |
| +#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H |
| +#define _DT_BINDINGS_POWER_MT8192_POWER_H |
| + |
| +#define MT8192_POWER_DOMAIN_CONN 0 |
| +#define MT8192_POWER_DOMAIN_MFG0 1 |
| +#define MT8192_POWER_DOMAIN_MFG1 2 |
| +#define MT8192_POWER_DOMAIN_MFG2 3 |
| +#define MT8192_POWER_DOMAIN_MFG3 4 |
| +#define MT8192_POWER_DOMAIN_MFG4 5 |
| +#define MT8192_POWER_DOMAIN_MFG5 6 |
| +#define MT8192_POWER_DOMAIN_MFG6 7 |
| +#define MT8192_POWER_DOMAIN_DISP 8 |
| +#define MT8192_POWER_DOMAIN_ISP 9 |
| +#define MT8192_POWER_DOMAIN_ISP2 10 |
| +#define MT8192_POWER_DOMAIN_IPE 11 |
| +#define MT8192_POWER_DOMAIN_VDEC 12 |
| +#define MT8192_POWER_DOMAIN_VDEC2 13 |
| +#define MT8192_POWER_DOMAIN_VENC 14 |
| +#define MT8192_POWER_DOMAIN_MDP 15 |
| +#define MT8192_POWER_DOMAIN_AUDIO 16 |
| +#define MT8192_POWER_DOMAIN_ADSP 17 |
| +#define MT8192_POWER_DOMAIN_CAM 18 |
| +#define MT8192_POWER_DOMAIN_CAM_RAWA 19 |
| +#define MT8192_POWER_DOMAIN_CAM_RAWB 20 |
| +#define MT8192_POWER_DOMAIN_CAM_RAWC 21 |
| +#define MT8192_POWER_DOMAIN_MSDC 22 |
| + |
| +#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ |
| diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h |
| new file mode 100755 |
| index 0000000000000000000000000000000000000000..d7e13c40f2f575efcf4b23065ef55b41e4d6bdf6 |
| --- /dev/null |
| +++ b/include/dt-bindings/reset-controller/mt8192-resets.h |
| @@ -0,0 +1,91 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + * Author: Yong Liang <yong.liang@mediatek.com> |
| + */ |
| + |
| +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
| +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
| + |
| +/* INFRACFG AO resets */ |
| +#define MT8192_INFRACFG_AO_THERM_CTRL_SW_RST 0 |
| +#define MT8192_INFRACFG_AO_USB_TOP_SW_RST 1 |
| +#define MT8192_INFRACFG_AO_AP_MD_CCIF_SW_RST 2 |
| +#define MT8192_INFRACFG_AO_MM_IOMMU_SW_RST 3 |
| +#define MT8192_INFRACFG_AO_MSDC3_SW_RST 4 |
| +#define MT8192_INFRACFG_AO_MSDC2_SW_RST 5 |
| +#define MT8192_INFRACFG_AO_MSDC1_SW_RST 6 |
| +#define MT8192_INFRACFG_AO_MSDC0_SW_RST 7 |
| +#define MT8192_INFRACFG_AO_APDMA_SW_RST 9 |
| +#define MT8192_INFRACFG_AO_MIMP_D_SW_RST 10 |
| +#define MT8192_INFRACFG_AO_MIMP_C_SW_RST 11 |
| +#define MT8192_INFRACFG_AO_BTIF_SW_RST 12 |
| +#define MT8192_INFRACFG_AO_SSUSB_TOP_SW_RST 13 |
| +#define MT8192_INFRACFG_AO_DISP_PWM_SW_RST 14 |
| +#define MT8192_INFRACFG_AO_AUXADC_SW_RST 15 |
| + |
| +#define MT8192_INFRACFG_AO_IRTX_SW_RST 32 |
| +#define MT8192_INFRACFG_AO_SPI0_SW_RST 33 |
| +#define MT8192_INFRACFG_AO_I2C0_SW_RST 34 |
| +#define MT8192_INFRACFG_AO_I2C1_SW_RST 35 |
| +#define MT8192_INFRACFG_AO_I2C2_SW_RST 36 |
| +#define MT8192_INFRACFG_AO_I2C3_SW_RST 37 |
| +#define MT8192_INFRACFG_AO_UART0_SW_RST 38 |
| +#define MT8192_INFRACFG_AO_UART1_SW_RST 39 |
| +#define MT8192_INFRACFG_AO_UART2_SW_RST 40 |
| +#define MT8192_INFRACFG_AO_PWM_SW_RST 41 |
| +#define MT8192_INFRACFG_AO_SPI1_SW_RST 42 |
| +#define MT8192_INFRACFG_AO_I2C4_SW_RST 43 |
| +#define MT8192_INFRACFG_AO_DVFSP_SW_RST 44 |
| +#define MT8192_INFRACFG_AO_SPI2_SW_RST 45 |
| +#define MT8192_INFRACFG_AO_SPI3_SW_RST 46 |
| +#define MT8192_INFRACFG_AO_UFSHCI_SW_RST 47 |
| + |
| +#define MT8192_INFRACFG_AO_PMIC_WRAP_SW_RST 64 |
| +#define MT8192_INFRACFG_AO_SPM_SW_RST 65 |
| +#define MT8192_INFRACFG_AO_USBSIF_SW_RST 66 |
| +#define MT8192_INFRACFG_AO_KP_SW_RST 68 |
| +#define MT8192_INFRACFG_AO_APXGPT_SW_RST 69 |
| +#define MT8192_INFRACFG_AO_CLDMA_AO_SW_RST 70 |
| +#define MT8192_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 |
| +#define MT8192_INFRACFG_AO_DX_CC_SW_RST 72 |
| +#define MT8192_INFRACFG_AO_UFSPHY_SW_RST 73 |
| +#define MT8192_INFRACFG_AO_MEM_SW_RST 75 |
| +#define MT8192_INFRACFG_AO_PWM_AO_SW_RST 76 |
| +#define MT8192_INFRACFG_AO_TIA_AO_SW_RST 77 |
| +#define MT8192_INFRACFG_AO_PMIFSPMI_SW_RST 78 |
| +#define MT8192_INFRACFG_AO_PEXTP_PHY_SW_RST 79 |
| + |
| +#define MT8192_INFRACFG_AO_DX_CC_SEC_SW_RST 96 |
| +#define MT8192_INFRACFG_AO_GCE_SW_RST 97 |
| +#define MT8192_INFRACFG_AO_CLDMA_SW_RST 98 |
| +#define MT8192_INFRACFG_AO_TRNG_SW_RST 99 |
| +#define MT8192_INFRACFG_AO_MFG_CHIP_P2P_TX_SW_RST 100 |
| +#define MT8192_INFRACFG_AO_MFG_THERM_CTRL_PTP_SW_RST 101 |
| +#define MT8192_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 |
| +#define MT8192_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 |
| +#define MT8192_INFRACFG_AO_I2C1_IMM_SW_RST 105 |
| +#define MT8192_INFRACFG_AO_I2C1_ARB_SW_RST 106 |
| +#define MT8192_INFRACFG_AO_I2C2_IMM_SW_RST 107 |
| +#define MT8192_INFRACFG_AO_I2C2_ARB_SW_RST 108 |
| +#define MT8192_INFRACFG_AO_I2C5_SW_RST 109 |
| +#define MT8192_INFRACFG_AO_I2C5_IMM_SW_RST 110 |
| +#define MT8192_INFRACFG_AO_I2C5_ARB_SW_RST 111 |
| +#define MT8192_INFRACFG_AO_SPI4_SW_RST 112 |
| +#define MT8192_INFRACFG_AO_SPI5_SW_RST 113 |
| +#define MT8192_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 |
| +#define MT8192_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 |
| +#define MT8192_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 |
| +#define MT8192_INFRACFG_AO_UFS_AES_SW_RST 117 |
| +#define MT8192_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 |
| +#define MT8192_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 |
| +#define MT8192_INFRACFG_AO_I2C6_SW_RST 120 |
| +#define MT8192_INFRACFG_AO_CCU_GALS_SW_RST 121 |
| +#define MT8192_INFRACFG_AO_IPU_GALS_SW_RST 122 |
| +#define MT8192_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 |
| +#define MT8192_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 |
| +#define MT8192_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 |
| +#define MT8192_INFRACFG_AO_I2C7_SW_RST 126 |
| +#define MT8192_INFRACFG_AO_I2C8_SW_RST 127 |
| + |
| +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ |
| diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h |
| index 53d53c6c2be9a486e6000df17a4bdb27906e3401..48d343189e2873b89afc3f66d56fa74dba11b3c8 100644 |
| --- a/include/linux/io-pgtable.h |
| +++ b/include/linux/io-pgtable.h |
| @@ -77,8 +77,8 @@ struct io_pgtable_cfg { |
| * TLB maintenance when mapping as well as when unmapping. |
| * |
| * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend |
| - * to support up to 34 bits PA where the bit32 and bit33 are |
| - * encoded in the bit9 and bit4 of the PTE respectively. |
| + * to support up to 35 bits PA where the bit32, bit33 and bit34 are |
| + * encoded in the bit9, bit4 and bit5 of the PTE respectively. |
| * |
| * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs |
| * on unmap, for DMA domains using the flush queue mechanism for |
| diff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h |
| index c5a11b7458d4280849b73ae55507f1d0011bf02d..e205a80d604bc7119f029f53e2fe60af159d5ce3 100644 |
| --- a/include/linux/mfd/mt6358/core.h |
| +++ b/include/linux/mfd/mt6358/core.h |
| @@ -6,12 +6,9 @@ |
| #ifndef __MFD_MT6358_CORE_H__ |
| #define __MFD_MT6358_CORE_H__ |
| |
| -#define MT6358_REG_WIDTH 16 |
| - |
| struct irq_top_t { |
| int hwirq_base; |
| unsigned int num_int_regs; |
| - unsigned int num_int_bits; |
| unsigned int en_reg; |
| unsigned int en_reg_shift; |
| unsigned int sta_reg; |
| @@ -25,6 +22,7 @@ struct pmic_irq_data { |
| unsigned short top_int_status_reg; |
| bool *enable_hwirq; |
| bool *cache_hwirq; |
| + struct irq_top_t *pmic_ints; |
| }; |
| |
| enum mt6358_irq_top_status_shift { |
| @@ -34,7 +32,7 @@ enum mt6358_irq_top_status_shift { |
| MT6358_SCK_TOP, |
| MT6358_BM_TOP, |
| MT6358_HK_TOP, |
| - MT6358_AUD_TOP, |
| + MT6358_AUD_TOP = 7, |
| MT6358_MISC_TOP, |
| }; |
| |
| @@ -146,8 +144,8 @@ enum mt6358_irq_numbers { |
| { \ |
| .hwirq_base = MT6358_IRQ_##sp##_BASE, \ |
| .num_int_regs = \ |
| - ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \ |
| - .num_int_bits = MT6358_IRQ_##sp##_BITS, \ |
| + ((MT6358_IRQ_##sp##_BITS - 1) / \ |
| + MTK_PMIC_REG_WIDTH) + 1, \ |
| .en_reg = MT6358_##sp##_TOP_INT_CON0, \ |
| .en_reg_shift = 0x6, \ |
| .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \ |
| diff --git a/include/linux/mfd/mt6359/core.h b/include/linux/mfd/mt6359/core.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..5540a74ad08e8ddd288c183b17e9dcba07a4ac93 |
| --- /dev/null |
| +++ b/include/linux/mfd/mt6359/core.h |
| @@ -0,0 +1,133 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + */ |
| + |
| +#ifndef __MFD_MT6359_CORE_H__ |
| +#define __MFD_MT6359_CORE_H__ |
| + |
| +enum mt6359p_irq_top_status_shift { |
| + MT6359_BUCK_TOP = 0, |
| + MT6359_LDO_TOP, |
| + MT6359_PSC_TOP, |
| + MT6359_SCK_TOP, |
| + MT6359_BM_TOP, |
| + MT6359_HK_TOP, |
| + MT6359_AUD_TOP = 7, |
| + MT6359_MISC_TOP, |
| +}; |
| + |
| +enum mt6359p_irq_numbers { |
| + MT6359_IRQ_VCORE_OC = 1, |
| + MT6359_IRQ_VGPU11_OC, |
| + MT6359_IRQ_VGPU12_OC, |
| + MT6359_IRQ_VMODEM_OC, |
| + MT6359_IRQ_VPROC1_OC, |
| + MT6359_IRQ_VPROC2_OC, |
| + MT6359_IRQ_VS1_OC, |
| + MT6359_IRQ_VS2_OC, |
| + MT6359_IRQ_VPA_OC = 9, |
| + MT6359_IRQ_VFE28_OC = 16, |
| + MT6359_IRQ_VXO22_OC, |
| + MT6359_IRQ_VRF18_OC, |
| + MT6359_IRQ_VRF12_OC, |
| + MT6359_IRQ_VEFUSE_OC, |
| + MT6359_IRQ_VCN33_1_OC, |
| + MT6359_IRQ_VCN33_2_OC, |
| + MT6359_IRQ_VCN13_OC, |
| + MT6359_IRQ_VCN18_OC, |
| + MT6359_IRQ_VA09_OC, |
| + MT6359_IRQ_VCAMIO_OC, |
| + MT6359_IRQ_VA12_OC, |
| + MT6359_IRQ_VAUX18_OC, |
| + MT6359_IRQ_VAUD18_OC, |
| + MT6359_IRQ_VIO18_OC, |
| + MT6359_IRQ_VSRAM_PROC1_OC, |
| + MT6359_IRQ_VSRAM_PROC2_OC, |
| + MT6359_IRQ_VSRAM_OTHERS_OC, |
| + MT6359_IRQ_VSRAM_MD_OC, |
| + MT6359_IRQ_VEMC_OC, |
| + MT6359_IRQ_VSIM1_OC, |
| + MT6359_IRQ_VSIM2_OC, |
| + MT6359_IRQ_VUSB_OC, |
| + MT6359_IRQ_VRFCK_OC, |
| + MT6359_IRQ_VBBCK_OC, |
| + MT6359_IRQ_VBIF28_OC, |
| + MT6359_IRQ_VIBR_OC, |
| + MT6359_IRQ_VIO28_OC, |
| + MT6359_IRQ_VM18_OC, |
| + MT6359_IRQ_VUFS_OC = 45, |
| + MT6359_IRQ_PWRKEY = 48, |
| + MT6359_IRQ_HOMEKEY, |
| + MT6359_IRQ_PWRKEY_R, |
| + MT6359_IRQ_HOMEKEY_R, |
| + MT6359_IRQ_NI_LBAT_INT, |
| + MT6359_IRQ_CHRDET_EDGE = 53, |
| + MT6359_IRQ_RTC = 64, |
| + MT6359_IRQ_FG_BAT_H = 80, |
| + MT6359_IRQ_FG_BAT_L, |
| + MT6359_IRQ_FG_CUR_H, |
| + MT6359_IRQ_FG_CUR_L, |
| + MT6359_IRQ_FG_ZCV = 84, |
| + MT6359_IRQ_FG_N_CHARGE_L = 87, |
| + MT6359_IRQ_FG_IAVG_H, |
| + MT6359_IRQ_FG_IAVG_L = 89, |
| + MT6359_IRQ_FG_DISCHARGE = 91, |
| + MT6359_IRQ_FG_CHARGE, |
| + MT6359_IRQ_BATON_LV = 96, |
| + MT6359_IRQ_BATON_BAT_IN = 98, |
| + MT6359_IRQ_BATON_BAT_OU, |
| + MT6359_IRQ_BIF = 100, |
| + MT6359_IRQ_BAT_H = 112, |
| + MT6359_IRQ_BAT_L, |
| + MT6359_IRQ_BAT2_H, |
| + MT6359_IRQ_BAT2_L, |
| + MT6359_IRQ_BAT_TEMP_H, |
| + MT6359_IRQ_BAT_TEMP_L, |
| + MT6359_IRQ_THR_H, |
| + MT6359_IRQ_THR_L, |
| + MT6359_IRQ_AUXADC_IMP, |
| + MT6359_IRQ_NAG_C_DLTV = 121, |
| + MT6359_IRQ_AUDIO = 128, |
| + MT6359_IRQ_ACCDET = 133, |
| + MT6359_IRQ_ACCDET_EINT0, |
| + MT6359_IRQ_ACCDET_EINT1, |
| + MT6359_IRQ_SPI_CMD_ALERT = 144, |
| + MT6359_IRQ_NR, |
| +}; |
| + |
| +#define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC |
| +#define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC |
| +#define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY |
| +#define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC |
| +#define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H |
| +#define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H |
| +#define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO |
| +#define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT |
| + |
| +#define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1) |
| +#define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1) |
| +#define MT6359_IRQ_PSC_BITS \ |
| + (MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1) |
| +#define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1) |
| +#define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1) |
| +#define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1) |
| +#define MT6359_IRQ_AUD_BITS \ |
| + (MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1) |
| +#define MT6359_IRQ_MISC_BITS \ |
| + (MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1) |
| + |
| +#define MT6359_TOP_GEN(sp) \ |
| +{ \ |
| + .hwirq_base = MT6359_IRQ_##sp##_BASE, \ |
| + .num_int_regs = \ |
| + ((MT6359_IRQ_##sp##_BITS - 1) / \ |
| + MTK_PMIC_REG_WIDTH) + 1, \ |
| + .en_reg = MT6359_##sp##_TOP_INT_CON0, \ |
| + .en_reg_shift = 0x6, \ |
| + .sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \ |
| + .sta_reg_shift = 0x2, \ |
| + .top_offset = MT6359_##sp##_TOP, \ |
| +} |
| + |
| +#endif /* __MFD_MT6359_CORE_H__ */ |
| diff --git a/include/linux/mfd/mt6359/registers.h b/include/linux/mfd/mt6359/registers.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..32f627e0cb9c0e719e6ed6a7c5dedbef1bc748d7 |
| --- /dev/null |
| +++ b/include/linux/mfd/mt6359/registers.h |
| @@ -0,0 +1,531 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2019 MediaTek Inc. |
| + */ |
| + |
| +#ifndef __MFD_MT6359_REGISTERS_H__ |
| +#define __MFD_MT6359_REGISTERS_H__ |
| + |
| +/* PMIC Registers */ |
| +#define MT6359_SWCID 0xa |
| +#define MT6359_MISC_TOP_INT_CON0 0x188 |
| +#define MT6359_MISC_TOP_INT_STATUS0 0x194 |
| +#define MT6359_TOP_INT_STATUS0 0x19e |
| +#define MT6359_SCK_TOP_INT_CON0 0x528 |
| +#define MT6359_SCK_TOP_INT_STATUS0 0x534 |
| +#define MT6359_EOSC_CALI_CON0 0x53a |
| +#define MT6359_EOSC_CALI_CON1 0x53c |
| +#define MT6359_RTC_MIX_CON0 0x53e |
| +#define MT6359_RTC_MIX_CON1 0x540 |
| +#define MT6359_RTC_MIX_CON2 0x542 |
| +#define MT6359_RTC_DSN_ID 0x580 |
| +#define MT6359_RTC_DSN_REV0 0x582 |
| +#define MT6359_RTC_DBI 0x584 |
| +#define MT6359_RTC_DXI 0x586 |
| +#define MT6359_RTC_BBPU 0x588 |
| +#define MT6359_RTC_IRQ_STA 0x58a |
| +#define MT6359_RTC_IRQ_EN 0x58c |
| +#define MT6359_RTC_CII_EN 0x58e |
| +#define MT6359_RTC_AL_MASK 0x590 |
| +#define MT6359_RTC_TC_SEC 0x592 |
| +#define MT6359_RTC_TC_MIN 0x594 |
| +#define MT6359_RTC_TC_HOU 0x596 |
| +#define MT6359_RTC_TC_DOM 0x598 |
| +#define MT6359_RTC_TC_DOW 0x59a |
| +#define MT6359_RTC_TC_MTH 0x59c |
| +#define MT6359_RTC_TC_YEA 0x59e |
| +#define MT6359_RTC_AL_SEC 0x5a0 |
| +#define MT6359_RTC_AL_MIN 0x5a2 |
| +#define MT6359_RTC_AL_HOU 0x5a4 |
| +#define MT6359_RTC_AL_DOM 0x5a6 |
| +#define MT6359_RTC_AL_DOW 0x5a8 |
| +#define MT6359_RTC_AL_MTH 0x5aa |
| +#define MT6359_RTC_AL_YEA 0x5ac |
| +#define MT6359_RTC_OSC32CON 0x5ae |
| +#define MT6359_RTC_POWERKEY1 0x5b0 |
| +#define MT6359_RTC_POWERKEY2 0x5b2 |
| +#define MT6359_RTC_PDN1 0x5b4 |
| +#define MT6359_RTC_PDN2 0x5b6 |
| +#define MT6359_RTC_SPAR0 0x5b8 |
| +#define MT6359_RTC_SPAR1 0x5ba |
| +#define MT6359_RTC_PROT 0x5bc |
| +#define MT6359_RTC_DIFF 0x5be |
| +#define MT6359_RTC_CALI 0x5c0 |
| +#define MT6359_RTC_WRTGR 0x5c2 |
| +#define MT6359_RTC_CON 0x5c4 |
| +#define MT6359_RTC_SEC_CTRL 0x5c6 |
| +#define MT6359_RTC_INT_CNT 0x5c8 |
| +#define MT6359_RTC_SEC_DAT0 0x5ca |
| +#define MT6359_RTC_SEC_DAT1 0x5cc |
| +#define MT6359_RTC_SEC_DAT2 0x5ce |
| +#define MT6359_RTC_SEC_DSN_ID 0x600 |
| +#define MT6359_RTC_SEC_DSN_REV0 0x602 |
| +#define MT6359_RTC_SEC_DBI 0x604 |
| +#define MT6359_RTC_SEC_DXI 0x606 |
| +#define MT6359_RTC_TC_SEC_SEC 0x608 |
| +#define MT6359_RTC_TC_MIN_SEC 0x60a |
| +#define MT6359_RTC_TC_HOU_SEC 0x60c |
| +#define MT6359_RTC_TC_DOM_SEC 0x60e |
| +#define MT6359_RTC_TC_DOW_SEC 0x610 |
| +#define MT6359_RTC_TC_MTH_SEC 0x612 |
| +#define MT6359_RTC_TC_YEA_SEC 0x614 |
| +#define MT6359_RTC_SEC_CK_PDN 0x616 |
| +#define MT6359_RTC_SEC_WRTGR 0x618 |
| +#define MT6359_PSC_TOP_INT_CON0 0x910 |
| +#define MT6359_PSC_TOP_INT_STATUS0 0x91c |
| +#define MT6359_BM_TOP_INT_CON0 0xc32 |
| +#define MT6359_BM_TOP_INT_CON1 0xc38 |
| +#define MT6359_BM_TOP_INT_STATUS0 0xc4a |
| +#define MT6359_BM_TOP_INT_STATUS1 0xc4c |
| +#define MT6359_HK_TOP_INT_CON0 0xf92 |
| +#define MT6359_HK_TOP_INT_STATUS0 0xf9e |
| +#define MT6359_BUCK_TOP_INT_CON0 0x1418 |
| +#define MT6359_BUCK_TOP_INT_STATUS0 0x1424 |
| +#define MT6359_BUCK_VPU_CON0 0x1488 |
| +#define MT6359_BUCK_VPU_DBG0 0x14a6 |
| +#define MT6359_BUCK_VPU_DBG1 0x14a8 |
| +#define MT6359_BUCK_VPU_ELR0 0x14ac |
| +#define MT6359_BUCK_VCORE_CON0 0x1508 |
| +#define MT6359_BUCK_VCORE_DBG0 0x1526 |
| +#define MT6359_BUCK_VCORE_DBG1 0x1528 |
| +#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a |
| +#define MT6359_BUCK_VCORE_ELR0 0x1534 |
| +#define MT6359_BUCK_VGPU11_CON0 0x1588 |
| +#define MT6359_BUCK_VGPU11_DBG0 0x15a6 |
| +#define MT6359_BUCK_VGPU11_DBG1 0x15a8 |
| +#define MT6359_BUCK_VGPU11_ELR0 0x15ac |
| +#define MT6359_BUCK_VMODEM_CON0 0x1688 |
| +#define MT6359_BUCK_VMODEM_DBG0 0x16a6 |
| +#define MT6359_BUCK_VMODEM_DBG1 0x16a8 |
| +#define MT6359_BUCK_VMODEM_ELR0 0x16ae |
| +#define MT6359_BUCK_VPROC1_CON0 0x1708 |
| +#define MT6359_BUCK_VPROC1_DBG0 0x1726 |
| +#define MT6359_BUCK_VPROC1_DBG1 0x1728 |
| +#define MT6359_BUCK_VPROC1_ELR0 0x172e |
| +#define MT6359_BUCK_VPROC2_CON0 0x1788 |
| +#define MT6359_BUCK_VPROC2_DBG0 0x17a6 |
| +#define MT6359_BUCK_VPROC2_DBG1 0x17a8 |
| +#define MT6359_BUCK_VPROC2_ELR0 0x17b2 |
| +#define MT6359_BUCK_VS1_CON0 0x1808 |
| +#define MT6359_BUCK_VS1_DBG0 0x1826 |
| +#define MT6359_BUCK_VS1_DBG1 0x1828 |
| +#define MT6359_BUCK_VS1_ELR0 0x1834 |
| +#define MT6359_BUCK_VS2_CON0 0x1888 |
| +#define MT6359_BUCK_VS2_DBG0 0x18a6 |
| +#define MT6359_BUCK_VS2_DBG1 0x18a8 |
| +#define MT6359_BUCK_VS2_ELR0 0x18b4 |
| +#define MT6359_BUCK_VPA_CON0 0x1908 |
| +#define MT6359_BUCK_VPA_CON1 0x190e |
| +#define MT6359_BUCK_VPA_CFG0 0x1910 |
| +#define MT6359_BUCK_VPA_CFG1 0x1912 |
| +#define MT6359_BUCK_VPA_DBG0 0x1914 |
| +#define MT6359_BUCK_VPA_DBG1 0x1916 |
| +#define MT6359_VGPUVCORE_ANA_CON2 0x198e |
| +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4 |
| +#define MT6359_VPROC1_ANA_CON3 0x19b2 |
| +#define MT6359_VPROC2_ANA_CON3 0x1a0e |
| +#define MT6359_VMODEM_ANA_CON3 0x1a1a |
| +#define MT6359_VPU_ANA_CON3 0x1a26 |
| +#define MT6359_VS1_ANA_CON0 0x1a2c |
| +#define MT6359_VS2_ANA_CON0 0x1a34 |
| +#define MT6359_VPA_ANA_CON0 0x1a3c |
| +#define MT6359_LDO_TOP_INT_CON0 0x1b14 |
| +#define MT6359_LDO_TOP_INT_CON1 0x1b1a |
| +#define MT6359_LDO_TOP_INT_STATUS0 0x1b28 |
| +#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a |
| +#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40 |
| +#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42 |
| +#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44 |
| +#define MT6359_LDO_VSRAM_MD_ELR 0x1b46 |
| +#define MT6359_LDO_VFE28_CON0 0x1b88 |
| +#define MT6359_LDO_VFE28_MON 0x1b8a |
| +#define MT6359_LDO_VXO22_CON0 0x1b98 |
| +#define MT6359_LDO_VXO22_MON 0x1b9a |
| +#define MT6359_LDO_VRF18_CON0 0x1ba8 |
| +#define MT6359_LDO_VRF18_MON 0x1baa |
| +#define MT6359_LDO_VRF12_CON0 0x1bb8 |
| +#define MT6359_LDO_VRF12_MON 0x1bba |
| +#define MT6359_LDO_VEFUSE_CON0 0x1bc8 |
| +#define MT6359_LDO_VEFUSE_MON 0x1bca |
| +#define MT6359_LDO_VCN33_1_CON0 0x1bd8 |
| +#define MT6359_LDO_VCN33_1_MON 0x1bda |
| +#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8 |
| +#define MT6359_LDO_VCN33_2_CON0 0x1c08 |
| +#define MT6359_LDO_VCN33_2_MON 0x1c0a |
| +#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18 |
| +#define MT6359_LDO_VCN13_CON0 0x1c1a |
| +#define MT6359_LDO_VCN13_MON 0x1c1c |
| +#define MT6359_LDO_VCN18_CON0 0x1c2a |
| +#define MT6359_LDO_VCN18_MON 0x1c2c |
| +#define MT6359_LDO_VA09_CON0 0x1c3a |
| +#define MT6359_LDO_VA09_MON 0x1c3c |
| +#define MT6359_LDO_VCAMIO_CON0 0x1c4a |
| +#define MT6359_LDO_VCAMIO_MON 0x1c4c |
| +#define MT6359_LDO_VA12_CON0 0x1c5a |
| +#define MT6359_LDO_VA12_MON 0x1c5c |
| +#define MT6359_LDO_VAUX18_CON0 0x1c88 |
| +#define MT6359_LDO_VAUX18_MON 0x1c8a |
| +#define MT6359_LDO_VAUD18_CON0 0x1c98 |
| +#define MT6359_LDO_VAUD18_MON 0x1c9a |
| +#define MT6359_LDO_VIO18_CON0 0x1ca8 |
| +#define MT6359_LDO_VIO18_MON 0x1caa |
| +#define MT6359_LDO_VEMC_CON0 0x1cb8 |
| +#define MT6359_LDO_VEMC_MON 0x1cba |
| +#define MT6359_LDO_VSIM1_CON0 0x1cc8 |
| +#define MT6359_LDO_VSIM1_MON 0x1cca |
| +#define MT6359_LDO_VSIM2_CON0 0x1cd8 |
| +#define MT6359_LDO_VSIM2_MON 0x1cda |
| +#define MT6359_LDO_VUSB_CON0 0x1d08 |
| +#define MT6359_LDO_VUSB_MON 0x1d0a |
| +#define MT6359_LDO_VUSB_MULTI_SW 0x1d18 |
| +#define MT6359_LDO_VRFCK_CON0 0x1d1a |
| +#define MT6359_LDO_VRFCK_MON 0x1d1c |
| +#define MT6359_LDO_VBBCK_CON0 0x1d2a |
| +#define MT6359_LDO_VBBCK_MON 0x1d2c |
| +#define MT6359_LDO_VBIF28_CON0 0x1d3a |
| +#define MT6359_LDO_VBIF28_MON 0x1d3c |
| +#define MT6359_LDO_VIBR_CON0 0x1d4a |
| +#define MT6359_LDO_VIBR_MON 0x1d4c |
| +#define MT6359_LDO_VIO28_CON0 0x1d5a |
| +#define MT6359_LDO_VIO28_MON 0x1d5c |
| +#define MT6359_LDO_VM18_CON0 0x1d88 |
| +#define MT6359_LDO_VM18_MON 0x1d8a |
| +#define MT6359_LDO_VUFS_CON0 0x1d98 |
| +#define MT6359_LDO_VUFS_MON 0x1d9a |
| +#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88 |
| +#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a |
| +#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e |
| +#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6 |
| +#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8 |
| +#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac |
| +#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08 |
| +#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a |
| +#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e |
| +#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26 |
| +#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c |
| +#define MT6359_LDO_VSRAM_MD_MON 0x1f2e |
| +#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32 |
| +#define MT6359_VFE28_ANA_CON0 0x1f88 |
| +#define MT6359_VAUX18_ANA_CON0 0x1f8c |
| +#define MT6359_VUSB_ANA_CON0 0x1f90 |
| +#define MT6359_VBIF28_ANA_CON0 0x1f94 |
| +#define MT6359_VCN33_1_ANA_CON0 0x1f98 |
| +#define MT6359_VCN33_2_ANA_CON0 0x1f9c |
| +#define MT6359_VEMC_ANA_CON0 0x1fa0 |
| +#define MT6359_VSIM1_ANA_CON0 0x1fa4 |
| +#define MT6359_VSIM2_ANA_CON0 0x1fa8 |
| +#define MT6359_VIO28_ANA_CON0 0x1fac |
| +#define MT6359_VIBR_ANA_CON0 0x1fb0 |
| +#define MT6359_VRF18_ANA_CON0 0x2008 |
| +#define MT6359_VEFUSE_ANA_CON0 0x200c |
| +#define MT6359_VCN18_ANA_CON0 0x2010 |
| +#define MT6359_VCAMIO_ANA_CON0 0x2014 |
| +#define MT6359_VAUD18_ANA_CON0 0x2018 |
| +#define MT6359_VIO18_ANA_CON0 0x201c |
| +#define MT6359_VM18_ANA_CON0 0x2020 |
| +#define MT6359_VUFS_ANA_CON0 0x2024 |
| +#define MT6359_VRF12_ANA_CON0 0x202a |
| +#define MT6359_VCN13_ANA_CON0 0x202e |
| +#define MT6359_VA09_ANA_CON0 0x2032 |
| +#define MT6359_VA12_ANA_CON0 0x2036 |
| +#define MT6359_VXO22_ANA_CON0 0x2088 |
| +#define MT6359_VRFCK_ANA_CON0 0x208c |
| +#define MT6359_VBBCK_ANA_CON0 0x2094 |
| +#define MT6359_AUD_TOP_INT_CON0 0x2328 |
| +#define MT6359_AUD_TOP_INT_STATUS0 0x2334 |
| + |
| +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 |
| +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 |
| +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1 |
| +#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0 |
| +#define MT6359_DA_VPU_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VPU_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 |
| +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 |
| +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 |
| +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 |
| +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 |
| +#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0 |
| +#define MT6359_DA_VCORE_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VCORE_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 |
| +#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 |
| +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 |
| +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4 |
| +#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0 |
| +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 |
| +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 |
| +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 |
| +#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0 |
| +#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VGPU11_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 |
| +#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0 |
| +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 |
| +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 |
| +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 |
| +#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0 |
| +#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VMODEM_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 |
| +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 |
| +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 |
| +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 |
| +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 |
| +#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0 |
| +#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VPROC1_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 |
| +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 |
| +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 |
| +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 |
| +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 |
| +#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0 |
| +#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VPROC2_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 |
| +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 |
| +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 |
| +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 |
| +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1 |
| +#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0 |
| +#define MT6359_DA_VS1_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VS1_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 |
| +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 |
| +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 |
| +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 |
| +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1 |
| +#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0 |
| +#define MT6359_DA_VS2_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VS2_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 |
| +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 |
| +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F |
| +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 |
| +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 |
| +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 |
| +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1 |
| +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 |
| +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F |
| +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0 |
| +#define MT6359_DA_VPA_VOSEL_MASK 0x3F |
| +#define MT6359_DA_VPA_VOSEL_SHIFT 0 |
| +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 |
| +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 |
| +#define MT6359_RG_VGPU11_FCCM_SHIFT 9 |
| +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 |
| +#define MT6359_RG_VCORE_FCCM_SHIFT 5 |
| +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 |
| +#define MT6359_RG_VPROC1_FCCM_SHIFT 1 |
| +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 |
| +#define MT6359_RG_VPROC2_FCCM_SHIFT 1 |
| +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 |
| +#define MT6359_RG_VMODEM_FCCM_SHIFT 1 |
| +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 |
| +#define MT6359_RG_VPU_FCCM_SHIFT 1 |
| +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 |
| +#define MT6359_RG_VS1_FPWM_SHIFT 3 |
| +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 |
| +#define MT6359_RG_VS2_FPWM_SHIFT 3 |
| +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 |
| +#define MT6359_RG_VPA_MODESET_SHIFT 1 |
| +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR |
| +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F |
| +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 |
| +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR |
| +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F |
| +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 |
| +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR |
| +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F |
| +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 |
| +#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0 |
| +#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON |
| +#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0 |
| +#define MT6359_RG_LDO_VXO22_EN_SHIFT 0 |
| +#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON |
| +#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0 |
| +#define MT6359_RG_LDO_VRF18_EN_SHIFT 0 |
| +#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON |
| +#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0 |
| +#define MT6359_RG_LDO_VRF12_EN_SHIFT 0 |
| +#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON |
| +#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0 |
| +#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0 |
| +#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON |
| +#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0 |
| +#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1 |
| +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 |
| +#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON |
| +#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW |
| +#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15 |
| +#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0 |
| +#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0 |
| +#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON |
| +#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW |
| +#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1 |
| +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 |
| +#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0 |
| +#define MT6359_RG_LDO_VCN13_EN_SHIFT 0 |
| +#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON |
| +#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0 |
| +#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON |
| +#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0 |
| +#define MT6359_RG_LDO_VA09_EN_SHIFT 0 |
| +#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON |
| +#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0 |
| +#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0 |
| +#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON |
| +#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0 |
| +#define MT6359_RG_LDO_VA12_EN_SHIFT 0 |
| +#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON |
| +#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0 |
| +#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON |
| +#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0 |
| +#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON |
| +#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0 |
| +#define MT6359_RG_LDO_VIO18_EN_SHIFT 0 |
| +#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON |
| +#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0 |
| +#define MT6359_RG_LDO_VEMC_EN_SHIFT 0 |
| +#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON |
| +#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0 |
| +#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0 |
| +#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON |
| +#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0 |
| +#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0 |
| +#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON |
| +#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0 |
| +#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1 |
| +#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0 |
| +#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON |
| +#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW |
| +#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1 |
| +#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15 |
| +#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0 |
| +#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0 |
| +#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON |
| +#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0 |
| +#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0 |
| +#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON |
| +#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0 |
| +#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON |
| +#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0 |
| +#define MT6359_RG_LDO_VIBR_EN_SHIFT 0 |
| +#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON |
| +#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0 |
| +#define MT6359_RG_LDO_VIO28_EN_SHIFT 0 |
| +#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON |
| +#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0 |
| +#define MT6359_RG_LDO_VM18_EN_SHIFT 0 |
| +#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON |
| +#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0 |
| +#define MT6359_RG_LDO_VUFS_EN_SHIFT 0 |
| +#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON |
| +#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0 |
| +#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON |
| +#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1 |
| +#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8 |
| +#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0 |
| +#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON |
| +#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1 |
| +#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8 |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0 |
| +#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON |
| +#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1 |
| +#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8 |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR \ |
| + MT6359_LDO_VSRAM_OTHERS_SSHUB |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR \ |
| + MT6359_LDO_VSRAM_OTHERS_SSHUB |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F |
| +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 |
| +#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0 |
| +#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON |
| +#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1 |
| +#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F |
| +#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0 |
| +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF |
| +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0 |
| +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF |
| +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0 |
| +#define MT6359_RG_VEMC_VOSEL_MASK 0xF |
| +#define MT6359_RG_VEMC_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0 |
| +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF |
| +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0 |
| +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF |
| +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0 |
| +#define MT6359_RG_VIO28_VOSEL_MASK 0xF |
| +#define MT6359_RG_VIO28_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0 |
| +#define MT6359_RG_VIBR_VOSEL_MASK 0xF |
| +#define MT6359_RG_VIBR_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0 |
| +#define MT6359_RG_VRF18_VOSEL_MASK 0xF |
| +#define MT6359_RG_VRF18_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0 |
| +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF |
| +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0 |
| +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF |
| +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0 |
| +#define MT6359_RG_VIO18_VOSEL_MASK 0xF |
| +#define MT6359_RG_VIO18_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0 |
| +#define MT6359_RG_VM18_VOSEL_MASK 0xF |
| +#define MT6359_RG_VM18_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0 |
| +#define MT6359_RG_VUFS_VOSEL_MASK 0xF |
| +#define MT6359_RG_VUFS_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0 |
| +#define MT6359_RG_VRF12_VOSEL_MASK 0xF |
| +#define MT6359_RG_VRF12_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0 |
| +#define MT6359_RG_VCN13_VOSEL_MASK 0xF |
| +#define MT6359_RG_VCN13_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0 |
| +#define MT6359_RG_VA09_VOSEL_MASK 0xF |
| +#define MT6359_RG_VA09_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0 |
| +#define MT6359_RG_VA12_VOSEL_MASK 0xF |
| +#define MT6359_RG_VA12_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0 |
| +#define MT6359_RG_VXO22_VOSEL_MASK 0xF |
| +#define MT6359_RG_VXO22_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0 |
| +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF |
| +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8 |
| +#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0 |
| +#define MT6359_RG_VBBCK_VOSEL_MASK 0xF |
| +#define MT6359_RG_VBBCK_VOSEL_SHIFT 8 |
| + |
| +#endif /* __MFD_MT6359_REGISTERS_H__ */ |
| diff --git a/include/linux/mfd/mt6359p/registers.h b/include/linux/mfd/mt6359p/registers.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..5f8cfc9e40c76ca620c3514a00d2fbb5bf9305a4 |
| --- /dev/null |
| +++ b/include/linux/mfd/mt6359p/registers.h |
| @@ -0,0 +1,555 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + */ |
| + |
| +#ifndef __MFD_MT6359P_REGISTERS_H__ |
| +#define __MFD_MT6359P_REGISTERS_H__ |
| + |
| +#define MT6359P_CHIP_VER 0x5930 |
| + |
| +/* PMIC Registers */ |
| +#define MT6359P_HWCID 0x8 |
| +#define MT6359P_SWCID 0xa |
| +#define MT6359P_TOP_TRAP 0x50 |
| +#define MT6359P_MISC_TOP_INT_CON0 0x188 |
| +#define MT6359P_MISC_TOP_INT_STATUS0 0x194 |
| +#define MT6359P_TOP_INT_STATUS0 0x19e |
| +#define MT6359P_TOP_TMA_KEY 0x3a8 |
| +#define MT6359P_SCK_TOP_INT_CON0 0x528 |
| +#define MT6359P_SCK_TOP_INT_STATUS0 0x534 |
| +#define MT6359P_EOSC_CALI_CON0 0x53a |
| +#define MT6359P_EOSC_CALI_CON1 0x53c |
| +#define MT6359P_RTC_MIX_CON0 0x53e |
| +#define MT6359P_RTC_MIX_CON1 0x540 |
| +#define MT6359P_RTC_MIX_CON2 0x542 |
| +#define MT6359P_RTC_DSN_ID 0x580 |
| +#define MT6359P_RTC_DSN_REV0 0x582 |
| +#define MT6359P_RTC_DBI 0x584 |
| +#define MT6359P_RTC_DXI 0x586 |
| +#define MT6359P_RTC_BBPU 0x588 |
| +#define MT6359P_RTC_IRQ_STA 0x58a |
| +#define MT6359P_RTC_IRQ_EN 0x58c |
| +#define MT6359P_RTC_CII_EN 0x58e |
| +#define MT6359P_RTC_AL_MASK 0x590 |
| +#define MT6359P_RTC_TC_SEC 0x592 |
| +#define MT6359P_RTC_TC_MIN 0x594 |
| +#define MT6359P_RTC_TC_HOU 0x596 |
| +#define MT6359P_RTC_TC_DOM 0x598 |
| +#define MT6359P_RTC_TC_DOW 0x59a |
| +#define MT6359P_RTC_TC_MTH 0x59c |
| +#define MT6359P_RTC_TC_YEA 0x59e |
| +#define MT6359P_RTC_AL_SEC 0x5a0 |
| +#define MT6359P_RTC_AL_MIN 0x5a2 |
| +#define MT6359P_RTC_AL_HOU 0x5a4 |
| +#define MT6359P_RTC_AL_DOM 0x5a6 |
| +#define MT6359P_RTC_AL_DOW 0x5a8 |
| +#define MT6359P_RTC_AL_MTH 0x5aa |
| +#define MT6359P_RTC_AL_YEA 0x5ac |
| +#define MT6359P_RTC_OSC32CON 0x5ae |
| +#define MT6359P_RTC_POWERKEY1 0x5b0 |
| +#define MT6359P_RTC_POWERKEY2 0x5b2 |
| +#define MT6359P_RTC_PDN1 0x5b4 |
| +#define MT6359P_RTC_PDN2 0x5b6 |
| +#define MT6359P_RTC_SPAR0 0x5b8 |
| +#define MT6359P_RTC_SPAR1 0x5ba |
| +#define MT6359P_RTC_PROT 0x5bc |
| +#define MT6359P_RTC_DIFF 0x5be |
| +#define MT6359P_RTC_CALI 0x5c0 |
| +#define MT6359P_RTC_WRTGR 0x5c2 |
| +#define MT6359P_RTC_CON 0x5c4 |
| +#define MT6359P_RTC_SEC_CTRL 0x5c6 |
| +#define MT6359P_RTC_INT_CNT 0x5c8 |
| +#define MT6359P_RTC_SEC_DAT0 0x5ca |
| +#define MT6359P_RTC_SEC_DAT1 0x5cc |
| +#define MT6359P_RTC_SEC_DAT2 0x5ce |
| +#define MT6359P_RTC_SEC_DSN_ID 0x600 |
| +#define MT6359P_RTC_SEC_DSN_REV0 0x602 |
| +#define MT6359P_RTC_SEC_DBI 0x604 |
| +#define MT6359P_RTC_SEC_DXI 0x606 |
| +#define MT6359P_RTC_TC_SEC_SEC 0x608 |
| +#define MT6359P_RTC_TC_MIN_SEC 0x60a |
| +#define MT6359P_RTC_TC_HOU_SEC 0x60c |
| +#define MT6359P_RTC_TC_DOM_SEC 0x60e |
| +#define MT6359P_RTC_TC_DOW_SEC 0x610 |
| +#define MT6359P_RTC_TC_MTH_SEC 0x612 |
| +#define MT6359P_RTC_TC_YEA_SEC 0x614 |
| +#define MT6359P_RTC_SEC_CK_PDN 0x616 |
| +#define MT6359P_RTC_SEC_WRTGR 0x618 |
| +#define MT6359P_PSC_TOP_INT_CON0 0x910 |
| +#define MT6359P_PSC_TOP_INT_STATUS0 0x91c |
| +#define MT6359P_BM_TOP_INT_CON0 0xc32 |
| +#define MT6359P_BM_TOP_INT_CON1 0xc38 |
| +#define MT6359P_BM_TOP_INT_STATUS0 0xc4a |
| +#define MT6359P_BM_TOP_INT_STATUS1 0xc4c |
| +#define MT6359P_HK_TOP_INT_CON0 0xf92 |
| +#define MT6359P_HK_TOP_INT_STATUS0 0xf9e |
| +#define MT6359P_BUCK_TOP_INT_CON0 0x1418 |
| +#define MT6359P_BUCK_TOP_INT_STATUS0 0x1424 |
| +#define MT6359P_BUCK_VPU_CON0 0x1488 |
| +#define MT6359P_BUCK_VPU_DBG0 0x14a6 |
| +#define MT6359P_BUCK_VPU_DBG1 0x14a8 |
| +#define MT6359P_BUCK_VPU_ELR0 0x14ac |
| +#define MT6359P_BUCK_VCORE_CON0 0x1508 |
| +#define MT6359P_BUCK_VCORE_DBG0 0x1526 |
| +#define MT6359P_BUCK_VCORE_DBG1 0x1528 |
| +#define MT6359P_BUCK_VCORE_ELR_NUM 0x152a |
| +#define MT6359P_BUCK_VCORE_ELR0 0x152c |
| +#define MT6359P_BUCK_VGPU11_CON0 0x1588 |
| +#define MT6359P_BUCK_VGPU11_DBG0 0x15a6 |
| +#define MT6359P_BUCK_VGPU11_DBG1 0x15a8 |
| +#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa |
| +#define MT6359P_BUCK_VGPU11_ELR0 0x15b4 |
| +#define MT6359P_BUCK_VGPU12_CON0 0x1608 |
| +#define MT6359P_BUCK_VGPU12_DBG0 0x1626 |
| +#define MT6359P_BUCK_VGPU12_DBG1 0x1628 |
| +#define MT6359P_BUCK_VMODEM_CON0 0x1688 |
| +#define MT6359P_BUCK_VMODEM_DBG0 0x16a6 |
| +#define MT6359P_BUCK_VMODEM_DBG1 0x16a8 |
| +#define MT6359P_BUCK_VMODEM_ELR0 0x16ae |
| +#define MT6359P_BUCK_VPROC1_CON0 0x1708 |
| +#define MT6359P_BUCK_VPROC1_DBG0 0x1726 |
| +#define MT6359P_BUCK_VPROC1_DBG1 0x1728 |
| +#define MT6359P_BUCK_VPROC1_ELR0 0x172e |
| +#define MT6359P_BUCK_VPROC2_CON0 0x1788 |
| +#define MT6359P_BUCK_VPROC2_DBG0 0x17a6 |
| +#define MT6359P_BUCK_VPROC2_DBG1 0x17a8 |
| +#define MT6359P_BUCK_VPROC2_ELR0 0x17b2 |
| +#define MT6359P_BUCK_VS1_CON0 0x1808 |
| +#define MT6359P_BUCK_VS1_DBG0 0x1826 |
| +#define MT6359P_BUCK_VS1_DBG1 0x1828 |
| +#define MT6359P_BUCK_VS1_ELR0 0x1834 |
| +#define MT6359P_BUCK_VS2_CON0 0x1888 |
| +#define MT6359P_BUCK_VS2_DBG0 0x18a6 |
| +#define MT6359P_BUCK_VS2_DBG1 0x18a8 |
| +#define MT6359P_BUCK_VS2_ELR0 0x18b4 |
| +#define MT6359P_BUCK_VPA_CON0 0x1908 |
| +#define MT6359P_BUCK_VPA_CON1 0x190e |
| +#define MT6359P_BUCK_VPA_CFG0 0x1910 |
| +#define MT6359P_BUCK_VPA_CFG1 0x1912 |
| +#define MT6359P_BUCK_VPA_DBG0 0x1914 |
| +#define MT6359P_BUCK_VPA_DBG1 0x1916 |
| +#define MT6359P_VGPUVCORE_ANA_CON2 0x198e |
| +#define MT6359P_VGPUVCORE_ANA_CON13 0x19a4 |
| +#define MT6359P_VPROC1_ANA_CON3 0x19b2 |
| +#define MT6359P_VPROC2_ANA_CON3 0x1a0e |
| +#define MT6359P_VMODEM_ANA_CON3 0x1a1a |
| +#define MT6359P_VPU_ANA_CON3 0x1a26 |
| +#define MT6359P_VS1_ANA_CON0 0x1a2c |
| +#define MT6359P_VS2_ANA_CON0 0x1a34 |
| +#define MT6359P_VPA_ANA_CON0 0x1a3c |
| +#define MT6359P_LDO_TOP_INT_CON0 0x1b14 |
| +#define MT6359P_LDO_TOP_INT_CON1 0x1b1a |
| +#define MT6359P_LDO_TOP_INT_STATUS0 0x1b28 |
| +#define MT6359P_LDO_TOP_INT_STATUS1 0x1b2a |
| +#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 |
| +#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 |
| +#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 |
| +#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a |
| +#define MT6359P_LDO_VEMC_ELR_0 0x1b4c |
| +#define MT6359P_LDO_VFE28_CON0 0x1b88 |
| +#define MT6359P_LDO_VFE28_MON 0x1b8c |
| +#define MT6359P_LDO_VXO22_CON0 0x1b9a |
| +#define MT6359P_LDO_VXO22_MON 0x1b9e |
| +#define MT6359P_LDO_VRF18_CON0 0x1bac |
| +#define MT6359P_LDO_VRF18_MON 0x1bb0 |
| +#define MT6359P_LDO_VRF12_CON0 0x1bbe |
| +#define MT6359P_LDO_VRF12_MON 0x1bc2 |
| +#define MT6359P_LDO_VEFUSE_CON0 0x1bd0 |
| +#define MT6359P_LDO_VEFUSE_MON 0x1bd4 |
| +#define MT6359P_LDO_VCN33_1_CON0 0x1be2 |
| +#define MT6359P_LDO_VCN33_1_MON 0x1be6 |
| +#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 |
| +#define MT6359P_LDO_VCN33_2_CON0 0x1c08 |
| +#define MT6359P_LDO_VCN33_2_MON 0x1c0c |
| +#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a |
| +#define MT6359P_LDO_VCN13_CON0 0x1c1c |
| +#define MT6359P_LDO_VCN13_MON 0x1c20 |
| +#define MT6359P_LDO_VCN18_CON0 0x1c2e |
| +#define MT6359P_LDO_VCN18_MON 0x1c32 |
| +#define MT6359P_LDO_VA09_CON0 0x1c40 |
| +#define MT6359P_LDO_VA09_MON 0x1c44 |
| +#define MT6359P_LDO_VCAMIO_CON0 0x1c52 |
| +#define MT6359P_LDO_VCAMIO_MON 0x1c56 |
| +#define MT6359P_LDO_VA12_CON0 0x1c64 |
| +#define MT6359P_LDO_VA12_MON 0x1c68 |
| +#define MT6359P_LDO_VAUX18_CON0 0x1c88 |
| +#define MT6359P_LDO_VAUX18_MON 0x1c8c |
| +#define MT6359P_LDO_VAUD18_CON0 0x1c9a |
| +#define MT6359P_LDO_VAUD18_MON 0x1c9e |
| +#define MT6359P_LDO_VIO18_CON0 0x1cac |
| +#define MT6359P_LDO_VIO18_MON 0x1cb0 |
| +#define MT6359P_LDO_VEMC_CON0 0x1cbe |
| +#define MT6359P_LDO_VEMC_MON 0x1cc2 |
| +#define MT6359P_LDO_VSIM1_CON0 0x1cd0 |
| +#define MT6359P_LDO_VSIM1_MON 0x1cd4 |
| +#define MT6359P_LDO_VSIM2_CON0 0x1ce2 |
| +#define MT6359P_LDO_VSIM2_MON 0x1ce6 |
| +#define MT6359P_LDO_VUSB_CON0 0x1d08 |
| +#define MT6359P_LDO_VUSB_MON 0x1d0c |
| +#define MT6359P_LDO_VUSB_MULTI_SW 0x1d1a |
| +#define MT6359P_LDO_VRFCK_CON0 0x1d1c |
| +#define MT6359P_LDO_VRFCK_MON 0x1d20 |
| +#define MT6359P_LDO_VBBCK_CON0 0x1d2e |
| +#define MT6359P_LDO_VBBCK_MON 0x1d32 |
| +#define MT6359P_LDO_VBIF28_CON0 0x1d40 |
| +#define MT6359P_LDO_VBIF28_MON 0x1d44 |
| +#define MT6359P_LDO_VIBR_CON0 0x1d52 |
| +#define MT6359P_LDO_VIBR_MON 0x1d56 |
| +#define MT6359P_LDO_VIO28_CON0 0x1d64 |
| +#define MT6359P_LDO_VIO28_MON 0x1d68 |
| +#define MT6359P_LDO_VM18_CON0 0x1d88 |
| +#define MT6359P_LDO_VM18_MON 0x1d8c |
| +#define MT6359P_LDO_VUFS_CON0 0x1d9a |
| +#define MT6359P_LDO_VUFS_MON 0x1d9e |
| +#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 |
| +#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c |
| +#define MT6359P_LDO_VSRAM_PROC1_VOSEL1 0x1e90 |
| +#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 |
| +#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac |
| +#define MT6359P_LDO_VSRAM_PROC2_VOSEL1 0x1eb0 |
| +#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 |
| +#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c |
| +#define MT6359P_LDO_VSRAM_OTHERS_VOSEL1 0x1f10 |
| +#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 |
| +#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e |
| +#define MT6359P_LDO_VSRAM_MD_MON 0x1f32 |
| +#define MT6359P_LDO_VSRAM_MD_VOSEL1 0x1f36 |
| +#define MT6359P_VFE28_ANA_CON0 0x1f88 |
| +#define MT6359P_VAUX18_ANA_CON0 0x1f8c |
| +#define MT6359P_VUSB_ANA_CON0 0x1f90 |
| +#define MT6359P_VBIF28_ANA_CON0 0x1f94 |
| +#define MT6359P_VCN33_1_ANA_CON0 0x1f98 |
| +#define MT6359P_VCN33_2_ANA_CON0 0x1f9c |
| +#define MT6359P_VEMC_ANA_CON0 0x1fa0 |
| +#define MT6359P_VSIM1_ANA_CON0 0x1fa2 |
| +#define MT6359P_VSIM2_ANA_CON0 0x1fa6 |
| +#define MT6359P_VIO28_ANA_CON0 0x1faa |
| +#define MT6359P_VIBR_ANA_CON0 0x1fae |
| +#define MT6359P_VFE28_ELR_4 0x1fc0 |
| +#define MT6359P_VRF18_ANA_CON0 0x2008 |
| +#define MT6359P_VEFUSE_ANA_CON0 0x200c |
| +#define MT6359P_VCN18_ANA_CON0 0x2010 |
| +#define MT6359P_VCAMIO_ANA_CON0 0x2014 |
| +#define MT6359P_VAUD18_ANA_CON0 0x2018 |
| +#define MT6359P_VIO18_ANA_CON0 0x201c |
| +#define MT6359P_VM18_ANA_CON0 0x2020 |
| +#define MT6359P_VUFS_ANA_CON0 0x2024 |
| +#define MT6359P_VRF12_ANA_CON0 0x202a |
| +#define MT6359P_VCN13_ANA_CON0 0x202e |
| +#define MT6359P_VA09_ANA_CON0 0x2032 |
| +#define MT6359P_VXO22_ANA_CON0 0x2088 |
| +#define MT6359P_VRFCK_ANA_CON0 0x208c |
| +#define MT6359P_VBBCK_ANA_CON0 0x2096 |
| +#define MT6359P_AUD_TOP_INT_CON0 0x2328 |
| +#define MT6359P_AUD_TOP_INT_STATUS0 0x2334 |
| + |
| +#define MT6359P_RG_BUCK_VPU_EN_ADDR MT6359P_BUCK_VPU_CON0 |
| +#define MT6359P_RG_BUCK_VPU_LP_ADDR MT6359P_BUCK_VPU_CON0 |
| +#define MT6359P_RG_BUCK_VPU_LP_SHIFT 1 |
| +#define MT6359P_DA_VPU_VOSEL_ADDR MT6359P_BUCK_VPU_DBG0 |
| +#define MT6359P_DA_VPU_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VPU_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VPU_EN_ADDR MT6359P_BUCK_VPU_DBG1 |
| +#define MT6359P_RG_BUCK_VPU_VOSEL_ADDR MT6359P_BUCK_VPU_ELR0 |
| +#define MT6359P_RG_BUCK_VPU_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VPU_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VCORE_EN_ADDR MT6359P_BUCK_VCORE_CON0 |
| +#define MT6359P_RG_BUCK_VCORE_LP_ADDR MT6359P_BUCK_VCORE_CON0 |
| +#define MT6359P_RG_BUCK_VCORE_LP_SHIFT 1 |
| +#define MT6359P_DA_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_DBG0 |
| +#define MT6359P_DA_VCORE_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VCORE_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VCORE_EN_ADDR MT6359P_BUCK_VCORE_DBG1 |
| +#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 |
| +#define MT6359P_RG_BUCK_VCORE_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VCORE_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VGPU11_EN_ADDR MT6359P_BUCK_VGPU11_CON0 |
| +#define MT6359P_RG_BUCK_VGPU11_LP_ADDR MT6359P_BUCK_VGPU11_CON0 |
| +#define MT6359P_RG_BUCK_VGPU11_LP_SHIFT 1 |
| +#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 |
| +#define MT6359P_DA_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_DBG0 |
| +#define MT6359P_DA_VGPU11_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VGPU11_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VGPU11_EN_ADDR MT6359P_BUCK_VGPU11_DBG1 |
| +#define MT6359P_RG_BUCK_VGPU12_EN_ADDR MT6359P_BUCK_VGPU12_CON0 |
| +#define MT6359P_RG_BUCK_VGPU12_LP_ADDR MT6359P_BUCK_VGPU12_CON0 |
| +#define MT6359P_RG_BUCK_VGPU12_LP_SHIFT 1 |
| +#define MT6359P_DA_VGPU12_VOSEL_ADDR MT6359P_BUCK_VGPU12_DBG0 |
| +#define MT6359P_DA_VGPU12_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VGPU12_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VGPU12_EN_ADDR MT6359P_BUCK_VGPU12_DBG1 |
| +#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 |
| +#define MT6359P_RG_BUCK_VGPU11_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VGPU11_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 |
| +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 |
| +#define MT6359P_RG_BUCK_VMODEM_EN_ADDR MT6359P_BUCK_VMODEM_CON0 |
| +#define MT6359P_RG_BUCK_VMODEM_LP_ADDR MT6359P_BUCK_VMODEM_CON0 |
| +#define MT6359P_RG_BUCK_VMODEM_LP_SHIFT 1 |
| +#define MT6359P_DA_VMODEM_VOSEL_ADDR MT6359P_BUCK_VMODEM_DBG0 |
| +#define MT6359P_DA_VMODEM_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VMODEM_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VMODEM_EN_ADDR MT6359P_BUCK_VMODEM_DBG1 |
| +#define MT6359P_RG_BUCK_VMODEM_VOSEL_ADDR MT6359P_BUCK_VMODEM_ELR0 |
| +#define MT6359P_RG_BUCK_VMODEM_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VMODEM_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VPROC1_EN_ADDR MT6359P_BUCK_VPROC1_CON0 |
| +#define MT6359P_RG_BUCK_VPROC1_LP_ADDR MT6359P_BUCK_VPROC1_CON0 |
| +#define MT6359P_RG_BUCK_VPROC1_LP_SHIFT 1 |
| +#define MT6359P_DA_VPROC1_VOSEL_ADDR MT6359P_BUCK_VPROC1_DBG0 |
| +#define MT6359P_DA_VPROC1_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VPROC1_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VPROC1_EN_ADDR MT6359P_BUCK_VPROC1_DBG1 |
| +#define MT6359P_RG_BUCK_VPROC1_VOSEL_ADDR MT6359P_BUCK_VPROC1_ELR0 |
| +#define MT6359P_RG_BUCK_VPROC1_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VPROC1_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VPROC2_EN_ADDR MT6359P_BUCK_VPROC2_CON0 |
| +#define MT6359P_RG_BUCK_VPROC2_LP_ADDR MT6359P_BUCK_VPROC2_CON0 |
| +#define MT6359P_RG_BUCK_VPROC2_LP_SHIFT 1 |
| +#define MT6359P_DA_VPROC2_VOSEL_ADDR MT6359P_BUCK_VPROC2_DBG0 |
| +#define MT6359P_DA_VPROC2_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VPROC2_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VPROC2_EN_ADDR MT6359P_BUCK_VPROC2_DBG1 |
| +#define MT6359P_RG_BUCK_VPROC2_VOSEL_ADDR MT6359P_BUCK_VPROC2_ELR0 |
| +#define MT6359P_RG_BUCK_VPROC2_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VPROC2_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VS1_EN_ADDR MT6359P_BUCK_VS1_CON0 |
| +#define MT6359P_RG_BUCK_VS1_LP_ADDR MT6359P_BUCK_VS1_CON0 |
| +#define MT6359P_RG_BUCK_VS1_LP_SHIFT 1 |
| +#define MT6359P_DA_VS1_VOSEL_ADDR MT6359P_BUCK_VS1_DBG0 |
| +#define MT6359P_DA_VS1_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VS1_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VS1_EN_ADDR MT6359P_BUCK_VS1_DBG1 |
| +#define MT6359P_RG_BUCK_VS1_VOSEL_ADDR MT6359P_BUCK_VS1_ELR0 |
| +#define MT6359P_RG_BUCK_VS1_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VS1_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VS2_EN_ADDR MT6359P_BUCK_VS2_CON0 |
| +#define MT6359P_RG_BUCK_VS2_LP_ADDR MT6359P_BUCK_VS2_CON0 |
| +#define MT6359P_RG_BUCK_VS2_LP_SHIFT 1 |
| +#define MT6359P_DA_VS2_VOSEL_ADDR MT6359P_BUCK_VS2_DBG0 |
| +#define MT6359P_DA_VS2_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VS2_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VS2_EN_ADDR MT6359P_BUCK_VS2_DBG1 |
| +#define MT6359P_RG_BUCK_VS2_VOSEL_ADDR MT6359P_BUCK_VS2_ELR0 |
| +#define MT6359P_RG_BUCK_VS2_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_BUCK_VS2_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_BUCK_VPA_EN_ADDR MT6359P_BUCK_VPA_CON0 |
| +#define MT6359P_RG_BUCK_VPA_LP_ADDR MT6359P_BUCK_VPA_CON0 |
| +#define MT6359P_RG_BUCK_VPA_LP_SHIFT 1 |
| +#define MT6359P_RG_BUCK_VPA_VOSEL_ADDR MT6359P_BUCK_VPA_CON1 |
| +#define MT6359P_RG_BUCK_VPA_VOSEL_MASK 0x3F |
| +#define MT6359P_RG_BUCK_VPA_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VPA_VOSEL_ADDR MT6359P_BUCK_VPA_DBG0 |
| +#define MT6359P_DA_VPA_VOSEL_MASK 0x3F |
| +#define MT6359P_DA_VPA_VOSEL_SHIFT 0 |
| +#define MT6359P_DA_VPA_EN_ADDR MT6359P_BUCK_VPA_DBG1 |
| +#define MT6359P_RG_VGPU11_FCCM_ADDR MT6359P_VGPUVCORE_ANA_CON2 |
| +#define MT6359P_RG_VGPU11_FCCM_SHIFT 9 |
| +#define MT6359P_RG_VCORE_FCCM_ADDR MT6359P_VGPUVCORE_ANA_CON13 |
| +#define MT6359P_RG_VCORE_FCCM_SHIFT 5 |
| +#define MT6359P_RG_VPROC1_FCCM_ADDR MT6359P_VPROC1_ANA_CON3 |
| +#define MT6359P_RG_VPROC1_FCCM_SHIFT 1 |
| +#define MT6359P_RG_VPROC2_FCCM_ADDR MT6359P_VPROC2_ANA_CON3 |
| +#define MT6359P_RG_VPROC2_FCCM_SHIFT 1 |
| +#define MT6359P_RG_VMODEM_FCCM_ADDR MT6359P_VMODEM_ANA_CON3 |
| +#define MT6359P_RG_VMODEM_FCCM_SHIFT 1 |
| +#define MT6359P_RG_VPU_FCCM_ADDR MT6359P_VPU_ANA_CON3 |
| +#define MT6359P_RG_VPU_FCCM_SHIFT 1 |
| +#define MT6359P_RG_VS1_FPWM_ADDR MT6359P_VS1_ANA_CON0 |
| +#define MT6359P_RG_VS1_FPWM_SHIFT 3 |
| +#define MT6359P_RG_VS2_FPWM_ADDR MT6359P_VS2_ANA_CON0 |
| +#define MT6359P_RG_VS2_FPWM_SHIFT 3 |
| +#define MT6359P_RG_VPA_MODESET_ADDR MT6359P_VPA_ANA_CON0 |
| +#define MT6359P_RG_VPA_MODESET_SHIFT 1 |
| +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR |
| +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR |
| +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR |
| +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 |
| +#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 |
| +#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF |
| +#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 |
| +#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 |
| +#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON |
| +#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 |
| +#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 |
| +#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON |
| +#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 |
| +#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 |
| +#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON |
| +#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 |
| +#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 |
| +#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON |
| +#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 |
| +#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 |
| +#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON |
| +#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 |
| +#define MT6359P_RG_LDO_VCN33_1_EN_0_MASK 0x1 |
| +#define MT6359P_RG_LDO_VCN33_1_EN_0_SHIFT 0 |
| +#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON |
| +#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW |
| +#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 |
| +#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 |
| +#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 |
| +#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON |
| +#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW |
| +#define MT6359P_RG_LDO_VCN33_2_EN_1_MASK 0x1 |
| +#define MT6359P_RG_LDO_VCN33_2_EN_1_SHIFT 15 |
| +#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 |
| +#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 |
| +#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON |
| +#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 |
| +#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON |
| +#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 |
| +#define MT6359P_RG_LDO_VA09_EN_SHIFT 0 |
| +#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON |
| +#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 |
| +#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 |
| +#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON |
| +#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 |
| +#define MT6359P_RG_LDO_VA12_EN_SHIFT 0 |
| +#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON |
| +#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 |
| +#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON |
| +#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 |
| +#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON |
| +#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 |
| +#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 |
| +#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON |
| +#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 |
| +#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 |
| +#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON |
| +#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 |
| +#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 |
| +#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON |
| +#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 |
| +#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 |
| +#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON |
| +#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 |
| +#define MT6359P_RG_LDO_VUSB_EN_0_MASK 0x1 |
| +#define MT6359P_RG_LDO_VUSB_EN_0_SHIFT 0 |
| +#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON |
| +#define MT6359P_RG_LDO_VUSB_EN_1_ADDR MT6359P_LDO_VUSB_MULTI_SW |
| +#define MT6359P_RG_LDO_VUSB_EN_1_MASK 0x1 |
| +#define MT6359P_RG_LDO_VUSB_EN_1_SHIFT 15 |
| +#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 |
| +#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 |
| +#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON |
| +#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 |
| +#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 |
| +#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON |
| +#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 |
| +#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON |
| +#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 |
| +#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 |
| +#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON |
| +#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 |
| +#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 |
| +#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON |
| +#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 |
| +#define MT6359P_RG_LDO_VM18_EN_SHIFT 0 |
| +#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON |
| +#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 |
| +#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 |
| +#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON |
| +#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 |
| +#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON |
| +#define MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_VOSEL1 |
| +#define MT6359P_DA_VSRAM_PROC1_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VSRAM_PROC1_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 |
| +#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON |
| +#define MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_VOSEL1 |
| +#define MT6359P_DA_VSRAM_PROC2_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VSRAM_PROC2_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 |
| +#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON |
| +#define MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_VOSEL1 |
| +#define MT6359P_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VSRAM_OTHERS_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR \ |
| + MT6359P_LDO_VSRAM_OTHERS_SSHUB |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR \ |
| + MT6359P_LDO_VSRAM_OTHERS_SSHUB |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F |
| +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 |
| +#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 |
| +#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON |
| +#define MT6359P_DA_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_VOSEL1 |
| +#define MT6359P_DA_VSRAM_MD_VOSEL_MASK 0x7F |
| +#define MT6359P_DA_VSRAM_MD_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 |
| +#define MT6359P_RG_VCN33_1_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VCN33_1_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 |
| +#define MT6359P_RG_VCN33_2_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VCN33_2_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VEMC_VOSEL_ADDR MT6359P_VEMC_ANA_CON0 |
| +#define MT6359P_RG_VEMC_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VEMC_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 |
| +#define MT6359P_RG_VSIM1_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VSIM1_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 |
| +#define MT6359P_RG_VSIM2_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VSIM2_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 |
| +#define MT6359P_RG_VIO28_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VIO28_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 |
| +#define MT6359P_RG_VIBR_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VIBR_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 |
| +#define MT6359P_RG_VRF18_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VRF18_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 |
| +#define MT6359P_RG_VEFUSE_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VEFUSE_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 |
| +#define MT6359P_RG_VCAMIO_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VCAMIO_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 |
| +#define MT6359P_RG_VIO18_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VIO18_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 |
| +#define MT6359P_RG_VM18_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VM18_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 |
| +#define MT6359P_RG_VUFS_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VUFS_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 |
| +#define MT6359P_RG_VRF12_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VRF12_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 |
| +#define MT6359P_RG_VCN13_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VCN13_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VA09_ANA_CON0 |
| +#define MT6359P_RG_VA09_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VA09_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 |
| +#define MT6359P_RG_VA12_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VA12_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 |
| +#define MT6359P_RG_VXO22_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VXO22_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 |
| +#define MT6359P_RG_VRFCK_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VRFCK_VOSEL_SHIFT 8 |
| +#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 |
| +#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF |
| +#define MT6359P_RG_VBBCK_VOSEL_SHIFT 8 |
| +#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP |
| +#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY |
| + |
| +#define TMA_KEY 0x9CA6 |
| + |
| +#endif /* __MFD_MT6359P_REGISTERS_H__ */ |
| diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h |
| index 949268581b369a910404dd0a3e00e66f2f2dba09..56f210eebc541612f01e953c7e221bdad7c3f2e0 100644 |
| --- a/include/linux/mfd/mt6397/core.h |
| +++ b/include/linux/mfd/mt6397/core.h |
| @@ -13,6 +13,7 @@ |
| enum chip_id { |
| MT6323_CHIP_ID = 0x23, |
| MT6358_CHIP_ID = 0x58, |
| + MT6359_CHIP_ID = 0x59, |
| MT6391_CHIP_ID = 0x91, |
| MT6397_CHIP_ID = 0x97, |
| }; |
| diff --git a/include/linux/regulator/mt6315-regulator.h b/include/linux/regulator/mt6315-regulator.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..8d1322c664a4713abdaedb55910f77fdee60d0c9 |
| --- /dev/null |
| +++ b/include/linux/regulator/mt6315-regulator.h |
| @@ -0,0 +1,53 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2020 MediaTek Inc. |
| + */ |
| + |
| +#ifndef __LINUX_REGULATOR_MT6315_H |
| +#define __LINUX_REGULATOR_MT6315_H |
| + |
| +#define MT6315_SLAVE_ID_3 3 |
| +#define MT6315_SLAVE_ID_6 6 |
| +#define MT6315_SLAVE_ID_7 7 |
| + |
| +enum { |
| + MT6315_ID_6_VBUCK1 = 0, |
| + MT6315_ID_6_VBUCK3, |
| + MT6315_ID_6_MAX, |
| +}; |
| + |
| +enum { |
| + MT6315_ID_7_VBUCK1 = 0, |
| + MT6315_ID_7_VBUCK3, |
| + MT6315_ID_7_MAX, |
| +}; |
| + |
| +enum { |
| + MT6315_ID_3_VBUCK1 = 0, |
| + MT6315_ID_3_VBUCK3, |
| + MT6315_ID_3_VBUCK4, |
| + MT6315_ID_3_MAX, |
| +}; |
| + |
| +/* Register */ |
| +#define MT6315_SWCID_H 0xb |
| +#define MT6315_TOP2_ELR7 0x139 |
| +#define MT6315_TOP_TMA_KEY 0x39f |
| +#define MT6315_TOP_TMA_KEY_H 0x3a0 |
| +#define MT6315_BUCK_TOP_CON0 0x1440 |
| +#define MT6315_BUCK_TOP_CON1 0x1443 |
| +#define MT6315_BUCK_TOP_ELR0 0x1449 |
| +#define MT6315_BUCK_TOP_ELR4 0x144d |
| +#define MT6315_BUCK_TOP_ELR6 0x144f |
| +#define MT6315_BUCK_VBUCK1_DBG0 0x1499 |
| +#define MT6315_BUCK_VBUCK1_DBG4 0x149d |
| +#define MT6315_BUCK_VBUCK3_DBG0 0x1599 |
| +#define MT6315_BUCK_VBUCK3_DBG4 0x159d |
| +#define MT6315_BUCK_VBUCK4_DBG0 0x1619 |
| +#define MT6315_BUCK_VBUCK4_DBG4 0x161d |
| +#define MT6315_BUCK_TOP_4PHASE_ANA_CON42 0x16b1 |
| + |
| +#define PROTECTION_KEY_H 0x9C |
| +#define PROTECTION_KEY 0xEA |
| + |
| +#endif /* __LINUX_REGULATOR_MT6315_H */ |
| diff --git a/include/linux/regulator/mt6359-regulator.h b/include/linux/regulator/mt6359-regulator.h |
| new file mode 100644 |
| index 0000000000000000000000000000000000000000..6b171730837bc5825e53dd904a7e4ba74042e9ff |
| --- /dev/null |
| +++ b/include/linux/regulator/mt6359-regulator.h |
| @@ -0,0 +1,58 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +/* |
| + * Copyright (c) 2019 MediaTek Inc. |
| + */ |
| + |
| +#ifndef __LINUX_REGULATOR_MT6359_H |
| +#define __LINUX_REGULATOR_MT6359_H |
| + |
| +enum { |
| + MT6359_ID_VS1 = 0, |
| + MT6359_ID_VGPU11, |
| + MT6359_ID_VMODEM, |
| + MT6359_ID_VPU, |
| + MT6359_ID_VCORE, |
| + MT6359_ID_VS2, |
| + MT6359_ID_VPA, |
| + MT6359_ID_VPROC2, |
| + MT6359_ID_VPROC1, |
| + MT6359_ID_VCORE_SSHUB, |
| + MT6359_ID_VAUD18 = 10, |
| + MT6359_ID_VSIM1, |
| + MT6359_ID_VIBR, |
| + MT6359_ID_VRF12, |
| + MT6359_ID_VUSB, |
| + MT6359_ID_VSRAM_PROC2, |
| + MT6359_ID_VIO18, |
| + MT6359_ID_VCAMIO, |
| + MT6359_ID_VCN18, |
| + MT6359_ID_VFE28, |
| + MT6359_ID_VCN13, |
| + MT6359_ID_VCN33_1_BT, |
| + MT6359_ID_VCN33_1_WIFI, |
| + MT6359_ID_VAUX18, |
| + MT6359_ID_VSRAM_OTHERS, |
| + MT6359_ID_VEFUSE, |
| + MT6359_ID_VXO22, |
| + MT6359_ID_VRFCK, |
| + MT6359_ID_VBIF28, |
| + MT6359_ID_VIO28, |
| + MT6359_ID_VEMC, |
| + MT6359_ID_VCN33_2_BT, |
| + MT6359_ID_VCN33_2_WIFI, |
| + MT6359_ID_VA12, |
| + MT6359_ID_VA09, |
| + MT6359_ID_VRF18, |
| + MT6359_ID_VSRAM_MD, |
| + MT6359_ID_VUFS, |
| + MT6359_ID_VM18, |
| + MT6359_ID_VBBCK, |
| + MT6359_ID_VSRAM_PROC1, |
| + MT6359_ID_VSIM2, |
| + MT6359_ID_VSRAM_OTHERS_SSHUB, |
| + MT6359_ID_RG_MAX, |
| +}; |
| + |
| +#define MT6359_MAX_REGULATOR MT6359_ID_RG_MAX |
| + |
| +#endif /* __LINUX_REGULATOR_MT6359_H */ |
| diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h |
| deleted file mode 100644 |
| index fd25f01485660e0401cb9a4be8dbc5ac8e3eecfa..0000000000000000000000000000000000000000 |
| --- a/include/linux/soc/mediatek/infracfg.h |
| +++ /dev/null |
| @@ -1,39 +0,0 @@ |
| -/* SPDX-License-Identifier: GPL-2.0 */ |
| -#ifndef __SOC_MEDIATEK_INFRACFG_H |
| -#define __SOC_MEDIATEK_INFRACFG_H |
| - |
| -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) |
| -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) |
| -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) |
| -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) |
| -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) |
| -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) |
| -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) |
| -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) |
| -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) |
| -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) |
| -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) |
| -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) |
| -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) |
| -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) |
| -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) |
| -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) |
| -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) |
| -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) |
| - |
| -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) |
| -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) |
| -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) |
| - |
| -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) |
| -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) |
| -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ |
| - BIT(28)) |
| -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ |
| - BIT(7) | BIT(8)) |
| - |
| -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, |
| - bool reg_update); |
| -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, |
| - bool reg_update); |
| -#endif /* __SOC_MEDIATEK_INFRACFG_H */ |
| diff --git a/include/linux/spmi.h b/include/linux/spmi.h |
| index 394a3f68bad5df36a1d0ad15c179e9b88adca7e6..729bcbf9f5ad1197818728b8546668fb64addd0e 100644 |
| --- a/include/linux/spmi.h |
| +++ b/include/linux/spmi.h |
| @@ -138,6 +138,7 @@ struct spmi_driver { |
| struct device_driver driver; |
| int (*probe)(struct spmi_device *sdev); |
| void (*remove)(struct spmi_device *sdev); |
| + void (*shutdown)(struct spmi_device *sdev); |
| }; |
| |
| static inline struct spmi_driver *to_spmi_driver(struct device_driver *d) |
| diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h |
| index 5a34b87d89e32fdc7bbea9a138fcc5f80c482f99..7d0ae3fd59439624f16cfc6acb7c882e8922be4f 100644 |
| --- a/include/soc/mediatek/smi.h |
| +++ b/include/soc/mediatek/smi.h |
| @@ -11,13 +11,12 @@ |
| |
| #ifdef CONFIG_MTK_SMI |
| |
| -#define MTK_LARB_NR_MAX 16 |
| - |
| #define MTK_SMI_MMU_EN(port) BIT(port) |
| |
| struct mtk_smi_larb_iommu { |
| struct device *dev; |
| unsigned int mmu; |
| + unsigned int bank[32]; |
| }; |
| |
| /* |