blob: a69157e8bedfcfd5574aa1b41541683faccb8df5 [file] [log] [blame]
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE pkgmetadata SYSTEM "">
<maintainer type="person" proxied="yes">
<name>Huang Rui</name>
<maintainer type="project">
<name>Gentoo Electronics Project</name>
<maintainer type="project" proxied="proxy">
<name>Proxy Maintainers</name>
<remote-id type="github">steveicarus/iverilog</remote-id>
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2001.