From 1fdfeaa7cdd6d2630dede50f53622b16485bed81 Mon Sep 17 00:00:00 2001
From: Sreerenj Balachandran <sreerenj.balachandran@intel.com>
Date: Fri, 12 Jun 2020 13:57:51 -0700
Subject: [PATCH] Decoder: VP9: GEN9: Disable HPR VP9 mode switch to avoid GPU
 hang

Without having the HprVp9ModeSwitchEco disabled, the gen9 devices
cause gpu to hang while decoding tiled 4k vp9 streams for a
longer period. This particular chicken bit has been set in the
legacy i965 driver to avoid random gpu hangs.

Fixes #974
---
 .../agnostic/gen9_kbl/hw/vdbox/mhw_vdbox_hcp_g9_kbl.cpp       | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/media_driver/agnostic/gen9_kbl/hw/vdbox/mhw_vdbox_hcp_g9_kbl.cpp b/media_driver/agnostic/gen9_kbl/hw/vdbox/mhw_vdbox_hcp_g9_kbl.cpp
index ca57f073d24c..ebb8896a2b4e 100644
--- a/media_driver/agnostic/gen9_kbl/hw/vdbox/mhw_vdbox_hcp_g9_kbl.cpp
+++ b/media_driver/agnostic/gen9_kbl/hw/vdbox/mhw_vdbox_hcp_g9_kbl.cpp
@@ -275,6 +275,10 @@ MOS_STATUS MhwVdboxHcpInterfaceG9Kbl::AddHcpPipeModeSelectCmd(
 
     m_cpInterface->SetProtectionSettingsForMfxPipeModeSelect((uint32_t *)cmd);
 
+    // Without having the HprVp9ModeSwitchEco disabled, the gen9 devices
+    // cause gpu to hang while decoding tiled 4k vp9 streams
+    cmd->DW4.HprVp9ModeSwitchEcoDisable = 1;
+
     cmd->DW1.PakPipelineStreamoutEnable = params->bStreamOutEnabled;
     cmd->DW1.AdvancedRateControlEnable = params->bAdvancedRateControlEnable;
 
-- 
2.17.1