dev-embedded/ti50-sdk/files/llvm11-10122020-soteria.patch

This patch enables custom RISCV instructions in our version of LLVM.

These instructions aren't part of the standard RISCV spec, so upstreaming seems
nontrivial.

new file mode 100644
--- /dev/null
+++ b/clang/include/clang/Basic/BuiltinsSoteria.def
@@ -0,0 +1,24 @@
+//===-- BuiltinsSoteria.def - Soteria Builtin function database --*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the Soteria-specific builtin function database. Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+// The format of this database matches clang/Basic/Builtins.def.
+
+// The builtins below are not autogenerated from iset.py.
+// Make sure you do not overwrite these.
+
+BUILTIN(__builtin_riscv_soteria_grev, "iii", "nc")
+BUILTIN(__builtin_riscv_soteria_bitc, "iii", "nc")
+BUILTIN(__builtin_riscv_soteria_bits, "iii", "nc")
+BUILTIN(__builtin_riscv_soteria_fls, "ii", "nc")
+
+#undef BUILTIN
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -300,6 +300,15 @@ namespace clang {
   };
   }
 
+  namespace RISCV {
+  enum {
+    LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+  #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+  #include "clang/Basic/BuiltinsSoteria.def"
+    LastTSBuiltin
+  };
+  }
+
   /// SystemZ builtins
   namespace SystemZ {
     enum {
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -11,6 +11,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
 #include "clang/Basic/MacroBuilder.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/TargetParser.h"
@@ -18,6 +20,16 @@
 using namespace clang;
 using namespace clang::targets;
 
+const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)                                               \
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
+#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
+  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsSoteria.def"
+};
+
 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
       // Integer registers
@@ -129,6 +141,14 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (HasB)
     Builder.defineMacro("__riscv_bitmanip");
+
+  if (HasSoteria)
+    Builder.defineMacro("__soteria");
+}
+
+ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
+  return llvm::makeArrayRef(BuiltinInfo, clang::RISCV::LastTSBuiltin -
+                            Builtin::FirstTSBuiltin);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -144,6 +164,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
       .Case("d", HasD)
       .Case("c", HasC)
       .Case("experimental-b", HasB)
+      .Case("xsoteria", HasSoteria)
       .Default(false);
 }
 
@@ -163,6 +184,8 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       HasC = true;
     else if (Feature == "+experimental-b")
       HasB = true;
+    else if (Feature == "+xsoteria")
+      HasSoteria = true;
   }
 
   return true;
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -31,11 +31,13 @@ protected:
   bool HasD;
   bool HasC;
   bool HasB;
+  bool HasSoteria;
+  static const Builtin::Info BuiltinInfo[];
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-        HasD(false), HasC(false), HasB(false) {
+        HasD(false), HasC(false), HasB(false), HasSoteria(false) {
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
@@ -55,7 +57,7 @@ public:
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
-  ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
+  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::VoidPtrBuiltinVaList;
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -4534,6 +4534,9 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF,
   case llvm::Triple::nvptx:
   case llvm::Triple::nvptx64:
     return CGF->EmitNVPTXBuiltinExpr(BuiltinID, E);
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    return CGF->EmitRISCVBuiltinExpr(BuiltinID, E);
   case llvm::Triple::wasm32:
   case llvm::Triple::wasm64:
     return CGF->EmitWebAssemblyBuiltinExpr(BuiltinID, E);
@@ -16100,6 +16103,14 @@ RValue CodeGenFunction::EmitBuiltinAlignTo(const CallExpr *E, bool AlignUp) {
   return RValue::get(Result);
 }
 
+Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
+                                             const CallExpr *E) {
+  switch (BuiltinID) {
+    default:
+      return nullptr;
+  }
+}
+
 Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
                                                    const CallExpr *E) {
   switch (BuiltinID) {
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4068,6 +4068,7 @@ public:
   llvm::Value *EmitAMDGPUBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitSystemZBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
+  llvm::Value *EmitRISCVBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
                                           const CallExpr *E);
   llvm::Value *EmitHexagonBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -73,6 +73,9 @@ static bool isSupportedExtension(StringRef Ext) {
     return true;
 
   // LLVM does not support "sx", "s" nor "x" extensions.
+  if (Ext == "xsoteria") {
+    return true;
+  }
   return false;
 }
 
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-soteria.c
@@ -0,0 +1,53 @@
+// RUN: %clang_cc1 -triple=riscv32-unknown-none -target-feature +xsoteria -O3 \
+// RUN:   -S -o - %s | FileCheck %s -check-prefix=RV32S
+
+int intrinsics(int x) {
+  // RV32S-LABEL: intrinsics:
+
+  int v1 = __builtin_riscv_soteria_grev(x, x);
+  // RV32S: grev
+
+  int v2 = __builtin_riscv_soteria_grev(x, 1);
+  // RV32S: grevi
+
+  int v3 = __builtin_riscv_soteria_bitc(x, x);
+  // RV32S: bitc
+
+  int v4 = __builtin_riscv_soteria_bitc(x, 2);
+  // RV32S: bitci
+
+  int v5 = __builtin_riscv_soteria_bits(x, x);
+  // RV32S: bits
+
+  int v6 = __builtin_riscv_soteria_bits(x, 3);
+  // RV32S: bitsi
+
+  int v7 = __builtin_popcount(x);
+  // RV32S: pcnt
+
+  int v8 = __builtin_clz(x);
+  // RV32S: clz
+
+  int v9 = __builtin_riscv_soteria_fls(x);
+  // RV32S: fls
+
+  return v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8 + v9;
+}
+
+int bitc_pattern(int a, int b) {
+  // RV32S-LABEL: bitc_pattern:
+
+  return a & ~(1 << b);
+  // RV32S-NOT: and
+  // RV32S: bitc a0, a0, a1
+  // RV32S-NEXT: ret
+}
+
+int bits_pattern(int a, int b) {
+  // RV32S-LABEL: bits_pattern:
+
+  return a | (1 << b);
+  // RV32S-NOT: or
+  // RV32S: bits a0, a0, a1
+  // RV32S-NEXT: ret
+}
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -622,7 +622,9 @@ enum : unsigned {
   EF_RISCV_FLOAT_ABI_SINGLE = 0x0002,
   EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004,
   EF_RISCV_FLOAT_ABI_QUAD = 0x0006,
-  EF_RISCV_RVE = 0x0008
+  EF_RISCV_RVE = 0x0008,
+  // 0x0010 is used by melvin
+  EF_RISCV_SOTERIA = 0x0020
 };
 
 // ELF Relocation types for RISC-V
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -65,4 +65,23 @@ let TargetPrefix = "riscv" in {
   // @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
   defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
 
+class SoteriaIntrinsic<string name,
+                       list<LLVMType> ret_types,
+                       list<LLVMType> param_types = [],
+                       list<IntrinsicProperty> properties = []>
+  : GCCBuiltin<"__builtin_riscv_soteria_"#name>,
+    Intrinsic<ret_types, param_types, properties>;
+
+def int_riscv_soteria_grev
+  : SoteriaIntrinsic<"grev", [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                     [IntrNoMem]>;
+def int_riscv_soteria_bitc
+  : SoteriaIntrinsic<"bitc", [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                     [IntrNoMem]>;
+def int_riscv_soteria_bits
+  : SoteriaIntrinsic<"bits", [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                     [IntrNoMem]>;
+def int_riscv_soteria_fls
+  : SoteriaIntrinsic<"fls", [llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+
 } // TargetPrefix = "riscv"
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -293,6 +293,9 @@ SubtargetFeatures ELFObjectFileBase::getRISCVFeatures() const {
   if (PlatformFlags & ELF::EF_RISCV_RVC) {
     Features.AddFeature("c");
   }
+  if (PlatformFlags & ELF::EF_RISCV_SOTERIA) {
+    Features.AddFeature("xsoteria");
+  }
 
   // Add features according to the ELF attribute section.
   // If there are any unrecognized features, ignore them.
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -37,6 +37,8 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
 
   if (Features[RISCV::FeatureStdExtC])
     EFlags |= ELF::EF_RISCV_RVC;
+  if (Features[RISCV::FeatureSoteria])
+    EFlags |= ELF::EF_RISCV_SOTERIA;
 
   switch (ABI) {
   case RISCVABI::ABI_ILP32:
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -164,6 +164,13 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                        "RV32I Base Instruction Set">;
 
+def FeatureSoteria
+    : SubtargetFeature<"xsoteria", "HasExtSoteria", "true",
+                       "'Soteria' (Soteria non-standard instructions)">;
+def HasExtSoteria : Predicate<"Subtarget->hasExtSoteria()">,
+                               AssemblerPredicate<(all_of FeatureSoteria),
+			       "'Soteria' (Soteria non-standard instructions)">;
+
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;
 
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -157,7 +157,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (!Subtarget.hasStdExtZbp())
     setOperationAction(ISD::BSWAP, XLenVT, Expand);
 
-  if (!Subtarget.hasStdExtZbb()) {
+  if (Subtarget.hasExtSoteria()) {
+    setOperationAction(ISD::CTPOP, XLenVT, Legal);
+    setOperationAction(ISD::CTLZ, XLenVT, Legal);
+    setOperationAction(ISD::CTTZ, XLenVT, Expand);
+  } else if (!Subtarget.hasStdExtZbb()) {
     setOperationAction(ISD::CTTZ, XLenVT, Expand);
     setOperationAction(ISD::CTLZ, XLenVT, Expand);
     setOperationAction(ISD::CTPOP, XLenVT, Expand);
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -818,3 +818,7 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
                                         RISCVII::MO_CALL));
   return It;
 }
+
+bool RISCVInstrInfo::isSoteria() const {
+  return STI.hasExtSoteria();
+}
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -130,6 +130,8 @@ public:
   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator &It, MachineFunction &MF,
                      const outliner::Candidate &C) const override;
+  bool isSoteria() const;
+
 protected:
   const RISCVSubtarget &STI;
 };
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1178,3 +1178,4 @@ include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
+include "RISCVInstrInfoSoteria.td"
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSoteria.td
@@ -0,0 +1,96 @@
+//===-- RISCVInstrInfoSoteria.td - Soteria instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions that are specific to the
+// Soteria architecture.
+//
+//===----------------------------------------------------------------------===//
+
+
+def OPC_GREV  : RISCVOpcode<0b0101011>;
+def OPC_GREVI : RISCVOpcode<0b0001011>;
+def OPC_BITC  : RISCVOpcode<0b0101011>;
+def OPC_BITCI : RISCVOpcode<0b0001011>;
+def OPC_BITS  : RISCVOpcode<0b0101011>;
+def OPC_BITSI : RISCVOpcode<0b0001011>;
+def OPC_PCNT  : RISCVOpcode<0b0001011>;
+def OPC_CLZ   : RISCVOpcode<0b0001011>;
+def OPC_FLS   : RISCVOpcode<0b0001011>;
+
+// Some Soteria specific instructions take 2 register operands with a normal R
+// style encoding.
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+class SoteriaInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, string opcodestr>
+  : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+// Other soteria instructions take a single register operand and a 5 bit
+// immediate value.
+class SoteriaInstI<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, string opcodestr>
+  : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), opcodestr, "$rd, $rs1, $imm5", [], InstFormatOther> {
+  bits<5> rs1;
+  bits<5> imm5;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = imm5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+// PCNT, CLZ and FLS instructions only have a single source operand.
+class SoteriaInst<bits<12> funct12, bits<3> funct3, RISCVOpcode opcode, string opcodestr>
+  : RVInst<(outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1", [], InstFormatOther> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-20} = funct12;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+}
+
+let Predicates = [HasExtSoteria], hasNoSchedulingInfo = 1 in {
+def SOT_GREV  : SoteriaInstR<0b0000000, 0b000, OPC_GREV, "grev">;
+def SOT_GREVI : SoteriaInstI<0b0000000, 0b000, OPC_GREVI, "grevi">;
+def SOT_BITC  : SoteriaInstR<0b0000000, 0b001, OPC_BITC, "bitc">;
+def SOT_BITCI : SoteriaInstI<0b0000000, 0b001, OPC_BITCI, "bitci">;
+def SOT_BITS  : SoteriaInstR<0b0100000, 0b001, OPC_BITS, "bits">;
+def SOT_BITSI : SoteriaInstI<0b0100000, 0b001, OPC_BITSI, "bitsi">;
+def SOT_PCNT  : SoteriaInst<0b000000000000, 0b011, OPC_PCNT, "pcnt">;
+def SOT_CLZ   : SoteriaInst<0b010000000000, 0b010, OPC_CLZ, "clz">;
+def SOT_FLS   : SoteriaInst<0b000000000000, 0b010, OPC_FLS, "fls">;
+
+}
+
+let Predicates = [HasExtSoteria] in {
+def : Pat<(int_riscv_soteria_grev GPR:$rs1, GPR:$rs2),
+          (SOT_GREV GPR:$rs1, GPR:$rs2)>;
+def : Pat<(int_riscv_soteria_grev GPR:$rs1, uimm5:$imm5),
+          (SOT_GREVI GPR:$rs1, uimm5:$imm5)>;
+def : Pat<(int_riscv_soteria_bitc GPR:$rs1, GPR:$rs2),
+          (SOT_BITC GPR:$rs1, GPR:$rs2)>;
+def : Pat<(int_riscv_soteria_bitc GPR:$rs1, uimm5:$imm5),
+          (SOT_BITCI GPR:$rs1, uimm5:$imm5)>;
+def : Pat<(int_riscv_soteria_bits GPR:$rs1, GPR:$rs2),
+          (SOT_BITS GPR:$rs1, GPR:$rs2)>;
+def : Pat<(int_riscv_soteria_bits GPR:$rs1, uimm5:$imm5),
+          (SOT_BITSI GPR:$rs1, uimm5:$imm5)>;
+def : Pat<(ctpop GPR:$rs1), (SOT_PCNT GPR:$rs1)>;
+def : Pat<(ctlz GPR:$rs1), (SOT_CLZ GPR:$rs1)>;
+def : Pat<(int_riscv_soteria_fls GPR:$rs1), (SOT_FLS GPR:$rs1)>;
+
+def : Pat<(and (xor (shl 1, GPR:$rs2), -1), GPR:$rs1),
+          (SOT_BITC GPR:$rs1, GPR:$rs2)>;
+def : Pat<(or (shl 1, GPR:$rs2), GPR:$rs1),
+          (SOT_BITS GPR:$rs1, GPR:$rs2)>;
+}
+
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -53,6 +53,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtV = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
+  bool HasExtSoteria = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
@@ -114,6 +115,7 @@ public:
   bool hasStdExtV() const { return HasStdExtV; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
+  bool hasExtSoteria() const { return HasExtSoteria; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -370,3 +370,6 @@ def : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def : SysReg<"vlenb", 0xC22>;
+
+include "SoteriaSystemOperands.td"
+
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/RISCV/SoteriaSystemOperands.td
@@ -0,0 +1,51 @@
+//===-----------------------------------------------
+// Soteria Non-Standard CSRs
+//===-----------------------------------------------
+def : SysReg<"mgpscratch0",  0x7C0>;
+def : SysReg<"mgpscratch1",  0x7C1>;
+def : SysReg<"mgpscratch2",  0x7C2>;
+def : SysReg<"mgpscratch3",  0x7C3>;
+def : SysReg<"mgpscratch4",  0x7C4>;
+def : SysReg<"mgpscratch5",  0x7C5>;
+def : SysReg<"mgpscratch6",  0x7C6>;
+def : SysReg<"mgpscratch7",  0x7C7>;
+def : SysReg<"mgpscratch8",  0x7C8>;
+def : SysReg<"mgpscratch9",  0x7C9>;
+def : SysReg<"mgpscratch10", 0x7CA>;
+def : SysReg<"mgpscratch11", 0x7CB>;
+def : SysReg<"mgpscratch12", 0x7CC>;
+def : SysReg<"mgpscratch13", 0x7CD>;
+def : SysReg<"mgpscratch14", 0x7CE>;
+def : SysReg<"mgpscratch15", 0x7CF>;
+def : SysReg<"mnmivec",      0x7D0>;
+def : SysReg<"ualert",       0x802>;
+
+//===-----------------------------------------------
+// Soteria Attack Countermeasure CSRs
+//===-----------------------------------------------
+def : SysReg<"mx0",          0xBC0>;
+
+//===-----------------------------------------------
+// Soteria Control Flow Integrity CSRs
+//===-----------------------------------------------
+def : SysReg<"ucfic",        0x807>;
+def : SysReg<"ucfiseed0",    0x803>;
+def : SysReg<"ucfiseed1",    0x80A>;
+def : SysReg<"ucfichk0",     0x80E>;
+def : SysReg<"ucfichk1",     0x806>;
+def : SysReg<"ucfimix0",     0x805>;
+def : SysReg<"ucfimix1",     0x801>;
+def : SysReg<"ucfisave0",    0x804>;
+def : SysReg<"ucfisave1",    0x80F>;
+
+//===-----------------------------------------------
+// Soteria Pseudorandom Decoy Instruction CSRs
+//===-----------------------------------------------
+def : SysReg<"mpigrate",     0xBC9>;
+def : SysReg<"mpigseed0",    0xBCE>;
+def : SysReg<"mpigseed1",    0xBCC>;
+
+//===-----------------------------------------------
+// Soteria Machine State Wipe
+//===-----------------------------------------------
+def : SysReg<"uswc",         0x800>;
\ No newline at end of file
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/builtins-soteria.ll
@@ -0,0 +1,94 @@
+; RUN: llc -O3 -verify-machineinstrs --show-mc-encoding < %s \
+; RUN: | FileCheck %s -check-prefix=RV32S
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-unknown-elf"
+
+define dso_local i32 @grev(i32 %a, i32 %b) local_unnamed_addr #0 {
+; RV32S-LABEL: grev:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.grev(i32 %a, i32 %b)
+  ; RV32S: grev a0, a0, a1 # encoding: [0x2b,0x05,0xb5,0x00]
+  ret i32 %0
+}
+
+define dso_local i32 @grevi(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: grevi:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.grev(i32 %a, i32 16)
+  ; RV32S: grevi a0, a0, 16 # encoding: [0x0b,0x05,0x05,0x01]
+  ret i32 %0
+}
+
+define dso_local i32 @bitc(i32 %a, i32 %b) local_unnamed_addr #0 {
+; RV32S-LABEL: bitc:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.bitc(i32 %a, i32 %b)
+  ; RV32S: bitc a0, a0, a1 # encoding: [0x2b,0x15,0xb5,0x00]
+  ret i32 %0
+}
+
+define dso_local i32 @bitci(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: bitci:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.bitc(i32 %a, i32 18)
+  ; RV32S: bitci a0, a0, 18 # encoding: [0x0b,0x15,0x25,0x01]
+  ret i32 %0
+}
+
+define dso_local i32 @bits(i32 %a, i32 %b) local_unnamed_addr #0 {
+; RV32S-LABEL: bits:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.bits(i32 %a, i32 %b)
+  ; RV32S: bits a0, a0, a1 # encoding: [0x2b,0x15,0xb5,0x40]
+  ret i32 %0
+}
+
+define dso_local i32 @bitsi(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: bitsi:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.bits(i32 %a, i32 31)
+  ; RV32S: bitsi a0, a0, 31 # encoding: [0x0b,0x15,0xf5,0x41]
+  ret i32 %0
+}
+
+define dso_local i32 @pcnt(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: pcnt:
+entry:
+  %0 = tail call i32 @llvm.ctpop.i32(i32 %a), !range !3
+  ; RV32S: pcnt a0, a0 # encoding: [0x0b,0x35,0x05,0x00]
+  ret i32 %0
+}
+
+define dso_local i32 @clz(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: clz:
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true), !range !3
+  ; RV32S: clz a0, a0 # encoding: [0x0b,0x25,0x05,0x40]
+  ret i32 %0
+}
+
+define dso_local i32 @fls(i32 %a) local_unnamed_addr #0 {
+; RV32S-LABEL: fls:
+entry:
+  %0 = tail call i32 @llvm.riscv.soteria.fls(i32 %a)
+  ; RV32S: fls a0, a0 # encoding: [0x0b,0x25,0x05,0x00]
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.soteria.grev(i32, i32) #1
+declare i32 @llvm.riscv.soteria.bitc(i32, i32) #1
+declare i32 @llvm.riscv.soteria.bits(i32, i32) #1
+declare i32 @llvm.ctpop.i32(i32) #1
+declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
+declare i32 @llvm.riscv.soteria.fls(i32) #1
+
+attributes #0 = { nounwind readnone "target-features"="+c,+m,+relax,+xsoteria" }
+attributes #1 = { nounwind readnone }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"target-abi", !"ilp32"}
+!3 = !{i32 0, i32 33}
+
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/soteria-csr-names.s
@@ -0,0 +1,488 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+###################################################
+# Soteria Non-Standard CSRs
+###################################################
+
+# mgpscratch0
+# name
+# CHECK-INST: csrrs t1, mgpscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch0
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch0
+# name
+csrrs t1, mgpscratch0, zero
+# uimm12
+csrrs t2, 0x7C0, zero
+
+# mgpscratch1
+# name
+# CHECK-INST: csrrs t1, mgpscratch1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch1
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch1
+# name
+csrrs t1, mgpscratch1, zero
+# uimm12
+csrrs t2, 0x7C1, zero
+
+# mgpscratch2
+# name
+# CHECK-INST: csrrs t1, mgpscratch2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch2
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch2
+# name
+csrrs t1, mgpscratch2, zero
+# uimm12
+csrrs t2, 0x7C2, zero
+
+# mgpscratch3
+# name
+# CHECK-INST: csrrs t1, mgpscratch3, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch3
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch3, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch3
+# name
+csrrs t1, mgpscratch3, zero
+# uimm12
+csrrs t2, 0x7C3, zero
+
+# mgpscratch4
+# name
+# CHECK-INST: csrrs t1, mgpscratch4, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch4
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch4, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch4
+# name
+csrrs t1, mgpscratch4, zero
+# uimm12
+csrrs t2, 0x7C4, zero
+
+# mgpscratch5
+# name
+# CHECK-INST: csrrs t1, mgpscratch5, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch5
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch5, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch5
+# name
+csrrs t1, mgpscratch5, zero
+# uimm12
+csrrs t2, 0x7C5, zero
+
+# mgpscratch6
+# name
+# CHECK-INST: csrrs t1, mgpscratch6, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch6
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch6, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch6
+# name
+csrrs t1, mgpscratch6, zero
+# uimm12
+csrrs t2, 0x7C6, zero
+
+# mgpscratch7
+# name
+# CHECK-INST: csrrs t1, mgpscratch7, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch7
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch7, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch7
+# name
+csrrs t1, mgpscratch7, zero
+# uimm12
+csrrs t2, 0x7C7, zero
+
+# mgpscratch8
+# name
+# CHECK-INST: csrrs t1, mgpscratch8, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch8
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch8, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch8
+# name
+csrrs t1, mgpscratch8, zero
+# uimm12
+csrrs t2, 0x7C8, zero
+
+# mgpscratch9
+# name
+# CHECK-INST: csrrs t1, mgpscratch9, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch9
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch9, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch9
+# name
+csrrs t1, mgpscratch9, zero
+# uimm12
+csrrs t2, 0x7C9, zero
+
+# mgpscratch10
+# name
+# CHECK-INST: csrrs t1, mgpscratch10, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch10
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch10, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch10
+# name
+csrrs t1, mgpscratch10, zero
+# uimm12
+csrrs t2, 0x7CA, zero
+
+# mgpscratch11
+# name
+# CHECK-INST: csrrs t1, mgpscratch11, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch11
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch11, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch11
+# name
+csrrs t1, mgpscratch11, zero
+# uimm12
+csrrs t2, 0x7CB, zero
+
+# mgpscratch12
+# name
+# CHECK-INST: csrrs t1, mgpscratch12, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch12
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch12, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch12
+# name
+csrrs t1, mgpscratch12, zero
+# uimm12
+csrrs t2, 0x7CC, zero
+
+# mgpscratch13
+# name
+# CHECK-INST: csrrs t1, mgpscratch13, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch13
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch13, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch13
+# name
+csrrs t1, mgpscratch13, zero
+# uimm12
+csrrs t2, 0x7CD, zero
+
+# mgpscratch14
+# name
+# CHECK-INST: csrrs t1, mgpscratch14, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch14
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch14, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch14
+# name
+csrrs t1, mgpscratch14, zero
+# uimm12
+csrrs t2, 0x7CE, zero
+
+# mgpscratch15
+# name
+# CHECK-INST: csrrs t1, mgpscratch15, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x7c]
+# CHECK-INST-ALIAS: csrr t1, mgpscratch15
+# uimm12
+# CHECK-INST: csrrs t2, mgpscratch15, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x7c]
+# CHECK-INST-ALIAS: csrr t2, mgpscratch15
+# name
+csrrs t1, mgpscratch15, zero
+# uimm12
+csrrs t2, 0x7CF, zero
+
+# mnmivec
+# name
+# CHECK-INST: csrrs t1, mnmivec, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7d]
+# CHECK-INST-ALIAS: csrr t1, mnmivec
+# uimm12
+# CHECK-INST: csrrs t2, mnmivec, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7d]
+# CHECK-INST-ALIAS: csrr t2, mnmivec
+# name
+csrrs t1, mnmivec, zero
+# uimm12
+csrrs t2, 0x7D0, zero
+
+# ualert
+# name
+# CHECK-INST: csrrs t1, ualert, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x80]
+# CHECK-INST-ALIAS: csrr t1, ualert
+# uimm12
+# CHECK-INST: csrrs t2, ualert, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x80]
+# CHECK-INST-ALIAS: csrr t2, ualert
+# name
+csrrs t1, ualert, zero
+# uimm12
+csrrs t2, 0x802, zero
+
+
+###################################################
+# Soteria Attack Countermeasure CSRs
+###################################################
+
+# mx0
+# name
+# CHECK-INST: csrrs t1, mx0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xbc]
+# CHECK-INST-ALIAS: csrr t1, mx0
+# uimm12
+# CHECK-INST: csrrs t2, mx0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xbc]
+# CHECK-INST-ALIAS: csrr t2, mx0
+# name
+csrrs t1, mx0, zero
+# uimm12
+csrrs t2, 0xBC0, zero
+
+###################################################
+# Soteria Control Flow Integrity CSRs
+###################################################
+
+# ucfic
+# name
+# CHECK-INST: csrrs t1, ucfic, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfic
+# uimm12
+# CHECK-INST: csrrs t2, ucfic, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfic
+# name
+csrrs t1, ucfic, zero
+# uimm12
+csrrs t2, 0x807, zero
+
+# ucfiseed0
+# name
+# CHECK-INST: csrrs t1, ucfiseed0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfiseed0
+# uimm12
+# CHECK-INST: csrrs t2, ucfiseed0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfiseed0
+# name
+csrrs t1, ucfiseed0, zero
+# uimm12
+csrrs t2, 0x803, zero
+
+# ucfiseed1
+# name
+# CHECK-INST: csrrs t1, ucfiseed1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfiseed1
+# uimm12
+# CHECK-INST: csrrs t2, ucfiseed1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfiseed1
+# name
+csrrs t1, ucfiseed1, zero
+# uimm12
+csrrs t2, 0x80A, zero
+
+# ucfichk0
+# name
+# CHECK-INST: csrrs t1, ucfichk0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfichk0
+# uimm12
+# CHECK-INST: csrrs t2, ucfichk0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfichk0
+# name
+csrrs t1, ucfichk0, zero
+# uimm12
+csrrs t2, 0x80E, zero
+
+# ucfichk1
+# name
+# CHECK-INST: csrrs t1, ucfichk1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfichk1
+# uimm12
+# CHECK-INST: csrrs t2, ucfichk1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfichk1
+# name
+csrrs t1, ucfichk1, zero
+# uimm12
+csrrs t2, 0x806, zero
+
+# ucfimix0
+# name
+# CHECK-INST: csrrs t1, ucfimix0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfimix0
+# uimm12
+# CHECK-INST: csrrs t2, ucfimix0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfimix0
+# name
+csrrs t1, ucfimix0, zero
+# uimm12
+csrrs t2, 0x805, zero
+
+# ucfimix1
+# name
+# CHECK-INST: csrrs t1, ucfimix1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfimix1
+# uimm12
+# CHECK-INST: csrrs t2, ucfimix1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfimix1
+# name
+csrrs t1, ucfimix1, zero
+# uimm12
+csrrs t2, 0x801, zero
+
+# ucfisave0
+# name
+# CHECK-INST: csrrs t1, ucfisave0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfisave0
+# uimm12
+# CHECK-INST: csrrs t2, ucfisave0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfisave0
+# name
+csrrs t1, ucfisave0, zero
+# uimm12
+csrrs t2, 0x804, zero
+
+# ucfisave0
+# name
+# CHECK-INST: csrrs t1, ucfisave0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfisave0
+# uimm12
+# CHECK-INST: csrrs t2, ucfisave0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfisave0
+# name
+csrrs t1, ucfisave0, zero
+# uimm12
+csrrs t2, 0x804, zero
+
+# ucfisave1
+# name
+# CHECK-INST: csrrs t1, ucfisave1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x80]
+# CHECK-INST-ALIAS: csrr t1, ucfisave1
+# uimm12
+# CHECK-INST: csrrs t2, ucfisave1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x80]
+# CHECK-INST-ALIAS: csrr t2, ucfisave1
+# name
+csrrs t1, ucfisave1, zero
+# uimm12
+csrrs t2, 0x80F, zero
+
+###################################################
+# Soteria Pseudorandom Decoy Instruction CSRs
+###################################################
+
+# mpigrate
+# name
+# CHECK-INST: csrrs t1, mpigrate, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0xbc]
+# CHECK-INST-ALIAS: csrr t1, mpigrate
+# uimm12
+# CHECK-INST: csrrs t2, mpigrate, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0xbc]
+# CHECK-INST-ALIAS: csrr t2, mpigrate
+# name
+csrrs t1, mpigrate, zero
+# uimm12
+csrrs t2, 0xBC9, zero
+
+# mpigseed0
+# name
+# CHECK-INST: csrrs t1, mpigseed0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0xbc]
+# CHECK-INST-ALIAS: csrr t1, mpigseed0
+# uimm12
+# CHECK-INST: csrrs t2, mpigseed0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xbc]
+# CHECK-INST-ALIAS: csrr t2, mpigseed0
+# name
+csrrs t1, mpigseed0, zero
+# uimm12
+csrrs t2, 0xBCE, zero
+
+# mpigseed1
+# name
+# CHECK-INST: csrrs t1, mpigseed1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0xbc]
+# CHECK-INST-ALIAS: csrr t1, mpigseed1
+# uimm12
+# CHECK-INST: csrrs t2, mpigseed1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xbc]
+# CHECK-INST-ALIAS: csrr t2, mpigseed1
+# name
+csrrs t1, mpigseed1, zero
+# uimm12
+csrrs t2, 0xBCC, zero
+
+###################################################
+# Soteria Machine State Wipe
+###################################################
+
+# uswc
+# name
+# CHECK-INST: csrrs t1, uswc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x80]
+# CHECK-INST-ALIAS: csrr t1, uswc
+# uimm12
+# CHECK-INST: csrrs t2, uswc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x80]
+# CHECK-INST-ALIAS: csrr t2, uswc
+# name
+csrrs t1, uswc, zero
+# uimm12
+csrrs t2, 0x800, zero
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -1855,7 +1855,8 @@ static const EnumEntry<unsigned> ElfHeaderRISCVFlags[] = {
   ENUM_ENT(EF_RISCV_FLOAT_ABI_SINGLE, "single-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_DOUBLE, "double-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_QUAD, "quad-float ABI"),
-  ENUM_ENT(EF_RISCV_RVE, "RVE")
+  ENUM_ENT(EF_RISCV_RVE, "RVE"),
+  ENUM_ENT(EF_RISCV_SOTERIA, "Soteria")
 };
 
 static const EnumEntry<unsigned> ElfSymOtherFlags[] = {