| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <linux/kernel.h> |
| #include <linux/err.h> |
| #include <linux/platform_device.h> |
| #include <linux/module.h> |
| #include <linux/of.h> |
| #include <linux/of_device.h> |
| #include <linux/clk-provider.h> |
| #include <linux/regmap.h> |
| |
| #include <dt-bindings/clock/qcom,gcc-ipq8074.h> |
| |
| #include "common.h" |
| #include "clk-regmap.h" |
| #include "clk-pll.h" |
| #include "clk-rcg.h" |
| #include "clk-branch.h" |
| #include "clk-alpha-pll.h" |
| #include "clk-regmap-divider.h" |
| #include "clk-regmap-mux.h" |
| #include "reset.h" |
| |
| enum { |
| P_XO, |
| P_GPLL0, |
| P_GPLL0_DIV2, |
| P_GPLL2, |
| P_GPLL4, |
| P_GPLL6, |
| P_SLEEP_CLK, |
| P_PCIE20_PHY0_PIPE, |
| P_PCIE20_PHY1_PIPE, |
| P_USB3PHY_0_PIPE, |
| P_USB3PHY_1_PIPE, |
| P_UBI32_PLL, |
| P_NSS_CRYPTO_PLL, |
| P_BIAS_PLL, |
| P_BIAS_PLL_NSS_NOC, |
| P_UNIPHY0_RX, |
| P_UNIPHY0_TX, |
| P_UNIPHY1_RX, |
| P_UNIPHY1_TX, |
| P_UNIPHY2_RX, |
| P_UNIPHY2_TX, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = { |
| "xo", |
| "gpll0", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL0_DIV2, 4 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0[] = { |
| "xo", |
| "gpll0", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { |
| "xo", |
| "gpll0", |
| "gpll2", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL2, 2 }, |
| { P_GPLL0_DIV2, 4 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_sleep_clk[] = { |
| "xo", |
| "gpll0", |
| "sleep_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 2 }, |
| { P_SLEEP_CLK, 6 }, |
| }; |
| |
| static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = { |
| "xo", |
| "gpll6", |
| "gpll0", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL6, 1 }, |
| { P_GPLL0, 3 }, |
| { P_GPLL0_DIV2, 4 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = { |
| "xo", |
| "gpll0_out_main_div2", |
| "gpll0", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0_DIV2, 2 }, |
| { P_GPLL0, 1 }, |
| }; |
| |
| static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = { |
| "usb3phy_0_cc_pipe_clk", |
| "xo", |
| }; |
| |
| static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { |
| { P_USB3PHY_0_PIPE, 0 }, |
| { P_XO, 2 }, |
| }; |
| |
| static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = { |
| "usb3phy_1_cc_pipe_clk", |
| "xo", |
| }; |
| |
| static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = { |
| { P_USB3PHY_1_PIPE, 0 }, |
| { P_XO, 2 }, |
| }; |
| |
| static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = { |
| "pcie20_phy0_pipe_clk", |
| "xo", |
| }; |
| |
| static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { |
| { P_PCIE20_PHY0_PIPE, 0 }, |
| { P_XO, 2 }, |
| }; |
| |
| static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = { |
| "pcie20_phy1_pipe_clk", |
| "xo", |
| }; |
| |
| static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { |
| { P_PCIE20_PHY1_PIPE, 0 }, |
| { P_XO, 2 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = { |
| "xo", |
| "gpll0", |
| "gpll6", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL6, 2 }, |
| { P_GPLL0_DIV2, 4 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = { |
| "xo", |
| "gpll0", |
| "gpll6", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL6, 2 }, |
| { P_GPLL0_DIV2, 3 }, |
| }; |
| |
| static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = { |
| "xo", |
| "bias_pll_nss_noc_clk", |
| "gpll0", |
| "gpll2", |
| }; |
| |
| static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = { |
| { P_XO, 0 }, |
| { P_BIAS_PLL_NSS_NOC, 1 }, |
| { P_GPLL0, 2 }, |
| { P_GPLL2, 3 }, |
| }; |
| |
| static const char * const gcc_xo_nss_crypto_pll_gpll0[] = { |
| "xo", |
| "nss_crypto_pll", |
| "gpll0", |
| }; |
| |
| static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = { |
| { P_XO, 0 }, |
| { P_NSS_CRYPTO_PLL, 1 }, |
| { P_GPLL0, 2 }, |
| }; |
| |
| static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = { |
| "xo", |
| "ubi32_pll", |
| "gpll0", |
| "gpll2", |
| "gpll4", |
| "gpll6", |
| }; |
| |
| static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = { |
| { P_XO, 0 }, |
| { P_UBI32_PLL, 1 }, |
| { P_GPLL0, 2 }, |
| { P_GPLL2, 3 }, |
| { P_GPLL4, 4 }, |
| { P_GPLL6, 5 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_out_main_div2[] = { |
| "xo", |
| "gpll0_out_main_div2", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0_DIV2, 1 }, |
| }; |
| |
| static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { |
| "xo", |
| "bias_pll_cc_clk", |
| "gpll0", |
| "gpll4", |
| "nss_crypto_pll", |
| "ubi32_pll", |
| }; |
| |
| static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = { |
| { P_XO, 0 }, |
| { P_BIAS_PLL, 1 }, |
| { P_GPLL0, 2 }, |
| { P_GPLL4, 3 }, |
| { P_NSS_CRYPTO_PLL, 4 }, |
| { P_UBI32_PLL, 5 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll4[] = { |
| "xo", |
| "gpll0", |
| "gpll4", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL4, 2 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { |
| "xo", |
| "uniphy0_gcc_rx_clk", |
| "uniphy0_gcc_tx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY0_RX, 1 }, |
| { P_UNIPHY0_TX, 2 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { |
| "xo", |
| "uniphy0_gcc_tx_clk", |
| "uniphy0_gcc_rx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY0_TX, 1 }, |
| { P_UNIPHY0_RX, 2 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { |
| "xo", |
| "uniphy0_gcc_rx_clk", |
| "uniphy0_gcc_tx_clk", |
| "uniphy1_gcc_rx_clk", |
| "uniphy1_gcc_tx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map |
| gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY0_RX, 1 }, |
| { P_UNIPHY0_TX, 2 }, |
| { P_UNIPHY1_RX, 3 }, |
| { P_UNIPHY1_TX, 4 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { |
| "xo", |
| "uniphy0_gcc_tx_clk", |
| "uniphy0_gcc_rx_clk", |
| "uniphy1_gcc_tx_clk", |
| "uniphy1_gcc_rx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map |
| gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY0_TX, 1 }, |
| { P_UNIPHY0_RX, 2 }, |
| { P_UNIPHY1_TX, 3 }, |
| { P_UNIPHY1_RX, 4 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = { |
| "xo", |
| "uniphy2_gcc_rx_clk", |
| "uniphy2_gcc_tx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY2_RX, 1 }, |
| { P_UNIPHY2_TX, 2 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = { |
| "xo", |
| "uniphy2_gcc_tx_clk", |
| "uniphy2_gcc_rx_clk", |
| "ubi32_pll", |
| "bias_pll_cc_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = { |
| { P_XO, 0 }, |
| { P_UNIPHY2_TX, 1 }, |
| { P_UNIPHY2_RX, 2 }, |
| { P_UBI32_PLL, 5 }, |
| { P_BIAS_PLL, 6 }, |
| }; |
| |
| static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = { |
| "xo", |
| "gpll0", |
| "gpll6", |
| "gpll0_out_main_div2", |
| "sleep_clk", |
| }; |
| |
| static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = { |
| { P_XO, 0 }, |
| { P_GPLL0, 1 }, |
| { P_GPLL6, 2 }, |
| { P_GPLL0_DIV2, 4 }, |
| { P_SLEEP_CLK, 6 }, |
| }; |
| |
| static struct clk_alpha_pll gpll0_main = { |
| .offset = 0x21000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll0_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_fixed_factor gpll0_out_main_div2 = { |
| .mult = 1, |
| .div = 2, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll0_out_main_div2", |
| .parent_names = (const char *[]){ |
| "gpll0_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv gpll0 = { |
| .offset = 0x21000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .width = 4, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gpll0", |
| .parent_names = (const char *[]){ |
| "gpll0_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| }, |
| }; |
| |
| static struct clk_alpha_pll gpll2_main = { |
| .offset = 0x4a000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(2), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll2_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_ops, |
| .flags = CLK_IS_CRITICAL, |
| }, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv gpll2 = { |
| .offset = 0x4a000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .width = 4, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gpll2", |
| .parent_names = (const char *[]){ |
| "gpll2_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_alpha_pll gpll4_main = { |
| .offset = 0x24000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(5), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll4_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_ops, |
| .flags = CLK_IS_CRITICAL, |
| }, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv gpll4 = { |
| .offset = 0x24000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .width = 4, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gpll4", |
| .parent_names = (const char *[]){ |
| "gpll4_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_alpha_pll gpll6_main = { |
| .offset = 0x37000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], |
| .flags = SUPPORTS_DYNAMIC_UPDATE, |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(7), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll6_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_ops, |
| .flags = CLK_IS_CRITICAL, |
| }, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv gpll6 = { |
| .offset = 0x37000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], |
| .width = 2, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gpll6", |
| .parent_names = (const char *[]){ |
| "gpll6_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_fixed_factor gpll6_out_main_div2 = { |
| .mult = 1, |
| .div = 2, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpll6_out_main_div2", |
| .parent_names = (const char *[]){ |
| "gpll6_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_alpha_pll ubi32_pll_main = { |
| .offset = 0x25000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], |
| .flags = SUPPORTS_DYNAMIC_UPDATE, |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(6), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ubi32_pll_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_huayra_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv ubi32_pll = { |
| .offset = 0x25000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], |
| .width = 2, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "ubi32_pll", |
| .parent_names = (const char *[]){ |
| "ubi32_pll_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_alpha_pll nss_crypto_pll_main = { |
| .offset = 0x22000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .clkr = { |
| .enable_reg = 0x0b000, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_crypto_pll_main", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_alpha_pll_postdiv nss_crypto_pll = { |
| .offset = 0x22000, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
| .width = 4, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_crypto_pll", |
| .parent_names = (const char *[]){ |
| "nss_crypto_pll_main" |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_postdiv_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(50000000, P_GPLL0, 16, 0, 0), |
| F(100000000, P_GPLL0, 8, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 pcnoc_bfdcd_clk_src = { |
| .cmd_rcgr = 0x27000, |
| .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pcnoc_bfdcd_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| .flags = CLK_IS_CRITICAL, |
| }, |
| }; |
| |
| static struct clk_fixed_factor pcnoc_clk_src = { |
| .mult = 1, |
| .div = 1, |
| .hw.init = &(struct clk_init_data){ |
| .name = "pcnoc_clk_src", |
| .parent_names = (const char *[]){ |
| "pcnoc_bfdcd_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sleep_clk_src = { |
| .halt_reg = 0x30000, |
| .clkr = { |
| .enable_reg = 0x30000, |
| .enable_mask = BIT(1), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sleep_clk_src", |
| .parent_names = (const char *[]){ |
| "sleep_clk" |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_GPLL0_DIV2, 16, 0, 0), |
| F(50000000, P_GPLL0, 16, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x0200c, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup1_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { |
| F(960000, P_XO, 10, 1, 2), |
| F(4800000, P_XO, 4, 0, 0), |
| F(9600000, P_XO, 2, 0, 0), |
| F(12500000, P_GPLL0_DIV2, 16, 1, 2), |
| F(16000000, P_GPLL0, 10, 1, 5), |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_GPLL0, 16, 1, 2), |
| F(50000000, P_GPLL0, 16, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { |
| .cmd_rcgr = 0x02024, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup1_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x03000, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup2_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { |
| .cmd_rcgr = 0x03014, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup2_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x04000, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup3_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { |
| .cmd_rcgr = 0x04014, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup3_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x05000, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup4_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { |
| .cmd_rcgr = 0x05014, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup4_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x06000, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup5_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { |
| .cmd_rcgr = 0x06014, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup5_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { |
| .cmd_rcgr = 0x07000, |
| .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup6_i2c_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { |
| .cmd_rcgr = 0x07014, |
| .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_qup6_spi_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { |
| F(3686400, P_GPLL0_DIV2, 1, 144, 15625), |
| F(7372800, P_GPLL0_DIV2, 1, 288, 15625), |
| F(14745600, P_GPLL0_DIV2, 1, 576, 15625), |
| F(16000000, P_GPLL0_DIV2, 5, 1, 5), |
| F(19200000, P_XO, 1, 0, 0), |
| F(24000000, P_GPLL0, 1, 3, 100), |
| F(25000000, P_GPLL0, 16, 1, 2), |
| F(32000000, P_GPLL0, 1, 1, 25), |
| F(40000000, P_GPLL0, 1, 1, 20), |
| F(46400000, P_GPLL0, 1, 29, 500), |
| F(48000000, P_GPLL0, 1, 3, 50), |
| F(51200000, P_GPLL0, 1, 8, 125), |
| F(56000000, P_GPLL0, 1, 7, 100), |
| F(58982400, P_GPLL0, 1, 1152, 15625), |
| F(60000000, P_GPLL0, 1, 3, 40), |
| F(64000000, P_GPLL0, 12.5, 1, 1), |
| { } |
| }; |
| |
| static struct clk_rcg2 blsp1_uart1_apps_clk_src = { |
| .cmd_rcgr = 0x02044, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart1_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_uart2_apps_clk_src = { |
| .cmd_rcgr = 0x03034, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart2_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_uart3_apps_clk_src = { |
| .cmd_rcgr = 0x04034, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart3_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_uart4_apps_clk_src = { |
| .cmd_rcgr = 0x05034, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart4_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_uart5_apps_clk_src = { |
| .cmd_rcgr = 0x06034, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart5_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 blsp1_uart6_apps_clk_src = { |
| .cmd_rcgr = 0x07034, |
| .freq_tbl = ftbl_blsp1_uart_apps_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "blsp1_uart6_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_pcie_axi_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(200000000, P_GPLL0, 4, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 pcie0_axi_clk_src = { |
| .cmd_rcgr = 0x75054, |
| .freq_tbl = ftbl_pcie_axi_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pcie0_axi_clk_src", |
| .parent_names = gcc_xo_gpll0, |
| .num_parents = 2, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| }; |
| |
| static struct clk_rcg2 pcie0_aux_clk_src = { |
| .cmd_rcgr = 0x75024, |
| .freq_tbl = ftbl_pcie_aux_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pcie0_aux_clk_src", |
| .parent_names = gcc_xo_gpll0_sleep_clk, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_mux pcie0_pipe_clk_src = { |
| .reg = 0x7501c, |
| .shift = 8, |
| .width = 2, |
| .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "pcie0_pipe_clk_src", |
| .parent_names = gcc_pcie20_phy0_pipe_clk_xo, |
| .num_parents = 2, |
| .ops = &clk_regmap_mux_closest_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 pcie1_axi_clk_src = { |
| .cmd_rcgr = 0x76054, |
| .freq_tbl = ftbl_pcie_axi_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pcie1_axi_clk_src", |
| .parent_names = gcc_xo_gpll0, |
| .num_parents = 2, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 pcie1_aux_clk_src = { |
| .cmd_rcgr = 0x76024, |
| .freq_tbl = ftbl_pcie_aux_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pcie1_aux_clk_src", |
| .parent_names = gcc_xo_gpll0_sleep_clk, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_mux pcie1_pipe_clk_src = { |
| .reg = 0x7601c, |
| .shift = 8, |
| .width = 2, |
| .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "pcie1_pipe_clk_src", |
| .parent_names = gcc_pcie20_phy1_pipe_clk_xo, |
| .num_parents = 2, |
| .ops = &clk_regmap_mux_closest_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { |
| F(144000, P_XO, 16, 3, 25), |
| F(400000, P_XO, 12, 1, 4), |
| F(24000000, P_GPLL2, 12, 1, 4), |
| F(48000000, P_GPLL2, 12, 1, 2), |
| F(96000000, P_GPLL2, 12, 0, 0), |
| F(177777778, P_GPLL0, 4.5, 0, 0), |
| F(192000000, P_GPLL2, 6, 0, 0), |
| F(384000000, P_GPLL2, 3, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 sdcc1_apps_clk_src = { |
| .cmd_rcgr = 0x42004, |
| .freq_tbl = ftbl_sdcc_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "sdcc1_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(160000000, P_GPLL0, 5, 0, 0), |
| F(308570000, P_GPLL6, 3.5, 0, 0), |
| }; |
| |
| static struct clk_rcg2 sdcc1_ice_core_clk_src = { |
| .cmd_rcgr = 0x5d000, |
| .freq_tbl = ftbl_sdcc_ice_core_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "sdcc1_ice_core_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 sdcc2_apps_clk_src = { |
| .cmd_rcgr = 0x43004, |
| .freq_tbl = ftbl_sdcc_apps_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "sdcc2_apps_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_floor_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_usb_master_clk_src[] = { |
| F(80000000, P_GPLL0_DIV2, 5, 0, 0), |
| F(100000000, P_GPLL0, 8, 0, 0), |
| F(133330000, P_GPLL0, 6, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 usb0_master_clk_src = { |
| .cmd_rcgr = 0x3e00c, |
| .freq_tbl = ftbl_usb_master_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb0_master_clk_src", |
| .parent_names = gcc_xo_gpll0_out_main_div2_gpll0, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_usb_aux_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 usb0_aux_clk_src = { |
| .cmd_rcgr = 0x3e05c, |
| .freq_tbl = ftbl_usb_aux_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb0_aux_clk_src", |
| .parent_names = gcc_xo_gpll0_sleep_clk, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(20000000, P_GPLL6, 6, 1, 9), |
| F(60000000, P_GPLL6, 6, 1, 3), |
| { } |
| }; |
| |
| static struct clk_rcg2 usb0_mock_utmi_clk_src = { |
| .cmd_rcgr = 0x3e020, |
| .freq_tbl = ftbl_usb_mock_utmi_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb0_mock_utmi_clk_src", |
| .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_mux usb0_pipe_clk_src = { |
| .reg = 0x3e048, |
| .shift = 8, |
| .width = 2, |
| .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb0_pipe_clk_src", |
| .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo, |
| .num_parents = 2, |
| .ops = &clk_regmap_mux_closest_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 usb1_master_clk_src = { |
| .cmd_rcgr = 0x3f00c, |
| .freq_tbl = ftbl_usb_master_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb1_master_clk_src", |
| .parent_names = gcc_xo_gpll0_out_main_div2_gpll0, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 usb1_aux_clk_src = { |
| .cmd_rcgr = 0x3f05c, |
| .freq_tbl = ftbl_usb_aux_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb1_aux_clk_src", |
| .parent_names = gcc_xo_gpll0_sleep_clk, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 usb1_mock_utmi_clk_src = { |
| .cmd_rcgr = 0x3f020, |
| .freq_tbl = ftbl_usb_mock_utmi_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "usb1_mock_utmi_clk_src", |
| .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_mux usb1_pipe_clk_src = { |
| .reg = 0x3f048, |
| .shift = 8, |
| .width = 2, |
| .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb1_pipe_clk_src", |
| .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo, |
| .num_parents = 2, |
| .ops = &clk_regmap_mux_closest_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_xo_clk_src = { |
| .halt_reg = 0x30018, |
| .clkr = { |
| .enable_reg = 0x30018, |
| .enable_mask = BIT(1), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_xo_clk_src", |
| .parent_names = (const char *[]){ |
| "xo" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_fixed_factor gcc_xo_div4_clk_src = { |
| .mult = 1, |
| .div = 4, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_xo_div4_clk_src", |
| .parent_names = (const char *[]){ |
| "gcc_xo_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(50000000, P_GPLL0_DIV2, 8, 0, 0), |
| F(100000000, P_GPLL0, 8, 0, 0), |
| F(133333333, P_GPLL0, 6, 0, 0), |
| F(160000000, P_GPLL0, 5, 0, 0), |
| F(200000000, P_GPLL0, 4, 0, 0), |
| F(266666667, P_GPLL0, 3, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 system_noc_bfdcd_clk_src = { |
| .cmd_rcgr = 0x26004, |
| .freq_tbl = ftbl_system_noc_bfdcd_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "system_noc_bfdcd_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| .flags = CLK_IS_CRITICAL, |
| }, |
| }; |
| |
| static struct clk_fixed_factor system_noc_clk_src = { |
| .mult = 1, |
| .div = 1, |
| .hw.init = &(struct clk_init_data){ |
| .name = "system_noc_clk_src", |
| .parent_names = (const char *[]){ |
| "system_noc_bfdcd_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_ce_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(200000000, P_GPLL0, 4, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_ce_clk_src = { |
| .cmd_rcgr = 0x68098, |
| .freq_tbl = ftbl_nss_ce_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_ce_clk_src", |
| .parent_names = gcc_xo_gpll0, |
| .num_parents = 2, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_noc_bfdcd_clk_src = { |
| .cmd_rcgr = 0x68088, |
| .freq_tbl = ftbl_nss_noc_bfdcd_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_noc_bfdcd_clk_src", |
| .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_fixed_factor nss_noc_clk_src = { |
| .mult = 1, |
| .div = 1, |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_noc_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_noc_bfdcd_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_crypto_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_crypto_clk_src = { |
| .cmd_rcgr = 0x68144, |
| .freq_tbl = ftbl_nss_crypto_clk_src, |
| .mnd_width = 16, |
| .hid_width = 5, |
| .parent_map = gcc_xo_nss_crypto_pll_gpll0_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_crypto_clk_src", |
| .parent_names = gcc_xo_nss_crypto_pll_gpll0, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_ubi_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(187200000, P_UBI32_PLL, 8, 0, 0), |
| F(748800000, P_UBI32_PLL, 2, 0, 0), |
| F(1497600000, P_UBI32_PLL, 1, 0, 0), |
| F(1689600000, P_UBI32_PLL, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_ubi0_clk_src = { |
| .cmd_rcgr = 0x68104, |
| .freq_tbl = ftbl_nss_ubi_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_ubi0_clk_src", |
| .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6, |
| .num_parents = 6, |
| .ops = &clk_rcg2_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_ubi0_div_clk_src = { |
| .reg = 0x68118, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_ubi0_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_ubi0_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_ubi1_clk_src = { |
| .cmd_rcgr = 0x68124, |
| .freq_tbl = ftbl_nss_ubi_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_ubi1_clk_src", |
| .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6, |
| .num_parents = 6, |
| .ops = &clk_rcg2_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_ubi1_div_clk_src = { |
| .reg = 0x68138, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_ubi1_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_ubi1_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ro_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_GPLL0_DIV2, 16, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 ubi_mpt_clk_src = { |
| .cmd_rcgr = 0x68090, |
| .freq_tbl = ftbl_ubi_mpt_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "ubi_mpt_clk_src", |
| .parent_names = gcc_xo_gpll0_out_main_div2, |
| .num_parents = 2, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_imem_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(400000000, P_GPLL0, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_imem_clk_src = { |
| .cmd_rcgr = 0x68158, |
| .freq_tbl = ftbl_nss_imem_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll4_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_imem_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll4, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_ppe_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(300000000, P_BIAS_PLL, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_ppe_clk_src = { |
| .cmd_rcgr = 0x68080, |
| .freq_tbl = ftbl_nss_ppe_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_ppe_clk_src", |
| .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32, |
| .num_parents = 6, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_fixed_factor nss_ppe_cdiv_clk_src = { |
| .mult = 1, |
| .div = 4, |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_ppe_cdiv_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_ppe_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_fixed_factor_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY0_RX, 5, 0, 0), |
| F(125000000, P_UNIPHY0_RX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port1_rx_clk_src = { |
| .cmd_rcgr = 0x68020, |
| .freq_tbl = ftbl_nss_port1_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port1_rx_clk_src", |
| .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port1_rx_div_clk_src = { |
| .reg = 0x68400, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port1_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port1_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY0_TX, 5, 0, 0), |
| F(125000000, P_UNIPHY0_TX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port1_tx_clk_src = { |
| .cmd_rcgr = 0x68028, |
| .freq_tbl = ftbl_nss_port1_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port1_tx_clk_src", |
| .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port1_tx_div_clk_src = { |
| .reg = 0x68404, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port1_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port1_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port2_rx_clk_src = { |
| .cmd_rcgr = 0x68030, |
| .freq_tbl = ftbl_nss_port1_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port2_rx_clk_src", |
| .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port2_rx_div_clk_src = { |
| .reg = 0x68410, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port2_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port2_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port2_tx_clk_src = { |
| .cmd_rcgr = 0x68038, |
| .freq_tbl = ftbl_nss_port1_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port2_tx_clk_src", |
| .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port2_tx_div_clk_src = { |
| .reg = 0x68414, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port2_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port2_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port3_rx_clk_src = { |
| .cmd_rcgr = 0x68040, |
| .freq_tbl = ftbl_nss_port1_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port3_rx_clk_src", |
| .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port3_rx_div_clk_src = { |
| .reg = 0x68420, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port3_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port3_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port3_tx_clk_src = { |
| .cmd_rcgr = 0x68048, |
| .freq_tbl = ftbl_nss_port1_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port3_tx_clk_src", |
| .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port3_tx_div_clk_src = { |
| .reg = 0x68424, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port3_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port3_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port4_rx_clk_src = { |
| .cmd_rcgr = 0x68050, |
| .freq_tbl = ftbl_nss_port1_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port4_rx_clk_src", |
| .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port4_rx_div_clk_src = { |
| .reg = 0x68430, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port4_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port4_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg2 nss_port4_tx_clk_src = { |
| .cmd_rcgr = 0x68058, |
| .freq_tbl = ftbl_nss_port1_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port4_tx_clk_src", |
| .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port4_tx_div_clk_src = { |
| .reg = 0x68434, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port4_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port4_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), |
| F(78125000, P_UNIPHY1_RX, 4, 0, 0), |
| F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), |
| F(156250000, P_UNIPHY1_RX, 2, 0, 0), |
| F(312500000, P_UNIPHY1_RX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port5_rx_clk_src = { |
| .cmd_rcgr = 0x68060, |
| .freq_tbl = ftbl_nss_port5_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port5_rx_clk_src", |
| .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias, |
| .num_parents = 7, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port5_rx_div_clk_src = { |
| .reg = 0x68440, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port5_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port5_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), |
| F(78125000, P_UNIPHY1_TX, 4, 0, 0), |
| F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), |
| F(156250000, P_UNIPHY1_TX, 2, 0, 0), |
| F(312500000, P_UNIPHY1_TX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port5_tx_clk_src = { |
| .cmd_rcgr = 0x68068, |
| .freq_tbl = ftbl_nss_port5_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port5_tx_clk_src", |
| .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias, |
| .num_parents = 7, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port5_tx_div_clk_src = { |
| .reg = 0x68444, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port5_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port5_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), |
| F(78125000, P_UNIPHY2_RX, 4, 0, 0), |
| F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), |
| F(156250000, P_UNIPHY2_RX, 2, 0, 0), |
| F(312500000, P_UNIPHY2_RX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port6_rx_clk_src = { |
| .cmd_rcgr = 0x68070, |
| .freq_tbl = ftbl_nss_port6_rx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port6_rx_clk_src", |
| .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port6_rx_div_clk_src = { |
| .reg = 0x68450, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port6_rx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port6_rx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), |
| F(78125000, P_UNIPHY2_TX, 4, 0, 0), |
| F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), |
| F(156250000, P_UNIPHY2_TX, 2, 0, 0), |
| F(312500000, P_UNIPHY2_TX, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 nss_port6_tx_clk_src = { |
| .cmd_rcgr = 0x68078, |
| .freq_tbl = ftbl_nss_port6_tx_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "nss_port6_tx_clk_src", |
| .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div nss_port6_tx_div_clk_src = { |
| .reg = 0x68454, |
| .shift = 0, |
| .width = 4, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "nss_port6_tx_div_clk_src", |
| .parent_names = (const char *[]){ |
| "nss_port6_tx_clk_src" |
| }, |
| .num_parents = 1, |
| .ops = &clk_regmap_div_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct freq_tbl ftbl_crypto_clk_src[] = { |
| F(40000000, P_GPLL0_DIV2, 10, 0, 0), |
| F(80000000, P_GPLL0, 10, 0, 0), |
| F(100000000, P_GPLL0, 8, 0, 0), |
| F(160000000, P_GPLL0, 5, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 crypto_clk_src = { |
| .cmd_rcgr = 0x16004, |
| .freq_tbl = ftbl_crypto_clk_src, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "crypto_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct freq_tbl ftbl_gp_clk_src[] = { |
| F(19200000, P_XO, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 gp1_clk_src = { |
| .cmd_rcgr = 0x08004, |
| .freq_tbl = ftbl_gp_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gp1_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 gp2_clk_src = { |
| .cmd_rcgr = 0x09004, |
| .freq_tbl = ftbl_gp_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gp2_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 gp3_clk_src = { |
| .cmd_rcgr = 0x0a004, |
| .freq_tbl = ftbl_gp_clk_src, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gp3_clk_src", |
| .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, |
| .num_parents = 5, |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_ahb_clk = { |
| .halt_reg = 0x01008, |
| .clkr = { |
| .enable_reg = 0x01008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
| .halt_reg = 0x02008, |
| .clkr = { |
| .enable_reg = 0x02008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup1_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup1_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
| .halt_reg = 0x02004, |
| .clkr = { |
| .enable_reg = 0x02004, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup1_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup1_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
| .halt_reg = 0x03010, |
| .clkr = { |
| .enable_reg = 0x03010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup2_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup2_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
| .halt_reg = 0x0300c, |
| .clkr = { |
| .enable_reg = 0x0300c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup2_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup2_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
| .halt_reg = 0x04010, |
| .clkr = { |
| .enable_reg = 0x04010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup3_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup3_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
| .halt_reg = 0x0400c, |
| .clkr = { |
| .enable_reg = 0x0400c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup3_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup3_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
| .halt_reg = 0x05010, |
| .clkr = { |
| .enable_reg = 0x05010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup4_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup4_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
| .halt_reg = 0x0500c, |
| .clkr = { |
| .enable_reg = 0x0500c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup4_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup4_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { |
| .halt_reg = 0x06010, |
| .clkr = { |
| .enable_reg = 0x06010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup5_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup5_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { |
| .halt_reg = 0x0600c, |
| .clkr = { |
| .enable_reg = 0x0600c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup5_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup5_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { |
| .halt_reg = 0x07010, |
| .clkr = { |
| .enable_reg = 0x07010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup6_i2c_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup6_i2c_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { |
| .halt_reg = 0x0700c, |
| .clkr = { |
| .enable_reg = 0x0700c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_qup6_spi_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_qup6_spi_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
| .halt_reg = 0x0203c, |
| .clkr = { |
| .enable_reg = 0x0203c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart1_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart1_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
| .halt_reg = 0x0302c, |
| .clkr = { |
| .enable_reg = 0x0302c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart2_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart2_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart3_apps_clk = { |
| .halt_reg = 0x0402c, |
| .clkr = { |
| .enable_reg = 0x0402c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart3_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart3_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart4_apps_clk = { |
| .halt_reg = 0x0502c, |
| .clkr = { |
| .enable_reg = 0x0502c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart4_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart4_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart5_apps_clk = { |
| .halt_reg = 0x0602c, |
| .clkr = { |
| .enable_reg = 0x0602c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart5_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart5_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_blsp1_uart6_apps_clk = { |
| .halt_reg = 0x0702c, |
| .clkr = { |
| .enable_reg = 0x0702c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_blsp1_uart6_apps_clk", |
| .parent_names = (const char *[]){ |
| "blsp1_uart6_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_prng_ahb_clk = { |
| .halt_reg = 0x13004, |
| .halt_check = BRANCH_HALT_VOTED, |
| .clkr = { |
| .enable_reg = 0x0b004, |
| .enable_mask = BIT(8), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_prng_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_qpic_ahb_clk = { |
| .halt_reg = 0x57024, |
| .clkr = { |
| .enable_reg = 0x57024, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_qpic_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_qpic_clk = { |
| .halt_reg = 0x57020, |
| .clkr = { |
| .enable_reg = 0x57020, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_qpic_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie0_ahb_clk = { |
| .halt_reg = 0x75010, |
| .clkr = { |
| .enable_reg = 0x75010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie0_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie0_aux_clk = { |
| .halt_reg = 0x75014, |
| .clkr = { |
| .enable_reg = 0x75014, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie0_aux_clk", |
| .parent_names = (const char *[]){ |
| "pcie0_aux_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie0_axi_m_clk = { |
| .halt_reg = 0x75008, |
| .clkr = { |
| .enable_reg = 0x75008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie0_axi_m_clk", |
| .parent_names = (const char *[]){ |
| "pcie0_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie0_axi_s_clk = { |
| .halt_reg = 0x7500c, |
| .clkr = { |
| .enable_reg = 0x7500c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie0_axi_s_clk", |
| .parent_names = (const char *[]){ |
| "pcie0_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie0_pipe_clk = { |
| .halt_reg = 0x75018, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0x75018, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie0_pipe_clk", |
| .parent_names = (const char *[]){ |
| "pcie0_pipe_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sys_noc_pcie0_axi_clk = { |
| .halt_reg = 0x26048, |
| .clkr = { |
| .enable_reg = 0x26048, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sys_noc_pcie0_axi_clk", |
| .parent_names = (const char *[]){ |
| "pcie0_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie1_ahb_clk = { |
| .halt_reg = 0x76010, |
| .clkr = { |
| .enable_reg = 0x76010, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie1_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie1_aux_clk = { |
| .halt_reg = 0x76014, |
| .clkr = { |
| .enable_reg = 0x76014, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie1_aux_clk", |
| .parent_names = (const char *[]){ |
| "pcie1_aux_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie1_axi_m_clk = { |
| .halt_reg = 0x76008, |
| .clkr = { |
| .enable_reg = 0x76008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie1_axi_m_clk", |
| .parent_names = (const char *[]){ |
| "pcie1_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie1_axi_s_clk = { |
| .halt_reg = 0x7600c, |
| .clkr = { |
| .enable_reg = 0x7600c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie1_axi_s_clk", |
| .parent_names = (const char *[]){ |
| "pcie1_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_pcie1_pipe_clk = { |
| .halt_reg = 0x76018, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0x76018, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_pcie1_pipe_clk", |
| .parent_names = (const char *[]){ |
| "pcie1_pipe_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sys_noc_pcie1_axi_clk = { |
| .halt_reg = 0x2604c, |
| .clkr = { |
| .enable_reg = 0x2604c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sys_noc_pcie1_axi_clk", |
| .parent_names = (const char *[]){ |
| "pcie1_axi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_aux_clk = { |
| .halt_reg = 0x3e044, |
| .clkr = { |
| .enable_reg = 0x3e044, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_aux_clk", |
| .parent_names = (const char *[]){ |
| "usb0_aux_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sys_noc_usb0_axi_clk = { |
| .halt_reg = 0x26040, |
| .clkr = { |
| .enable_reg = 0x26040, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sys_noc_usb0_axi_clk", |
| .parent_names = (const char *[]){ |
| "usb0_master_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_master_clk = { |
| .halt_reg = 0x3e000, |
| .clkr = { |
| .enable_reg = 0x3e000, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_master_clk", |
| .parent_names = (const char *[]){ |
| "usb0_master_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_mock_utmi_clk = { |
| .halt_reg = 0x3e008, |
| .clkr = { |
| .enable_reg = 0x3e008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_mock_utmi_clk", |
| .parent_names = (const char *[]){ |
| "usb0_mock_utmi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { |
| .halt_reg = 0x3e080, |
| .clkr = { |
| .enable_reg = 0x3e080, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_phy_cfg_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_pipe_clk = { |
| .halt_reg = 0x3e040, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0x3e040, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_pipe_clk", |
| .parent_names = (const char *[]){ |
| "usb0_pipe_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb0_sleep_clk = { |
| .halt_reg = 0x3e004, |
| .clkr = { |
| .enable_reg = 0x3e004, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb0_sleep_clk", |
| .parent_names = (const char *[]){ |
| "gcc_sleep_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_aux_clk = { |
| .halt_reg = 0x3f044, |
| .clkr = { |
| .enable_reg = 0x3f044, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_aux_clk", |
| .parent_names = (const char *[]){ |
| "usb1_aux_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sys_noc_usb1_axi_clk = { |
| .halt_reg = 0x26044, |
| .clkr = { |
| .enable_reg = 0x26044, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sys_noc_usb1_axi_clk", |
| .parent_names = (const char *[]){ |
| "usb1_master_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_master_clk = { |
| .halt_reg = 0x3f000, |
| .clkr = { |
| .enable_reg = 0x3f000, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_master_clk", |
| .parent_names = (const char *[]){ |
| "usb1_master_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_mock_utmi_clk = { |
| .halt_reg = 0x3f008, |
| .clkr = { |
| .enable_reg = 0x3f008, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_mock_utmi_clk", |
| .parent_names = (const char *[]){ |
| "usb1_mock_utmi_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = { |
| .halt_reg = 0x3f080, |
| .clkr = { |
| .enable_reg = 0x3f080, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_phy_cfg_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_pipe_clk = { |
| .halt_reg = 0x3f040, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0x3f040, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_pipe_clk", |
| .parent_names = (const char *[]){ |
| "usb1_pipe_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_usb1_sleep_clk = { |
| .halt_reg = 0x3f004, |
| .clkr = { |
| .enable_reg = 0x3f004, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_usb1_sleep_clk", |
| .parent_names = (const char *[]){ |
| "gcc_sleep_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sdcc1_ahb_clk = { |
| .halt_reg = 0x4201c, |
| .clkr = { |
| .enable_reg = 0x4201c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sdcc1_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sdcc1_apps_clk = { |
| .halt_reg = 0x42018, |
| .clkr = { |
| .enable_reg = 0x42018, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sdcc1_apps_clk", |
| .parent_names = (const char *[]){ |
| "sdcc1_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sdcc1_ice_core_clk = { |
| .halt_reg = 0x5d014, |
| .clkr = { |
| .enable_reg = 0x5d014, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sdcc1_ice_core_clk", |
| .parent_names = (const char *[]){ |
| "sdcc1_ice_core_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sdcc2_ahb_clk = { |
| .halt_reg = 0x4301c, |
| .clkr = { |
| .enable_reg = 0x4301c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sdcc2_ahb_clk", |
| .parent_names = (const char *[]){ |
| "pcnoc_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gcc_sdcc2_apps_clk = { |
| .halt_reg = 0x43018, |
| .clkr = { |
| .enable_reg = 0x43018, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_sdcc2_apps_clk", |
| .parent_names = (const char *[]){ |
| "sdcc2_apps_clk_src" |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
|
