| /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
| /* |
| * Copyright (c) 2016 BayLibre, SAS |
| * Author: Neil Armstrong <narmstrong@baylibre.com> |
| * |
| * Copyright (c) 2018 Amlogic, inc. |
| * Author: Qiufang Dai <qiufang.dai@amlogic.com> |
| */ |
| |
| #ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK |
| #define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK |
| |
| #define CLKID_AO_REMOTE 0 |
| #define CLKID_AO_I2C_MASTER 1 |
| #define CLKID_AO_I2C_SLAVE 2 |
| #define CLKID_AO_UART1 3 |
| #define CLKID_AO_UART2 4 |
| #define CLKID_AO_IR_BLASTER 5 |
| #define CLKID_AO_SAR_ADC 6 |
| #define CLKID_AO_CLK81 7 |
| #define CLKID_AO_SAR_ADC_SEL 8 |
| #define CLKID_AO_SAR_ADC_DIV 9 |
| #define CLKID_AO_SAR_ADC_CLK 10 |
| #define CLKID_AO_ALT_XTAL 11 |
| |
| #endif |
