)]}'
{
  "commit": "c313bedcccfe2d5101010ce75b5af60919c63aa3",
  "tree": "304b0c9cfa48189f716d4c9eafa135a8416351a4",
  "parents": [
    "cfa9ed48d7b41bec72216c864a9e47e36fdc73c4"
  ],
  "author": {
    "name": "Lukas Wunner",
    "email": "lukas@wunner.de",
    "time": "Tue Jun 18 12:54:55 2024 +0200"
  },
  "committer": {
    "name": "Shuo Yang",
    "email": "gshuoy@google.com",
    "time": "Mon Sep 09 18:01:50 2024 +0000"
  },
  "message": "PCI/DPC: Fix use-after-free on concurrent DPC and hot-removal\n\ncommit 11a1f4bc47362700fcbde717292158873fb847ed upstream.\n\nKeith reports a use-after-free when a DPC event occurs concurrently to\nhot-removal of the same portion of the hierarchy:\n\nThe dpc_handler() awaits readiness of the secondary bus below the\nDownstream Port where the DPC event occurred.  To do so, it polls the\nconfig space of the first child device on the secondary bus.  If that\nchild device is concurrently removed, accesses to its struct pci_dev\ncause the kernel to oops.\n\nThat\u0027s because pci_bridge_wait_for_secondary_bus() neglects to hold a\nreference on the child device.  Before v6.3, the function was only\ncalled on resume from system sleep or on runtime resume.  Holding a\nreference wasn\u0027t necessary back then because the pciehp IRQ thread\ncould never run concurrently.  (On resume from system sleep, IRQs are\nnot enabled until after the resume_noirq phase.  And runtime resume is\nalways awaited before a PCI device is removed.)\n\nHowever starting with v6.3, pci_bridge_wait_for_secondary_bus() is also\ncalled on a DPC event.  Commit 53b54ad074de (\"PCI/DPC: Await readiness\nof secondary bus after reset\"), which introduced that, failed to\nappreciate that pci_bridge_wait_for_secondary_bus() now needs to hold a\nreference on the child device because dpc_handler() and pciehp may\nindeed run concurrently.  The commit was backported to v5.10+ stable\nkernels, so that\u0027s the oldest one affected.\n\nAdd the missing reference acquisition.\n\nAbridged stack trace:\n\n  BUG: unable to handle page fault for address: 00000000091400c0\n  CPU: 15 PID: 2464 Comm: irq/53-pcie-dpc 6.9.0\n  RIP: pci_bus_read_config_dword+0x17/0x50\n  pci_dev_wait()\n  pci_bridge_wait_for_secondary_bus()\n  dpc_reset_link()\n  pcie_do_recovery()\n  dpc_handler()\n\nBUG\u003db/362700943\nTEST\u003dpresubmit\nRELEASE_NOTE\u003dFixes CVE-2024-42302 in the Linux kernel\n\ncos-patch: security-high\nFixes: 53b54ad074de (\"PCI/DPC: Await readiness of secondary bus after reset\")\nCloses: https://lore.kernel.org/r/20240612181625.3604512-3-kbusch@meta.com/\nLink: https://lore.kernel.org/linux-pci/8e4bcd4116fd94f592f2bf2749f168099c480ddf.1718707743.git.lukas@wunner.de\nReported-by: Keith Busch \u003ckbusch@kernel.org\u003e\nTested-by: Keith Busch \u003ckbusch@kernel.org\u003e\nChange-Id: I5906d1bf2d2c88e7c5c62d6de8c0f22e4590b687\nSigned-off-by: Lukas Wunner \u003clukas@wunner.de\u003e\nSigned-off-by: Krzysztof Wilczyński \u003ckwilczynski@kernel.org\u003e\nReviewed-by: Keith Busch \u003ckbusch@kernel.org\u003e\nReviewed-by: Mika Westerberg \u003cmika.westerberg@linux.intel.com\u003e\nCc: stable@vger.kernel.org # v5.10+\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@linuxfoundation.org\u003e\nSigned-off-by: Shuo Yang \u003cgshuoy@google.com\u003e\nReviewed-on: https://cos-review.googlesource.com/c/third_party/kernel/+/80359\nTested-by: Cusky Presubmit Bot \u003cpresubmit@cos-infra-prod.iam.gserviceaccount.com\u003e\nReviewed-by: Anil Altinay \u003caaltinay@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0399204941dbe5743085689dad3a28c6c25a0240",
      "old_mode": 33188,
      "old_path": "drivers/pci/pci.c",
      "new_id": "2d373ab3ccb383e1577b122bb59c6e48d10187b1",
      "new_mode": 33188,
      "new_path": "drivers/pci/pci.c"
    }
  ]
}