// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <3>;
			enable-method = "psci";
		};
	};

	de: display-engine {
		compatible = "allwinner,sun50i-h6-display-engine";
		allwinner,pipelines = <&mixer0>;
		status = "disabled";
	};

	osc24M: osc24M_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "osc24M";
	};

	ext_osc32k: ext_osc32k_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "ext_osc32k";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		bus@1000000 {
			compatible = "allwinner,sun50i-h6-de3",
				     "allwinner,sun50i-a64-de2";
			reg = <0x1000000 0x400000>;
			allwinner,sram = <&de2_sram 1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x1000000 0x400000>;

			display_clocks: clock@0 {
				compatible = "allwinner,sun50i-h6-de3-clk";
				reg = <0x0 0x10000>;
				clocks = <&ccu CLK_DE>,
					 <&ccu CLK_BUS_DE>;
				clock-names = "mod",
					      "bus";
				resets = <&ccu RST_BUS_DE>;
				#clock-cells = <1>;
				#reset-cells = <1>;
			};

			mixer0: mixer@100000 {
				compatible = "allwinner,sun50i-h6-de3-mixer-0";
				reg = <0x100000 0x100000>;
				clocks = <&display_clocks CLK_BUS_MIXER0>,
					 <&display_clocks CLK_MIXER0>;
				clock-names = "bus",
					      "mod";
				resets = <&display_clocks RST_MIXER0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					mixer0_out: port@1 {
						reg = <1>;

						mixer0_out_tcon_top_mixer0: endpoint {
							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
						};
					};
				};
			};
		};

		video-codec@1c0e000 {
			compatible = "allwinner,sun50i-h6-video-engine";
			reg = <0x01c0e000 0x2000>;
			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
				 <&ccu CLK_MBUS_VE>;
			clock-names = "ahb", "mod", "ram";
			resets = <&ccu RST_BUS_VE>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			allwinner,sram = <&ve_sram 1>;
		};

		syscon: syscon@3000000 {
			compatible = "allwinner,sun50i-h6-system-control",
				     "allwinner,sun50i-a64-system-control";
			reg = <0x03000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_c: sram@28000 {
				compatible = "mmio-sram";
				reg = <0x00028000 0x1e000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00028000 0x1e000>;

				de2_sram: sram-section@0 {
					compatible = "allwinner,sun50i-h6-sram-c",
						     "allwinner,sun50i-a64-sram-c";
					reg = <0x0000 0x1e000>;
				};
			};

			sram_c1: sram@1a00000 {
				compatible = "mmio-sram";
				reg = <0x01a00000 0x200000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x01a00000 0x200000>;

				ve_sram: sram-section@0 {
					compatible = "allwinner,sun50i-h6-sram-c1",
						     "allwinner,sun4i-a10-sram-c1";
					reg = <0x000000 0x200000>;
				};
			};
		};

		ccu: clock@3001000 {
			compatible = "allwinner,sun50i-h6-ccu";
			reg = <0x03001000 0x1000>;
			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		dma: dma-controller@3002000 {
			compatible = "allwinner,sun50i-h6-dma";
			reg = <0x03002000 0x1000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
			clock-names = "bus", "mbus";
			dma-channels = <16>;
			dma-requests = <46>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		sid: efuse@3006000 {
			compatible = "allwinner,sun50i-h6-sid";
			reg = <0x03006000 0x400>;
		};

		watchdog: watchdog@30090a0 {
			compatible = "allwinner,sun50i-h6-wdt",
				     "allwinner,sun6i-a31-wdt";
			reg = <0x030090a0 0x20>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
			/* Broken on some H6 boards */
			status = "disabled";
		};

		pio: pinctrl@300b000 {
			compatible = "allwinner,sun50i-h6-pinctrl";
			reg = <0x0300b000 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			ext_rgmii_pins: rgmii-pins {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
				       "PD5", "PD7", "PD8", "PD9", "PD10",
				       "PD11", "PD12", "PD13", "PD19", "PD20";
				function = "emac";
				drive-strength = <40>;
			};

			hdmi_pins: hdmi-pins {
				pins = "PH8", "PH9", "PH10";
				function = "hdmi";
			};

			i2c0_pins: i2c0-pins {
				pins = "PD25", "PD26";
				function = "i2c0";
			};

			i2c1_pins: i2c1-pins {
				pins = "PH5", "PH6";
				function = "i2c1";
			};

			i2c2_pins: i2c2-pins {
				pins = "PD23", "PD24";
				function = "i2c2";
			};

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			/omit-if-no-ref/
			mmc1_pins: mmc1-pins {
				pins = "PG0", "PG1", "PG2", "PG3",
				       "PG4", "PG5";
				function = "mmc1";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_pins: mmc2-pins {
				pins = "PC1", "PC4", "PC5", "PC6",
				       "PC7", "PC8", "PC9", "PC10",
				       "PC11", "PC12", "PC13", "PC14";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			spdif_tx_pin: spdif-tx-pin {
				pins = "PH7";
				function = "spdif";
			};

			uart0_ph_pins: uart0-ph-pins {
				pins = "PH0", "PH1";
				function = "uart0";
			};
		};

		gic: interrupt-controller@3021000 {
			compatible = "arm,gic-400";
			reg = <0x03021000 0x1000>,
			      <0x03022000 0x2000>,
			      <0x03024000 0x2000>,
			      <0x03026000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		mmc0: mmc@4020000 {
			compatible = "allwinner,sun50i-h6-mmc",
				     "allwinner,sun50i-a64-mmc";
			reg = <0x04020000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc0_pins>;
			max-frequency = <150000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@4021000 {
			compatible = "allwinner,sun50i-h6-mmc",
				     "allwinner,sun50i-a64-mmc";
			reg = <0x04021000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc1_pins>;
			max-frequency = <150000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@4022000 {
			compatible = "allwinner,sun50i-h6-emmc",
				     "allwinner,sun50i-a64-emmc";
			reg = <0x04022000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc2_pins>;
			max-frequency = <150000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		uart0: serial@5000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x05000000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		uart1: serial@5000400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x05000400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			status = "disabled";
		};

		uart2: serial@5000800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x05000800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			status = "disabled";
		};

		uart3: serial@5000c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x05000c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART3>;
			resets = <&ccu RST_BUS_UART3>;
			status = "disabled";
		};

		i2c0: i2c@5002000 {
			compatible = "allwinner,sun50i-h6-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x05002000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@5002400 {
			compatible = "allwinner,sun50i-h6-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x05002400 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@5002800 {
			compatible = "allwinner,sun50i-h6-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x05002800 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		emac: ethernet@5020000 {
			compatible = "allwinner,sun50i-h6-emac",
				     "allwinner,sun50i-a64-emac";
			syscon = <&syscon>;
			reg = <0x05020000 0x10000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			resets = <&ccu RST_BUS_EMAC>;
			reset-names = "stmmaceth";
			clocks = <&ccu CLK_BUS_EMAC>;
			clock-names = "stmmaceth";
			status = "disabled";

			mdio: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		spdif: spdif@5093000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun50i-h6-spdif";
			reg = <0x05093000 0x400>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
			clock-names = "apb", "spdif";
			resets = <&ccu RST_BUS_SPDIF>;
			dmas = <&dma 2>;
			dma-names = "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&spdif_tx_pin>;
			status = "disabled";
		};

		usb2otg: usb@5100000 {
			compatible = "allwinner,sun50i-h6-musb",
				     "allwinner,sun8i-a33-musb";
			reg = <0x05100000 0x0400>;
			clocks = <&ccu CLK_BUS_OTG>;
			resets = <&ccu RST_BUS_OTG>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usb2phy 0>;
			phy-names = "usb";
			extcon = <&usb2phy 0>;
			status = "disabled";
		};

		usb2phy: phy@5100400 {
			compatible = "allwinner,sun50i-h6-usb-phy";
			reg = <0x05100400 0x24>,
			      <0x05101800 0x4>,
			      <0x05311800 0x4>;
			reg-names = "phy_ctrl",
				    "pmu0",
				    "pmu3";
			clocks = <&ccu CLK_USB_PHY0>,
				 <&ccu CLK_USB_PHY3>;
			clock-names = "usb0_phy",
				      "usb3_phy";
			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY3>;
			reset-names = "usb0_reset",
				      "usb3_reset";
			status = "disabled";
			#phy-cells = <1>;
		};

		ehci0: usb@5101000 {
			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
			reg = <0x05101000 0x100>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>,
				 <&ccu CLK_BUS_EHCI0>,
				 <&ccu CLK_USB_OHCI0>;
			resets = <&ccu RST_BUS_OHCI0>,
				 <&ccu RST_BUS_EHCI0>;
			phys = <&usb2phy 0>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@5101400 {
			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
			reg = <0x05101400 0x100>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>,
				 <&ccu CLK_USB_OHCI0>;
			resets = <&ccu RST_BUS_OHCI0>;
			phys = <&usb2phy 0>;
			phy-names = "usb";
			status = "disabled";
		};

		ehci3: usb@5311000 {
			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
			reg = <0x05311000 0x100>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI3>,
				 <&ccu CLK_BUS_EHCI3>,
				 <&ccu CLK_USB_OHCI3>;
			resets = <&ccu RST_BUS_OHCI3>,
				 <&ccu RST_BUS_EHCI3>;
			phys = <&usb2phy 3>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci3: usb@5311400 {
			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
			reg = <0x05311400 0x100>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI3>,
				 <&ccu CLK_USB_OHCI3>;
			resets = <&ccu RST_BUS_OHCI3>;
			phys = <&usb2phy 3>;
			phy-names = "usb";
			status = "disabled";
		};

		hdmi: hdmi@6000000 {
			compatible = "allwinner,sun50i-h6-dw-hdmi";
			reg = <0x06000000 0x10000>;
			reg-io-width = <1>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
				      "hdcp-bus";
			resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
			reset-names = "ctrl", "hdcp";
			phys = <&hdmi_phy>;
			phy-names = "phy";
			pinctrl-names = "default";
			pinctrl-0 = <&hdmi_pins>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				hdmi_in: port@0 {
					reg = <0>;

					hdmi_in_tcon_top: endpoint {
						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
					};
				};

				hdmi_out: port@1 {
					reg = <1>;
				};
			};
		};

		hdmi_phy: hdmi-phy@6010000 {
			compatible = "allwinner,sun50i-h6-hdmi-phy";
			reg = <0x06010000 0x10000>;
			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
			clock-names = "bus", "mod";
			resets = <&ccu RST_BUS_HDMI>;
			reset-names = "phy";
			#phy-cells = <0>;
		};

		tcon_top: tcon-top@6510000 {
			compatible = "allwinner,sun50i-h6-tcon-top";
			reg = <0x06510000 0x1000>;
			clocks = <&ccu CLK_BUS_TCON_TOP>,
				 <&ccu CLK_TCON_TV0>;
			clock-names = "bus",
				      "tcon-tv0";
			clock-output-names = "tcon-top-tv0";
			resets = <&ccu RST_BUS_TCON_TOP>;
			reset-names = "rst";
			#clock-cells = <1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon_top_mixer0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon_top_mixer0_in_mixer0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
					};
				};

				tcon_top_mixer0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
					};
				};

				tcon_top_hdmi_in: port@4 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <4>;

					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon_tv_out_tcon_top>;
					};
				};

				tcon_top_hdmi_out: port@5 {
					reg = <5>;

					tcon_top_hdmi_out_hdmi: endpoint {
						remote-endpoint = <&hdmi_in_tcon_top>;
					};
				};
			};
		};

		tcon_tv: lcd-controller@6515000 {
			compatible = "allwinner,sun50i-h6-tcon-tv",
				     "allwinner,sun8i-r40-tcon-tv";
			reg = <0x06515000 0x1000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_TCON_TV0>,
				 <&tcon_top CLK_TCON_TOP_TV0>;
			clock-names = "ahb",
				      "tcon-ch1";
			resets = <&ccu RST_BUS_TCON_TV0>;
			reset-names = "lcd";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon_tv_in: port@0 {
					reg = <0>;

					tcon_tv_in_tcon_top_mixer0: endpoint {
						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
					};
				};

				tcon_tv_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon_tv_out_tcon_top: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
					};
				};
			};
		};

		rtc: rtc@7000000 {
			compatible = "allwinner,sun50i-h6-rtc";
			reg = <0x07000000 0x400>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clock-output-names = "osc32k", "osc32k-out", "iosc";
			clocks = <&ext_osc32k>;
			#clock-cells = <1>;
		};

		r_ccu: clock@7010000 {
			compatible = "allwinner,sun50i-h6-r-ccu";
			reg = <0x07010000 0x400>;
			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
				 <&ccu CLK_PLL_PERIPH0>;
			clock-names = "hosc", "losc", "iosc", "pll-periph";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_watchdog: watchdog@7020400 {
			compatible = "allwinner,sun50i-h6-wdt",
				     "allwinner,sun6i-a31-wdt";
			reg = <0x07020400 0x20>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		r_intc: interrupt-controller@7021000 {
			compatible = "allwinner,sun50i-h6-r-intc",
				     "allwinner,sun6i-a31-r-intc";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x07021000 0x400>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		};

		r_pio: pinctrl@7022000 {
			compatible = "allwinner,sun50i-h6-r-pinctrl";
			reg = <0x07022000 0x400>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			r_i2c_pins: r-i2c-pins {
				pins = "PL0", "PL1";
				function = "s_i2c";
			};

			r_ir_rx_pin: r-ir-rx-pin {
				pins = "PL9";
				function = "s_cir_rx";
			};
		};

		r_ir: ir@7040000 {
				compatible = "allwinner,sun50i-h6-ir",
					     "allwinner,sun6i-a31-ir";
				reg = <0x07040000 0x400>;
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&r_ccu CLK_R_APB1_IR>,
					 <&r_ccu CLK_IR>;
				clock-names = "apb", "ir";
				resets = <&r_ccu RST_R_APB1_IR>;
				pinctrl-names = "default";
				pinctrl-0 = <&r_ir_rx_pin>;
				status = "disabled";
		};

		r_i2c: i2c@7081400 {
			compatible = "allwinner,sun50i-h6-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x07081400 0x400>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB2_I2C>;
			resets = <&r_ccu RST_R_APB2_I2C>;
			pinctrl-names = "default";
			pinctrl-0 = <&r_i2c_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};