)]}'
{
  "commit": "b4e2b74f69781ba034266aca355822bfd298a2cf",
  "tree": "b93c44a6e9f5104ad14eb5ea417e041e827a9717",
  "parents": [
    "8d185636a6299ff9d2e9eec3a4a25026c13d2351"
  ],
  "author": {
    "name": "Jim Quinlan",
    "email": "james.quinlan@broadcom.com",
    "time": "Mon Jan 05 12:34:19 2026 -0500"
  },
  "committer": {
    "name": "Greg Kroah-Hartman",
    "email": "gregkh@linuxfoundation.org",
    "time": "Thu Jan 08 10:15:04 2026 +0100"
  },
  "message": "PCI: brcmstb: Set MLW based on \"num-lanes\" DT property if present\n\n[ Upstream commit a364d10ffe361fb34c3838d33604da493045de1e ]\n\nBy default, the driver relies on the default hardware defined value for the\nMax Link Width (MLW) capability. But if the \"num-lanes\" DT property is\npresent, assume that the chip\u0027s default capability information is incorrect\nor undesired, and use the specified value instead.\n\nSigned-off-by: Jim Quinlan \u003cjames.quinlan@broadcom.com\u003e\n[mani: reworded the description and comments]\nSigned-off-by: Manivannan Sadhasivam \u003cmani@kernel.org\u003e\nReviewed-by: Florian Fainelli \u003cflorian.fainelli@broadcom.com\u003e\nLink: https://patch.msgid.link/20250530224035.41886-3-james.quinlan@broadcom.com\nStable-dep-of: 9583f9d22991 (\"PCI: brcmstb: Fix disabling L0s capability\")\nSigned-off-by: Sasha Levin \u003csashal@kernel.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@linuxfoundation.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "62e1d661ee0b579cf46db0d34fbbd459b848a8ac",
      "old_mode": 33188,
      "old_path": "drivers/pci/controller/pcie-brcmstb.c",
      "new_id": "29f0da00c7297a64c0ce7d77b8b481e7b82bdadd",
      "new_mode": 33188,
      "new_path": "drivers/pci/controller/pcie-brcmstb.c"
    }
  ]
}