// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2019 NXP.
 *
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A FRWY Board";
	compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "LT8642SEV-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&duart2 {
	status = "okay";
};

&duart3 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9546";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			power-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};

			eeprom@52 {
				compatible = "onnn,cat24c04", "atmel,24c04";
				reg = <0x52>;
			};
		};
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NAND Flash */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
	};

	ethernet@f2000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
	};

	mdio@fd000 {
		qsgmii_phy1: ethernet-phy@1c {
			reg = <0x1c>;
		};

		qsgmii_phy2: ethernet-phy@1d {
			reg = <0x1d>;
		};

		qsgmii_phy3: ethernet-phy@1e {
			reg = <0x1e>;
		};

		qsgmii_phy4: ethernet-phy@1f {
			reg = <0x1f>;
		};
	};
};