// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2016 Endless Computers, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

#include "meson-gxl.dtsi"

/ {
	compatible = "amlogic,meson-gxm";

	cpus {
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			clocks = <&scpi_dvfs 1>;
		};
	};
};

&apb {
	usb2_phy2: phy@78040 {
		compatible = "amlogic,meson-gxl-usb2-phy";
		#phy-cells = <0>;
		reg = <0x0 0x78040 0x0 0x20>;
		clocks = <&clkc CLKID_USB>;
		clock-names = "phy";
		resets = <&reset RESET_USB_OTG>;
		reset-names = "phy";
		status = "okay";
	};

	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gpu", "mmu", "job";
		clocks = <&clkc CLKID_MALI>;
		resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
				       <666666666>,
				       <0>; /* Do Nothing */
	};
};

&clkc_AO {
	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
};

&saradc {
	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
};

&scpi_dvfs {
	clock-indices = <0 1>;
	clock-output-names = "vbig", "vlittle";
};

&vpu {
	compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
};

&hdmi_tx {
	compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};

&dwc3 {
	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
};

&vdec {
	compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
};