What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
Date:		April 2015
KernelVersion:  4.01
Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Enable/disable tracing on this specific trace entiry.
		Enabling a source implies the source has been configured
		properly and a sink has been identidifed for it.  The path
		of coresight components linking the source to the sink is
		configured and managed automatically by the coresight framework.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) The CPU this tracing entity is associated with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of PE comparator inputs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of address comparator pairs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of counters that are available for
		tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates how many external inputs are implemented.

What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of Context ID comparators that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of VMID comparators that are available
		for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of sequencer states that are
		implemented.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of resource selection pairs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of single-shot comparator controls that
		are available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(W) Cancels all configuration on a trace unit and set it back
		to its boot configuration.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls various modes supported by this ETM, for example
		P0 instruction tracing, branch broadcast, cycle counting and
		context ID tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls which PE to trace.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the behavior of the events in bank 0 to 3.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the insertion of global timestamps in the trace
		streams.

What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls how often trace synchronization requests occur.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Sets the threshold value for cycle counting.

What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls which regions in the memory map are enabled to
		use branch broadcasting.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls instruction trace filtering.

What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) In Secure state, each bit controls whether instruction
		tracing is enabled for the corresponding exception level.

What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) In non-secure state, each bit controls whether instruction
		tracing is enabled for the corresponding exception level.

What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Select which address comparator or pair (of comparators) to
		work with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls what type of comparison the trace unit performs.

What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Used to setup single address comparator values.

What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Used to setup address range comparator values.

What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Select which sequensor.

What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Use this to set, or read, the sequencer state.

What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Moves the sequencer state to a specific state.

What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Moves the sequencer to state 0 when a programmed event
		occurs.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Select which counter unit to work with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) This sets or returns the reload count value of the
		specific counter.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) This sets or returns the current count value of the
                specific counter.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the operation of the selected counter.

What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Select which resource selection unit to work with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the selection of the resources in the trace unit.

What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Select which context ID comparator to work with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Get/Set the context ID comparator value to trigger on.

What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Mask for all 8 context ID comparator value
		registers (if implemented).

What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Select which virtual machine ID comparator to work with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Get/Set the virtual machine ID comparator value to
		trigger on.

What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Mask for all 8 virtual machine ID comparator value
		registers (if implemented).

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the OS Lock Status Register (0x304).
		The value it taken directly  from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Power Down Control Register
		(0x310).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Power Down Status Register
		(0x314).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the SW Lock Status Register
		(0xFB4).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Authentication Status Register
		(0xFB8).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Device ID Register
		(0xFC8).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Device Type Register
		(0xFCC).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Peripheral ID0 Register
		(0xFE0).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Peripheral ID1 Register
		(0xFE4).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Peripheral ID2 Register
		(0xFE8).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the Peripheral ID3 Register
		(0xFEC).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
Date:		February 2016
KernelVersion:	4.07
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the trace configuration register
		(0x010) as currently set by SW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
Date:		February 2016
KernelVersion:	4.07
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Print the content of the trace ID register (0x040).

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
		The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
		The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the maximum size of the data value, data address,
		VMID, context ID and instuction address in the trace unit
		(0x1E8).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the value associated with various resources
		available to the trace unit.  See the Trace Macrocell
		architecture specification for more details (0x1E8).
		The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns how many resources the trace unit supports (0x1F0).
		The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns how many resources the trace unit supports (0x1F4).
		The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the maximum speculation depth of the instruction
		trace stream. (0x180).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the number of P0 right-hand keys that the trace unit
		can use (0x184).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the number of P1 right-hand keys that the trace unit
		can use (0x188).  The value is taken directly from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the number of special P1 right-hand keys that the
		trace unit can use (0x18C).  The value is taken directly from
		the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the number of conditional P1 right-hand keys that
		the trace unit can use (0x190).  The value is taken directly
		from the HW.

What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Returns the number of special conditional P1 right-hand keys
		that the trace unit can use (0x194).  The value is taken
		directly from the HW.