exynos: Correct clock divider calculation
Due to a bug in clock_set_periph_rate(), peripherals do not use
the correct parent clock rate when their divider is being calculated.
Instead they use the current value of the peripheral clock. Fix
clock_set_periph_rate() so that the source PLL rate is used to
calculate the dividers. Also fix an off-by-one error in the
pre-divider calculation.
BUG=chrome-os-partner:21741
BRANCH=pit
TEST=manual
Boot through RO and RW U-Boot with both set to set up SDMMC0. Before this
change, in RW U-Boot the eMMC would have about 500ms to load the kernel
because it is running at a very slow clock. With this change, the speed
of kernel loading is correct (90ms).
Boot time for RO drops by 15ms from 720ms to 705ms
Boot time for RW drops by 345ms from 1240ms to 895ms
Change-Id: I10cd6b9efa13e4f85c4b72740dce4fbdd3626e30
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169104
1 file changed
