UPSTREAM: socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit e26ecebc684bfe74f6c27cca151c3490d1ed5d8f)
Change-Id: Id14aeb2077245b7781e9e4866530b620ed9c68ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/u-boot/+/3673315
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Paweł Anikiel <panikiel@google.com>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
1 file changed
