)]}'
{
  "log": [
    {
      "commit": "e59ef7002bf3f0a1702222e55117a05149a3213e",
      "tree": "718a14deea6074e77c079eb1ba53b7b4eecdd799",
      "parents": [
        "edf528bfea0fcf768436e8e05a1397ce902bc892"
      ],
      "author": {
        "name": "Chris McDonald",
        "email": "cjmcdonald@chromium.org",
        "time": "Mon Jun 24 15:10:24 2019 -0600"
      },
      "committer": {
        "name": "Chris McDonald",
        "email": "cjmcdonald@chromium.org",
        "time": "Mon Jun 24 21:12:38 2019 +0000"
      },
      "message": "coreboot: Add OWNERS file\n\nBUG\u003db:132095048\nTEST\u003dNone\n\nChange-Id: Id046d6e2b1de0b249d66c13b615270b0e1eac668\nReviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1674570\n"
    },
    {
      "commit": "edf528bfea0fcf768436e8e05a1397ce902bc892",
      "tree": "6216f96cebc9df11726830848f4c875511a0c605",
      "parents": [
        "796af17f18554380a49d69d7768ac18ee039d711"
      ],
      "author": {
        "name": "Bernie Thompson",
        "email": "bhthompson@google.com",
        "time": "Fri Feb 08 11:48:12 2019 -0800"
      },
      "committer": {
        "name": "ChromeOS Commit Bot",
        "email": "chromeos-commit-bot@chromium.org",
        "time": "Fri Feb 08 20:33:57 2019 +0000"
      },
      "message": "Replace coreboot contents with README.txt file\n\nAs Chrome OS does not use the master branch of coreboot, we stub\nit out with just a README.txt file.\n\n\"\nThese are not the sources you are looking for.\n\nThe master branch of Coreboot is not used for Chrome OS.\n\nPlease pick a chromeos-* branch, most likely \"chromeos-2016.05\".\n\"\n\nBUG\u003dchromium:812290\nTEST\u003dNone\n\nChange-Id: I6c8a9945d67e37ab6bb8b540be0a3404c75e4f34\nReviewed-on: https://chromium-review.googlesource.com/c/1461163\nReviewed-by: Bernie Thompson \u003cbhthompson@chromium.org\u003e\nCommit-Queue: Bernie Thompson \u003cbhthompson@chromium.org\u003e\nTested-by: Bernie Thompson \u003cbhthompson@chromium.org\u003e\n"
    },
    {
      "commit": "796af17f18554380a49d69d7768ac18ee039d711",
      "tree": "c0413b06c8e52e883d7d8288f713b23b06280a3c",
      "parents": [
        "5383a415ed1ecf52579d6b8c2de1fbf9d86a8996"
      ],
      "author": {
        "name": "Ted Kuo",
        "email": "tedkuo@ami.com.tw",
        "time": "Wed Mar 18 10:42:22 2015 +0800"
      },
      "committer": {
        "name": "ChromeOS Commit Bot",
        "email": "chromeos-commit-bot@chromium.org",
        "time": "Fri Apr 10 01:27:45 2015 +0000"
      },
      "message": "IT8772F: Add switch to enable HWM(Hardware Monitor)\n\nSetup External Temperature to read via thermal diode/resistor\ninto TMPINx register by setting thermal_mode switch.\n\nBUG\u003dnone\nTEST\u003dCompiled, verified\nSigned-off-by: Ted Kuo \u003ctedkuo@ami.com.tw\u003e\n\nChange-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034\nReviewed-on: https://chromium-review.googlesource.com/260545\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\nCommit-Queue: Ted Kuo \u003ctedkuo@ami.com.tw\u003e\nTested-by: Ted Kuo \u003ctedkuo@ami.com.tw\u003e\n(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)\nReviewed-on: https://chromium-review.googlesource.com/262340\n"
    },
    {
      "commit": "5383a415ed1ecf52579d6b8c2de1fbf9d86a8996",
      "tree": "847d97594c650a0322d875d0c880b42cd50eada1",
      "parents": [
        "84defb44fabf2e81498c689d1b0713a479162fae"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Jan 21 15:28:38 2014 -0600"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Feb 19 02:33:56 2014 +0000"
      },
      "message": "UPSTREAM: cbfstool: correct size left calculation for \"empty\" entries\n\nAfter removing a file sandwiched between two other files, that file\ncould no longer be re-added at the same location. cbfstool tried to\nadd the file, and a new \"empty\" entry, which, together, would no\nlonger fit, so it continued checking for the next available space.\n\nChange the behavior to add the file if there is enough space for the\nfile alone, then only add the \"empty\" entry if there is enough space\nfor it.\n\nChange-Id: Ia20f690f902aa7ea1a7c5fa62ca33436cf52d2ab\nSigned-off-by: Alexandru Gagniuc \u003cmr.nuke.me@gmail.com\u003e\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/186982\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "84defb44fabf2e81498c689d1b0713a479162fae",
      "tree": "13b4471dad81fc0b798f60a912c63406b668a3b4",
      "parents": [
        "a4f2dd4902a05884693e6e350b6be29276d16981"
      ],
      "author": {
        "name": "Martin Roth",
        "email": "martin.roth@se-eng.com",
        "time": "Fri Oct 11 12:34:53 2013 -0600"
      },
      "committer": {
        "name": "Martin Roth",
        "email": "martin.roth@se-eng.com",
        "time": "Fri Oct 11 20:12:27 2013 +0000"
      },
      "message": "baytrail: com1 is a reserved word in windows, rename to uart.c\n\nCoreboot was failing to build on windows because com1\nis a reserved keyword under windows.  I\u0027m renaming\nit to soc/intel/baytrail/romstage/uart.c.\n\nBUG\u003dNone\nBRANCH\u003dNone\nTEST\u003dBuilt and verified uart.c was compiled in.\n\nChange-Id: I9d1fb65944016e43a08f5c6517d86dc66993b973\nSigned-off-by: Martin Roth \u003cmartin.roth@se-eng.com\u003e\n"
    },
    {
      "commit": "a4f2dd4902a05884693e6e350b6be29276d16981",
      "tree": "1dfe3b4c93c9c9b2ea74027502be86bfba32edd2",
      "parents": [
        "f0a1366d328f84e720fe7768cecfe57b3e7dca79"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Wed Oct 09 23:45:07 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 11 03:58:38 2013 +0000"
      },
      "message": "tegra124: Make tegra124 compilable with serial turned off.\n\nThe bootblock and romstage UART consoles were being built in based only on\nwhether or not the bootblock and romstage consoles were selected, ignoring\nwhether serial console support was compiled in generally.\n\nBUG\u003dNone\nTEST\u003dBuilt for nyan with and without serial.\nBRANCH\u003dNone\n\nChange-Id: I3866519c422a990c44ced66885108eff24894563\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172580\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "f0a1366d328f84e720fe7768cecfe57b3e7dca79",
      "tree": "2fd03fe221fb147f67e24a7b0779155db6739798",
      "parents": [
        "2d0cd2190b1f394dc9ac1ee7844942575a520be1"
      ],
      "author": {
        "name": "Stefan Reinauer",
        "email": "reinauer@chromium.org",
        "time": "Thu Oct 03 12:07:59 2013 +0800"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 11 03:58:01 2013 +0000"
      },
      "message": "beltino: get ChromeOS up and running\n\nBRANCH\u003dnone\nBUG\u003dnone\nTEST\u003dboot ChromeOS on Beltino\n\nSigned-off-by: Stefan Reinauer \u003creinauer@google.com\u003e\n\nChange-Id: I6db35b0675f8c1c3d81d34c3b28adf8519de224f\nReviewed-on: https://chromium-review.googlesource.com/171554\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nTested-by: Stefan Reinauer \u003creinauer@chromium.org\u003e\nCommit-Queue: Stefan Reinauer \u003creinauer@chromium.org\u003e\n"
    },
    {
      "commit": "2d0cd2190b1f394dc9ac1ee7844942575a520be1",
      "tree": "846a645a830f019bc1decff599974dc18d7de792",
      "parents": [
        "5ef93446471589941c7bedc84bdd49a0ae3e2bbb"
      ],
      "author": {
        "name": "Stefan Reinauer",
        "email": "reinauer@chromium.org",
        "time": "Mon Oct 07 16:29:54 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 11 03:57:57 2013 +0000"
      },
      "message": "lynxpoint: Export pch_enable_lpc() for SuperIO systems\n\nIn order to enable a SuperIO in non ChromeEC systems we\nneed to make pch_enable_lpc() available to the mainboard\nromstage.c\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dboot ChromeOS on Beltino\n\nChange-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de\nSigned-off-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172180\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Stefan Reinauer \u003creinauer@chromium.org\u003e\n"
    },
    {
      "commit": "5ef93446471589941c7bedc84bdd49a0ae3e2bbb",
      "tree": "8b23468687cc4605a7a82dcf58c50eecc8feb4b8",
      "parents": [
        "d49358f7959bb52c3e7ff67d37c21a1b294adf72"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Thu Oct 10 12:41:49 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 20:48:43 2013 +0000"
      },
      "message": "x86: add common definitions for control registers\n\nThe access to control registers were scattered about.\nProvide a single header file to provide the correct\naccess function and definitions.\n\nBUG\u003dchrome-os-partner:22991\nBRANCH\u003dNone\nTEST\u003dBuilt and booted using this infrastructure. Also objdump\u0027d the\n     assembly to ensure consistency (objdump -d -r -S | grep xmm).\n\nChange-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172641\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\n"
    },
    {
      "commit": "d49358f7959bb52c3e7ff67d37c21a1b294adf72",
      "tree": "d666631d253cb6759f9ba9fbcad380265d65587e",
      "parents": [
        "572f49e9655abb673ee69d51de6b48852cf865df"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Thu Oct 10 12:44:11 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 20:48:38 2013 +0000"
      },
      "message": "xcompile: always use -march\u003di686\n\nWhen compiling coreboot for x86 on gcc the compiler is\nfree to pick whatever defaults it is using at the time of\ngcc\u0027s compile/configuration when no -march is specified.\nNot properly specifying -march then opens up the use of SSE\ninstructions for copmilation units it should not be used such\nas the SMM module as this module doesn\u0027t save/restore SSE\nregisters.\n\nBUG\u003dchrome-os-partner:22991\nBRANCH\u003dNone\nTEST\u003dBuilt and confirmed -march\u003di686 was used on command line. Also\n     noted not xmm registers were produced grep\u0027ing through objdump\n     output.\n\nChange-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172640\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\n"
    },
    {
      "commit": "572f49e9655abb673ee69d51de6b48852cf865df",
      "tree": "7219fb93d3edf23dc1a146fad11908a0a10d1e0a",
      "parents": [
        "ecec80e062f7efe32a9a17479dcf8cb678a4a98b"
      ],
      "author": {
        "name": "Bernie Thompson",
        "email": "bhthompson@chromium.org",
        "time": "Thu Oct 10 09:33:12 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 19:19:20 2013 +0000"
      },
      "message": "Provide libpayload configuration for rambi board\n\nThis is a direct copy of the bayleybay configuration.\n\nBUG\u003dchrome-os-partner:23121\nTEST\u003demerge-rambi libpayload\n\nChange-Id: Ib90f5797b4656ac366d16da5f3243fea20357dc5\nReviewed-on: https://chromium-review.googlesource.com/172587\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Bernie Thompson \u003cbhthompson@chromium.org\u003e\nTested-by: Bernie Thompson \u003cbhthompson@chromium.org\u003e\n"
    },
    {
      "commit": "ecec80e062f7efe32a9a17479dcf8cb678a4a98b",
      "tree": "ec4d54cdbc7d80318810fe2e68b32ea881b93c4d",
      "parents": [
        "e512c8bcaa5b8e05cae3b9d04cd4947298de999d"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Tue Sep 17 22:16:04 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:40 2013 +0000"
      },
      "message": "libpayload: usb: Refactor USB enumeration to fix SuperSpeed devices\n\nThis patch represents a major overhaul of the USB enumeration code in\norder to make it cleaner and much more robust to weird or malicious\ndevices. The main improvement is that it correctly parses the USB\ndescriptors even if there are unknown descriptors interspersed within,\nwhich is perfectly legal and in particular present on all SuperSpeed\ndevices (due to the SuperSpeed Endpoint Companion Descriptor).\n\nIn addition, it gets rid of the really whacky and special cased\nget_descriptor() function, which would read every descriptor twice\nwhether it made sense or not. The new code makes the callers allocate\ndescriptor memory and only read stuff twice when it\u0027s really necessary\n(i.e. the device and configuration descriptors).\n\nFinally, it also moves some more responsibilities into the\ncontroller-specific set_address() function in order to make sure things\nare initialized at the same stage for all controllers. In the new model\nit initializes the device entry (which zeroes the endpoint array), sets\nup endpoint 0 (including MPS), sets the device address and finally\nreturns the whole usbdev_t structure with that address correctly set.\n\nNote that this should make SuperSpeed devices work, but SuperSpeed hubs\nare a wholly different story and would require a custom hub driver\n(since the hub descriptor and port status formats are different for USB\n3.0 ports, and the whole issue about the same hub showing up as two\ndifferent devices on two different ports might present additional\nchallenges). The stack currently just issues a warning and refuses to\ninitialize this part of the hub, which means that 3.0 devices connected\nthrough a 3.0 hub may not work correctly.\n\nBUG\u003dchrome-os-partner:22139\nTEST\u003dManual\n\nChange-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170666\nReviewed-by: Kees Cook \u003ckeescook@chromium.org\u003e\n"
    },
    {
      "commit": "e512c8bcaa5b8e05cae3b9d04cd4947298de999d",
      "tree": "6292a06cd0b09c56a2c1c63e2a06fbc8bdc3d73f",
      "parents": [
        "4c6dd4c7cade7d922a258e0371e43972bce77249"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Fri Sep 27 12:45:11 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:36 2013 +0000"
      },
      "message": "libpayload: xhci: Use Event Data TRBs for transfer event generation\n\nThe current XHCI code only sets IOC on the last TRB of a TD, and\ndoesn\u0027t set ISP anywhere. On my Synopsys DesignWare3 controller, this\nwon\u0027t generate an event at all when we have a short transfer that is not\non the last TRB of a TD, resulting in event ring desync and everyone\nhaving a bad time. However, just setting ISP on other TRBs doesn\u0027t\nreally make for a nice solution: we then need to do ugly special casing\nto fish out the spurious second transfer event you get for short\npackets, and we still need a way to figure out how many bytes were\ntransferred. Since the Short Packet transfer event only reports\nuntransferred bytes for the current TRB, we would have to manually walk\nthe rest of the unprocessed TRB chain and add up the bytes. Check out\nU-Boot and the Linux kernel to see how complicated this looks in\npractice.\n\nNow what if we had a way to just tell the HC \"I want an event at exactly\n*this* point in the TD, I want it to have the right completion code for\nthe whole TD, and to contain the exact number of bytes written\"? Enter\nthe Event Data TRB: this little gizmo really does pretty much exactly\nwhat any sane XHCI driver would want, and I have no idea why it isn\u0027t\nused more often. It solves both the short packet event generation and\ncounting the transferred bytes without requiring any special magic in\nsoftware.\n\nBUG\u003dchrome-os-partner:21969\nTEST\u003dManual\n\nChange-Id: Idab412d61edf30655ec69c80066bfffd80290403\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170980\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-by: Kees Cook \u003ckeescook@chromium.org\u003e\n"
    },
    {
      "commit": "4c6dd4c7cade7d922a258e0371e43972bce77249",
      "tree": "c8cff6a488e125ae07761f72cd0f5b89d79e7681",
      "parents": [
        "161a39c53404ea0125221bbd54e54996967d6855"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Oct 06 11:04:33 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:20 2013 +0000"
      },
      "message": "tegra124: Call the set_avp_clock_to_clkm function in the bootblock.\n\nWe had a hardcoded version of the set_avp_clock_to_clkm function in the\nbootblock, and we had to use it until now because the real version uses\nudelay, and until now that hadn\u0027t been implemented. Also, replace the delay\nloop in the hacky_hardcoded_uart_setup_function with a call to the real thing.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan. Verified that there was\nstill serial output.\nBRANCH\u003dNone\n\nChange-Id: I6df9421bcad484e0855c67649683d474d78e4883\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172045\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "161a39c53404ea0125221bbd54e54996967d6855",
      "tree": "4d99b425f080493b6074fd883f8357b7d5aae855",
      "parents": [
        "d29e655b68143e86199ab1d74f89e125b16b67cc"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Oct 06 10:54:53 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:17 2013 +0000"
      },
      "message": "tegra124: Implement the monotonic timer by reading the 1us timer register.\n\nIt turns out there\u0027s a register in tegra which automatically counts at 1us\nincrements. It\u0027s primarily intended for hardware to use (I think to drive\nother timers) but we can read it ourselves since a 1us timer is exactly what\nwe need to support the monotonic timer API.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan with test code in the\nbootblock. Used that code to print two serial messages, 1 minute apart. The\nmessages happened 1 minute and 2 seconds apart. That\u0027s pretty close, although\nit might be worthwhile to figure out where those extra two seconds are coming\nfrom (measurement error?).\nBRANCH\u003dNone\n\nChange-Id: I68e947944acec7b460e61f42dbb325643a9739e8\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172044\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "d29e655b68143e86199ab1d74f89e125b16b67cc",
      "tree": "1c39e5800d933f3d865d76c9d0fe29502f109a57",
      "parents": [
        "5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Fri Oct 04 06:17:22 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:14 2013 +0000"
      },
      "message": "nyan: Use the new pinmux functions as part of UART setup.\n\nThe pins for the UART had been configured manually using hardcoded offsets and\nvalues. Now that we have pinmux functions for that sort of thing, we should\nuse that instead. This also provides a very simple test for the pinmux code.\n\nUltimately this code should be wrapped in a function which handles setting up\nany of the UARTs which is appropriately parameterized and which would be\ncalled from the bootblock main instead of being in it, but for now this is\nsufficient.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan. Saw console output.\nBRANCH\u003dNone\n\nChange-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171807\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a",
      "tree": "765c6cdae33841c8a82e36708b27ff26e0ee48ef",
      "parents": [
        "9100d475ebcc4dae23184583a6cc0162577e70d1"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Oct 03 04:35:01 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:10 2013 +0000"
      },
      "message": "tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.\n\nThe pins on tegra are controlled by three different units, the pinmux, the\npin group controls, and the GPIO banks. Each of these units controls some\naspect of the pins, and they layer together and interact in interesting ways.\n\nBy default, the GPIOs are configured to pass through the special purpose IO\nthat the pinmux is configured to and so can be ignored unless a GPIO is needed.\nThe pinmux controls which special purpose signal passes through, along with\npull ups, downs, and whether the output is tristated. The pingroup controls\nchange the parameters of a group of pins which all have to do with a related\nfunction unit.\n\nThe enum which holds constants related to the pinmux is relatively involved\nand may not be entirely complete or correct due to slightly inconsistent,\nincomplete, or missing docuemtnation related to the pinmux. Considerable\neffort has been made to make it as accurate as possible. It includes a\nconstant which is the index into the pinmux control registers for that pin,\nwhat each of the functions supported by that pin are, and which GPIO it\ncorresponds to. The GPIO constant is named after the GPIO and is the pinmux\nregister index for the pin for that GPIO. That way, when you need to turn on\na GPIO, you can use that constant along with the pinmux manipulating functions\nto enable its tristate and pull up/down mode in addition to setting up the\nGPIO controls.\n\nAlso, while in general I prefer not to use macros or the preprocessor when\nwriting C code, in this case the set of constants in the enums was too large\nand cumbersome to manage without them. Since they\u0027re being used to construct\na table in a straightforward way, hopefully their negative aspects will be\nminimized.\n\nIn addition to the low level functions in each driver, the GPIO code also\nincludes some high level functions to set up input or output GPIOs since that\nwill probably be a very common thing to want to do.\n\nBUG\u003dNone\nTEST\u003dReplaced the hardcoded pinmux configuration code for the UART pins and\nsaw that the UART still worked correctly. Added an infinite loop to the\nbootblock that read and print the value of the lid switch over and over. Ran\nit and toggled the lid switch on servo and saw that the output changed as\nexpected. Repeated that with the dev switch GPIO.\nBRANCH\u003dNone\n\nChange-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171806\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "9100d475ebcc4dae23184583a6cc0162577e70d1",
      "tree": "3f0d04b3e3e4523c7dea233859dc0b466218eef1",
      "parents": [
        "be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 08 23:16:51 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:32:06 2013 +0000"
      },
      "message": "exynos: Fix the name of the chip_operations structures.\n\nThe exynos directories had been moved from src/cpu to src/soc, but the name\nof the chip_operations structure wasn\u0027t updated properly. That meant that the\nSOCs never installed their memory resources and the ram stage would fail to\nload the payload.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted on pit. Before this change, the payload would fail to\nload because no bounce buffer could be found. After this change, ChromeOS\nbooted successfully.\nBRANCH\u003dNone\n\nChange-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172400\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402",
      "tree": "c76c835cddfc7bffe8f74b6e06e06f14e19ba482",
      "parents": [
        "65139f29682cedca8dfb58b3dfe67eab64299064"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 08 18:24:10 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:31:37 2013 +0000"
      },
      "message": "ARM: Use local versions of libgcc functions instead of linking against libgcc.\n\nThe flags used to compile libgcc may make it incompatible with the code it\u0027s\nlinked against, and/or the hardware it\u0027s going to run on. Rather than try to\ntease the right libgcc from the compiler, lets just leave it out and use our\nown implementations of the necessary functions.\n\nMost of these implementations were taken from the Linux kernel, except for\nuldivmod.S which was taken from a CL originally written for U-Boot by\nChe-Liang Chiou in December of 2010. It was modified to not use the CLZ\ninstruction on machines that don\u0027t have it, anything earlier than ARMv5. The\ntop block was taken from an earlier version of the same CL which didn\u0027t use\nCLZ in that spot. The later block was written from scratch.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan. Ran a series of tests which\ndivided and modded a 64 bit value by various 32 bit values which were powers\nof 2. Confirmed that this function was used and that the returned value was\ncorrect. Printed decimal and hex versions of some values and verified that\nthey equaled each other. Built and booted on pit with serial enabled.\nBRANCH\u003dNone\n\nChange-Id: I7527e28af411b7aa7f94579be95a6b352a91a224\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172401\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "65139f29682cedca8dfb58b3dfe67eab64299064",
      "tree": "2457fc1a6b9ca6b17d0a1384a3f90fe96091278f",
      "parents": [
        "8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d"
      ],
      "author": {
        "name": "David Hendricks",
        "email": "dhendrix@chromium.org",
        "time": "Thu Oct 03 14:02:45 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 10 00:31:29 2013 +0000"
      },
      "message": "arm: Update a stale comment in bootblock .S files\n\nThis just updates a comment which refers to \"board_init_f\". We use\nbootblock main() in coreboot.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dlocally compiled.\n\nChange-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0\nReviewed-on: https://chromium-review.googlesource.com/172095\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n"
    },
    {
      "commit": "8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d",
      "tree": "225b9e390df3bf80f0987b56e3babbe9622e6479",
      "parents": [
        "e6343a7ff4c1eb827552285774dfd0f7bde019f5"
      ],
      "author": {
        "name": "Ronald G. Minnich",
        "email": "rminnich@google.com",
        "time": "Tue Oct 01 10:46:35 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 09 17:59:12 2013 +0000"
      },
      "message": "PEPPY/HASWELL: move more support functions from mainboard to the intel i915 driver\n\nMove (and rename to make it clearer) the function that computes display\nparameters from the dpcd and edid.\n\nBUG\u003dNone\nTEST\u003dBuild and boot on peppy. Doesn\u0027t break falco other builds.\nBRANCH\u003dNone\n\nChange-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece\nSigned-off-by: Ronald G. Minnich \u003crminnich@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171366\nReviewed-by: Furquan Shaikh \u003cfurquan.m.shaikh@gmail.com\u003e\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Ronald Minnich \u003crminnich@chromium.org\u003e\n"
    },
    {
      "commit": "e6343a7ff4c1eb827552285774dfd0f7bde019f5",
      "tree": "cba81f22ffd30635941034d90ca9c7c2932721a9",
      "parents": [
        "4f463fe29863b1c73ffe5cb07bbd3f07b0df1b55"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Oct 08 15:33:39 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 09 13:57:00 2013 +0000"
      },
      "message": "rambi: add per-sku SPD support\n\nThere are currently 4 SKUs:\n0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz\n0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz\n0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz\n0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz\n\nAdd each of the 4 spds to the build, and use the proper\nparameters to MRC to use the in-memory SPD information.\n\nBUG\u003dchrome-os-partner:22865\nBRANCH\u003dNone\nTEST\u003dBuilt. Noted 1024 bytes of SPD content.\n\nChange-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172280\n"
    },
    {
      "commit": "4f463fe29863b1c73ffe5cb07bbd3f07b0df1b55",
      "tree": "30d0dcf14c9b377e0012da8ed7688985feced284",
      "parents": [
        "3f6facc7a4d8fcb27a09b2a649685c0ba29524c0"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Oct 08 16:54:18 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 09 13:56:56 2013 +0000"
      },
      "message": "baytrail: move early init to before mainboard\n\nIt\u0027s helpful to have a lot of the early init happen\nbefore the handoff to mainboard. One example of this\nneed is having the BARs programmed so that the mainboard\ncan read board-specific gpios.\n\nBUG\u003dchrome-os-partner:22865\nBRANCH\u003dNone\nTEST\u003dBuilt. Booted and saw console outout in bayleybay\n     mainboard.\n\nSigned-off-by; Aaron Durbin \u003cadurbin@chromium.org\u003e\n\nChange-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe\nReviewed-on: https://chromium-review.googlesource.com/172290\nTested-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nCommit-Queue: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "3f6facc7a4d8fcb27a09b2a649685c0ba29524c0",
      "tree": "eb1c8690715b4871d162f3b69edec48c278cccf1",
      "parents": [
        "79b61016bfd702b0ea5221658305d8bd359f4f62"
      ],
      "author": {
        "name": "Shawn Nematbakhsh",
        "email": "shawnn@chromium.org",
        "time": "Tue Oct 08 11:31:21 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 20:41:20 2013 +0000"
      },
      "message": "baytrail: Add functions to peek at GPIO input values\n\n- Add functions to peek at GPIO input pad values (need to be used from\n  romstage for board ram_id GPIOs)\n- Modify UART GPIOs to use existing fn-assignment function\n\nTEST\u003dManual. Add debug print and verify that GPIO functions return input\nvalues. Also, verify UART still functions in romstage.\nBUG\u003dchrome-os-partner:22865\n\nChange-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77\nSigned-off-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172189\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "79b61016bfd702b0ea5221658305d8bd359f4f62",
      "tree": "e6e07dbdc7af6b8672a93af0891613a99a3ec988",
      "parents": [
        "2c554f58f9ee18e151e824f01c03eb3f0e907858"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Oct 06 06:57:07 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 16:20:22 2013 +0000"
      },
      "message": "tegra124: Add base address for the pinmux and pingroup registers.\n\nThere weren\u0027t any constants for the pinmux or pingroup registers in the\naddress map header.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan.\nBRANCH\u003dNone\n\nChange-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172081\nReviewed-by: Julius Werner \u003cjwerner@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "2c554f58f9ee18e151e824f01c03eb3f0e907858",
      "tree": "941155f106f7235921363f3429ef7bf36f8448a8",
      "parents": [
        "4718e51cbbbca6e8e7c1cfa8e0acb83477bcdd2c"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Oct 06 06:13:24 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 16:20:19 2013 +0000"
      },
      "message": "tegra: Change how tegra124 and tegra include files from each other.\n\nA problem with including the tegra124 directory directly in the include path\nis that it makes all headers in that directory first level headers available\neverywhere including places that have nothing to do with the SOC, even headers\nwhich were only intended for local use by tegra124 code. This change modifies\nthings a bit to be more like the way the arch headers are chosen. In the\ntegra124 directory, there\u0027s an include directory which has an soc subdirectory\nin it. That include directory is added to the include path, making it possible\nto have headers private to the tegra124. When files specific to whatever tegra\nis being built for are needed, you can include \u003csoc/foo.h\u003e and get the version\nspecific to that particular soc.\n\nAlso, the soc.h header file was overhauled to use enums instead of defines, to\nconsistently name things as far as their prefix (the less cryptic TEGRA instead\nof NV_PA) and suffixes like \"BASE\", and to get rid of values which were\nspecific to U-Boot which we don\u0027t need. Since the only thing in the file were\naddress constants, I also renamed the file addressmap.h. It would be included\nas:\n\n\u003csoc/addressmap.h\u003e\n\nwhich I think is easy to remember, does what you\u0027d think it does from the\nname, and won\u0027t conflict with other header files just minding their own\nbusiness in some other directory.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan.\nBRANCH\u003dNone\n\nChange-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/172080\nReviewed-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "4718e51cbbbca6e8e7c1cfa8e0acb83477bcdd2c",
      "tree": "76dd6a24320ec50d9443878c200ec6bbe100b854",
      "parents": [
        "5059648e744e1cccb5f9b2a5dea59592ab92dd00"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Mon Oct 07 17:12:20 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 16:18:37 2013 +0000"
      },
      "message": "baytrail: set max frequency early in romstage\n\nSet the BSP to operate at max frequency early in romstage.\nThe call to punit_init() is when the frequency actually ramps as\nthat makes the punit actually start working.\n\nBUG\u003dchrome-os-partner:22857\nBRANCH\u003dNone\nTEST\u003dBuilt and booted. Noted operating frequency status is max.\n\nChange-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172131\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "5059648e744e1cccb5f9b2a5dea59592ab92dd00",
      "tree": "25e78acfd9a38cf104be6606977a65b1af84e091",
      "parents": [
        "286cede01befd4bbb67af3d476b22aa1264b6474"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Mon Oct 07 16:24:44 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 16:18:30 2013 +0000"
      },
      "message": "baytrail: adjust cache policy during romstage\n\nThe caching policy for romstage was previously using a 32KiB\nof cache-as-ram for both the MRC wrapper and the romstage stack/data.\nIt also used a 32KiB code cache region. The BWG\u0027s limitations for\nthe code and data region before memory is up was wrong. It consists\nof a 16-way set associative 1MiB cache. As long as enough addresses\nare not read there isn\u0027t a risk of evicting the data/stack.\n\nNow create a 64KiB cache-as-ram region split evenly between romstage\nand the MRC wrapper. Additionally cache the memory just below\n4GiB in CBFS size. This will cover any code and read-only data needed.\n\nBUG\u003dchrome-os-partner:22858\nBRANCH\u003dNone\nTEST\u003dBuilt and booted quickly with corresponding changes to MRC warpper.\nCQ-DEPEND\u003dCL:*146175\n\nChange-Id: I021cecb886a9c0622005edc389136d22905d4520\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/172150\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "286cede01befd4bbb67af3d476b22aa1264b6474",
      "tree": "2722cb4ab04f5adec3d99e444de4272a08b16d98",
      "parents": [
        "b02ed95bddbf19db04f6d223dbf39d5385d75c5e"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 15:23:31 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 08 16:18:23 2013 +0000"
      },
      "message": "baytrail: add punit access functions\n\nLike the bunit and dunit, add the punit accessor functions.\n\nBUG\u003dchrome-os-partner:23085\nBRANCH\u003dNone\nTEST\u003dBuilt.\n\nChange-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171931\n"
    },
    {
      "commit": "b02ed95bddbf19db04f6d223dbf39d5385d75c5e",
      "tree": "ae7c88f805ce060ff2d74911963c6bf1a6efa964",
      "parents": [
        "64a827a88305641d9765a1f4a7c1dacf4f687de9"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 15:17:14 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Oct 07 15:15:21 2013 +0000"
      },
      "message": "bayleybay: remove unused graphics.c\n\nThe graphics.c file was never used. Just remove it.\n\nBUG\u003dchrome-os-partner:23121\nBRANCH\u003dNone\nTEST\u003dbuilt.\n\nChange-Id: Ia6bc6251c76074dd73357564d22480122b6a3bb8\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171930\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "64a827a88305641d9765a1f4a7c1dacf4f687de9",
      "tree": "8b7329e996718c0d6becdfbc8a1d32bf47dbdbe6",
      "parents": [
        "a330fddb62cb6346ad66ceb5b5c32b66aecd81e2"
      ],
      "author": {
        "name": "Shawn Nematbakhsh",
        "email": "shawnn@chromium.org",
        "time": "Fri Oct 04 11:47:21 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Oct 07 04:02:10 2013 +0000"
      },
      "message": "baytrail: Change default GPIO configs to closer match power-on defaults\n\n- Set config0 defaults for hysteresis disable, pad bypass, etc.\n- Set config1 power-on defaults.\n- Set pad_val for input as default.\n\nBUG\u003dchrome-os-partner:22863\nTEST\u003dManual. Enable GPIO_DEBUG and verify pad registers are set\naccording to expectation. Also verify bayleybay still boots to payload\nloading.\n\nChange-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420\nReviewed-on: https://chromium-review.googlesource.com/171903\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\nTested-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "a330fddb62cb6346ad66ceb5b5c32b66aecd81e2",
      "tree": "afb9a7e67131c25d79280a5e0cae083426215e56",
      "parents": [
        "63a0c80ce5a19410d0608fede5a9fe0ec1c8e5c1"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Fri Oct 04 11:54:54 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 21:00:22 2013 +0000"
      },
      "message": "samus: Add ACPI MADT interrupt override for GPIO IRQ 14\n\nThis interrupt needs to be specified in the MADT before it can\nbe used by the kernel driver.\n\nBUG\u003dchrome-os-partner:22996\nBRANCH\u003dsamus\nTEST\u003demerge-samus chromeos-coreboot-samus\n\nThis was also tested on bolt by configuring the touchscreen to use\na shared GPIO interrupt:\n\nlocalhost ~ $ grep atmel_mxt_ts /proc/interrupts\n54:    24    188    93    124    LP-GPIO-demux    atmel_mxt_ts\n\nChange-Id: Ic920a792a203cb06cd4529815680584a21532106\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171902\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "63a0c80ce5a19410d0608fede5a9fe0ec1c8e5c1",
      "tree": "729509cec6b9c4357bc174621178775c524a670e",
      "parents": [
        "0a1385515c62fd1e534b12568df8aaf2170e06f4"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Fri Oct 04 11:54:04 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 21:00:19 2013 +0000"
      },
      "message": "lynxpoint: Add interrupt for GPIO controller in ACPI device\n\nThe GPIO controller uses IRQ14 as an active high level triggered\nsource for GPIOs that are configured to trigger shared interrupt.\n\nBUG\u003dchrome-os-partner:22996\nBRANCH\u003dsamus\nTEST\u003demerge-samus chromeos-coreboot-samus\n\nThis was also tested on bolt by configuring the touchscreen to use\na shared GPIO interrupt:\n\nlocalhost ~ $ grep atmel_mxt_ts /proc/interrupts\n54:    24    188    93    124    LP-GPIO-demux    atmel_mxt_ts\n\nChange-Id: I3765120112bae11407e5b2020399d0d0b8e3cef8\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171901\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "0a1385515c62fd1e534b12568df8aaf2170e06f4",
      "tree": "eccc512d8984644ac0327515b1435231a0c04e74",
      "parents": [
        "f6bceacf587a37825dd55bf79170ec2cf329b26a"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Fri Oct 04 11:49:29 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 21:00:14 2013 +0000"
      },
      "message": "samnus: Change SPD to indicate LPDDR\n\nThere is some magic new SPD SDRAM type 241 to indicate LPDDR.\nI cannot find it specificed in any JEDEC document but it is\nwhat the reference code uses.\n\nBUG\u003dchrome-os-partner:22996\nBRANCH\u003dsamus\nTEST\u003demerge-samus chromeos-coreboot-samus\n\nChange-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171900\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "f6bceacf587a37825dd55bf79170ec2cf329b26a",
      "tree": "e42869254c57358d456032173fec73d9be8b29b0",
      "parents": [
        "53e3bed868953f3da588ec90661d316a6482e27e"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 16:00:07 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 19:12:47 2013 +0000"
      },
      "message": "rambi: add initial rambi mainboard support\n\nThis is just a copy from bayleybay.\n\nBUG\u003dchrome-os-partner:23121\nBRANCH\u003dNone\nTEST\u003dNone\n\nChange-Id: I283415be326e2d92e1e1bf7866954f17a7266edb\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171940\nReviewed-by: Bernie Thompson \u003cbhthompson@chromium.org\u003e\n"
    },
    {
      "commit": "53e3bed868953f3da588ec90661d316a6482e27e",
      "tree": "97f3eee88174bb5a69913db5774f5ec3b9b60770",
      "parents": [
        "e00379f54802066fd3e0685b291cdec289078055"
      ],
      "author": {
        "name": "Ronald G. Minnich",
        "email": "rminnich@google.com",
        "time": "Thu Oct 03 17:05:55 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 19:12:43 2013 +0000"
      },
      "message": "Tegra,Tegra124: proposed layout for file hierarchy with example\n\nThis change shows the source structure for nvidia Tegra and Tegra124\nSOC.  The problem we are trying to solve is that there is a large\namount of common code in the form of .c and .h files across many\ndifferent Tegra SOCs. The solution is to provide common code in a\nsingle directory, but not to compile in the common code directory;\nrather, we compile in a directory for a given SOC. Different SOCs\nwill sometimes need different bits of code from the common directory.\n\nTegra common code lives in tegra/, but there is no makefile there: if\na Tegra common file is needed in a SOC, it is referenced via a\nMakefile in a specific Tegra SOC.\n\nAnother issue is includes. Include files in the common directory  might be\naccessed by a piece of code in an SOC directory. More problematically,\ncode in the common directory might require a file in an SOC directory.\nWe don\u0027t want to put the SOC name in an #include path, e.g.\nin a C file in tegra/ is very undesirable, since we might be compiling\nfor a tegra114.\n\nOn some systems this is solved by a pre-pass which creates a set of\nsymbolic links; on others with nested #ifdef in the common code\nwhich include different .h files depending on CPP variables.\nIn previous years, both LinuxBIOS and coreboot have tried these\nsolutions and found them inconvenient and error-prone.\n\nWe choose to solve it by requiring explicit naming of part of the path\nof files that are in the common directory. This requirement, coupled\nwith two -I directives in the Makefile.inc, allows common and SOC\nC code to incorporate both common and SOC .h files.\n\n.c and .h files -- SOC or common -- name include\nfiles in the common directory with the prefix tegra/, e.g.\nSOC files will be included from the SOC directory if they have no prefix:\nThe full patch of clock.h will depend on what SOC is being compiled, which\nis desirable.\n\nIn this way, a common file can pick up a specific SOC file without\ncreating symlinks or other such tricky magic.\n\nWe show this usage with one file, soc/nvidia/tega124/clock.c. This compiles.\n\nThe last question is where to put the prototype for the function\ndefined in this file -- soc.h?\n\nBUG\u003dNone\nTEST\u003dBuilds\nBRANCH\u003dNone\n\nChange-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409\nSigned-off-by: Ronald G. Minnich \u003crminnich@gmail.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171569\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "e00379f54802066fd3e0685b291cdec289078055",
      "tree": "d6211f75e9c91e10f1390e394f7bf455720f6340",
      "parents": [
        "f12424af0e29ac12963e8e5a7970fadcc0bb6cee"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Oct 03 19:18:44 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 19:12:39 2013 +0000"
      },
      "message": "ARMv4: Add a minimal version of cpu.h.\n\nAll this version does is define asmlinkage to be nothing. It\u0027s required by the\nthreading header file which is brought in by the timer implementation which I\nthink is the hook for thread switching.\n\nBUG\u003dNone\nTEST\u003dBuilt with Ron\u0027s patch which adds some clock functions and saw the\ncompile error go away.\nBRANCH\u003dNone\n\nChange-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171801\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "f12424af0e29ac12963e8e5a7970fadcc0bb6cee",
      "tree": "9814fb3d5a95f1ace63995f5b1736b8f4daa0b92",
      "parents": [
        "655a2162e2337fcdf86d40be6fa63b58ffed1fab"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Thu Sep 26 15:13:44 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Oct 05 02:21:04 2013 +0000"
      },
      "message": "libpayload: xhci: Ensure to reset dequeue pointer on stopped endpoints\n\nThis patch fixes a bug in the XHCI stack that occurs when a multi-TRB TD\ntimes out before the last TRB is processed. The driver will correctly\nissue a Stop Endpoint command in that case, but the xHC will still\npreserve the transfer state and just pick up right after that on the\nnext doorbell ring. It will then process the leftover TRBs from the old\nTD the next time a transfer is issued. (cf. XHCI 4.6.9)\n\nWe fix this by changing the existing xhci_reset_endpoint() calls in\ntransfer functions to not only trigger on Halted (2) and Error (4), but\nalso on Stopped (3). That function will not actually issue a Reset\nEndpoint command in this case, but it will nuke the whole transfer ring\nand issue a Set TR Dequeue Pointer command, which is sufficient (though\nslightly overkill) to solve our problem.\n\nBUG\u003dchrome-os-partner:21969\nTEST\u003dManual\n\nChange-Id: I3abbe30ff9d4911a8af1f792324e018d427019e8\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170833\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nReviewed-by: Kees Cook \u003ckeescook@chromium.org\u003e\n"
    },
    {
      "commit": "655a2162e2337fcdf86d40be6fa63b58ffed1fab",
      "tree": "e5e8e64448f00e0faff1914f151754b9707c7112",
      "parents": [
        "758a50a03d81d7112bc20f3696af20fe6174880c"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 11:17:45 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 04 21:40:38 2013 +0000"
      },
      "message": "baytrail: initialize punit\n\nThe punit is responsible for a number of things. Without\nperforming the sequence included it won\u0027t change processor\nfrequency when requested and apparently there are some bizarre\nhangs introduced if this sequence isn\u0027t included either. Lastly,\nthis needs to come after microcode has been loaded. As that is\ndone in bootblock the ordering is correct.\n\nOne other side effect is that this fixes the graphics devices\u0027\ndevice id. Before it was showing up as the same device id of the\nSoC transaction router.\n\nBUG\u003dchrome-os-partner:22880\nBUG\u003dchrome-os-partner:23085\nBUG\u003dchrome-os-partner:22876\nBRANCH\u003dNone\nTEST\u003dBuilt and booted.\n\nChange-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171862\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "758a50a03d81d7112bc20f3696af20fe6174880c",
      "tree": "62ccf4c7e4dd1b21e15bb4e74b8ed4d7e864a041",
      "parents": [
        "59478aee63975573a3e6084103ce2fdbe441660e"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 11:15:48 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 04 21:40:34 2013 +0000"
      },
      "message": "baytrail: load microcode in bootblock\n\nStart loading microcode in the bootblock. This way\nno caching has been set up and cache-as-ram mode\nwill be running in a validated configruation (with ucode\npatch).\n\nBUG\u003dchrome-os-partner:22858\nBRANCH\u003dNone\nTEST\u003dBuilt and booted. Confirmed microcode is loaded.\n\nChange-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171861\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "59478aee63975573a3e6084103ce2fdbe441660e",
      "tree": "3c27b90d298c2fb81ba9af4dd5e1c58a898b2e13",
      "parents": [
        "9671472263ddd0c30400ae3b6da780a18cd21ded"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Oct 04 11:11:52 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 04 21:40:30 2013 +0000"
      },
      "message": "baytrail: disable tco timer\n\nThe TCO timer always starts ticking out of reset.\nHowever, depending on microcode loading and punit\ninitialization the TCO timing out has a different\nimpact on the sytem. Without loading microcode\nor initializing the punit the tco times out and\nnothing happens. However, when microcode is loaded\na timeout will reset the system. Lastly, if the\npunit is initialized but the microcode isn\u0027t loaded\nthe TCO timeout will shut down the system.\n\nTo fix all the weird symptoms disable the TCO.\n\nBUG\u003dchrome-os-partner:22858\nBRANCH\u003dNone\nTEST\u003dBuilt and booted with microcode loading. Reset doesn\u0027t\n     occur.\n\nChange-Id: I49cd62f510726a96bf734ae728a352c671d1561e\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171860\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "9671472263ddd0c30400ae3b6da780a18cd21ded",
      "tree": "f62fdaced23de5b80c73af0602436c934756df93",
      "parents": [
        "f160d4439c0d7cea1d2e6b97207935d61dcbb2f2"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Wed Sep 25 12:30:07 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 04 18:46:36 2013 +0000"
      },
      "message": "libpayload: usb: Fix several minor USB stack bugs\n\nThis patch fixes the following minor bugs in the USB stack:\n\n1. Ensure that all dynamically allocated device structures are cleaned\non detachment, and that the device address is correctly released again.\n2. Make sure MSC and HID drivers notice missing endpoints and actually\ndetach the device in that case (to prevent it from being used).\n3. Make sure XHCI-specific set_address() cleans up all data structures\non failure.\n4. Fix broken Slot ID range check that prevented XHCI devices from being\ncorrectly cleaned up.\n\nBUG\u003dchrome-os-partner:22139\nTEST\u003dManual\n\nChange-Id: I7b2b9c8cd6c5e93cb19abcf01425bcd85d2e1f22\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170665\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nCommit-Queue: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Ronald Minnich \u003crminnich@chromium.org\u003e\n"
    },
    {
      "commit": "f160d4439c0d7cea1d2e6b97207935d61dcbb2f2",
      "tree": "c9501961ef7455df4b96d4b91e6c46017c22aed1",
      "parents": [
        "904eac5930bd705422886bc471a6ff5d7316b2a5"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Tue Sep 24 20:03:54 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Oct 04 18:46:30 2013 +0000"
      },
      "message": "libpayload: usb: Unify USB speed between XHCI stack and USB core\n\nThis patch removes the confusing concept of a special \"xhci_speed\" with\na different numeric value from the usual speed used throughout the USB\ncore (except for the places directly interacting with the xHC, which are\nexplicitly marked). It also moves the MPS0 decoding function into the\ncore and moves some definitions around in preparation of later changes\nthat will make the stack SuperSpeed-ready. It makes both set_address\nimplementations share a constant for the specification-defined\nSetAddress() recovery delay and removes pointless additional delays from\nthe non-XHCI version.\n\nBUG\u003dchrome-os-partner:22139\nTEST\u003dManual\n\nChange-Id: I422379d05d4a502b12dae183504e5231add5466a\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170664\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nCommit-Queue: Ronald Minnich \u003crminnich@chromium.org\u003e\n"
    },
    {
      "commit": "904eac5930bd705422886bc471a6ff5d7316b2a5",
      "tree": "582acda4802c6903fbe09d52ac07dabc4a178dd2",
      "parents": [
        "145f5aa92f5ea01a29fa664825334cb3babeb958"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Thu Oct 03 12:56:37 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 03 22:58:36 2013 +0000"
      },
      "message": "baytrail: program PUNIT memory-mapped base address\n\nApparently there was another BAR living at 0x5c in the LPC\nbridge that mapped the PUNIT registers. EDS 2.0 released\nand this register is now documented.\n\nBUG\u003dchrome-os-partner:23085\nBRANCH\u003dNone\nTEST\u003dBuilt and booted.\n\nChange-Id: I5892c2a14923b57826060e92b4335cb1952ea057\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171612\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "145f5aa92f5ea01a29fa664825334cb3babeb958",
      "tree": "504d3566afb3b72d1a84f55e1699a0bda400509d",
      "parents": [
        "83d99def2d4c729b02aba327a3e491fc1da320da"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Thu Oct 03 09:01:45 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 03 22:58:33 2013 +0000"
      },
      "message": "baytrail: add 316 microcode\n\nThe 316 microcode is the newest version. Include that in the build.\n\nBUG\u003dchrome-os-partner:22858\nBRANCH\u003dNone\nTEST\u003dBuilt and partially booted with microcode loading. Noted 316\n     loaded.\n\nChange-Id: Iba01dd58688737ae38bc58a84014ee9526540db1\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171611\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "83d99def2d4c729b02aba327a3e491fc1da320da",
      "tree": "b5b99ef5ffd3813e2a5c2302276fa56e2eb66cee",
      "parents": [
        "249a74c628264e3d4ce754803ede31238404b4d5"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Thu Oct 03 08:57:17 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 03 22:58:29 2013 +0000"
      },
      "message": "baytrail: additional iosf changes\n\nAllow for one to write an individual byte of a 32-bit register\nwhen sending a read/write through the IOSF messaging system.\nAdd PUNIT registers and fields for early sequencing.\n\nBUG\u003dchrome-os-partner:23085\nBRANCH\u003dNone\nTEST\u003dBuilt and partially booted with changes that use PUNIT\n     registers and individual byte en fields.\n\nChange-Id: I929fb5c51d805c55c478cab884e3572254987fc7\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171710\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "249a74c628264e3d4ce754803ede31238404b4d5",
      "tree": "273940b4054efb0795251376accbdefbd585034c",
      "parents": [
        "b02fa777aa5935021b2c69f7345dffd111cbd118"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Oct 02 16:10:54 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 03 22:57:37 2013 +0000"
      },
      "message": "samus: Add coreboot board\n\nAdd the coreboot board files for samus\n- Based on Bolt\n- GPIO setup based on 0.91 schematic\n- Support both memory types\n- No HDA verb table for this platform\n- Some GPIO interrupts are shared and need to be passed to OS\n\nBUG\u003dchrome-os-partner:22996\nBRANCH\u003dsamus\nTEST\u003demerge-samus chromeos-coreboot-samus\n\nChange-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171694\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "b02fa777aa5935021b2c69f7345dffd111cbd118",
      "tree": "d37405da256ce80fd9c70ecbc4ed6df378295d8e",
      "parents": [
        "5d45fc4ae134702262b6faf8f0666f13494a4fe3"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Oct 02 14:43:58 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Oct 03 22:57:34 2013 +0000"
      },
      "message": "falco: Add support for Samsung memory\n\nNew SPD and update to the SPD map.  Add both a 4GB and 2GB option.\n\n4GB \u003d RAM_ID{1,1,0}\n2GB \u003d RAM_ID{1,1,1}\n\nBUG\u003dchrome-os-partner:22995\nBRANCH\u003dfalco\nTEST\u003demerge-falco chromeos-coreboot-falco\n\nOriginal-Change-Id: I37318c1b5a6ee84b7c55da00d326f10fe8af6f1e\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n(cherry picked from commit 7eb5a4ef1062a34e883c3f356ab0dc00ba07910d)\n\nChange-Id: I0f35a7f5191fefeb5910a2d28aea153516d9a11d\nReviewed-on: https://chromium-review.googlesource.com/171693\nTested-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    },
    {
      "commit": "5d45fc4ae134702262b6faf8f0666f13494a4fe3",
      "tree": "57335e88d396596546528c35bb323c7c44c0a324",
      "parents": [
        "bcd81f1fdfd17940aadb36696d3cb81909d7b51f"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Wed Oct 02 11:06:31 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 18:31:17 2013 +0000"
      },
      "message": "baytrail: import and use updated mrc_wrapper.h\n\nThe mrc_wrapper.h was changed to protect against ABI differences\nbetween the two sets of compilers and flags used. This requires\na prope shim for the console output funciton.\n\nBUG\u003dchrome-os-partner:23048\nBRANCH\u003dNone\nTEST\u003dBuilt and booted successfully.\n\nChange-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171580\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "bcd81f1fdfd17940aadb36696d3cb81909d7b51f",
      "tree": "c627f601cad9283134b0a5d7faa1b1e6533c8dfb",
      "parents": [
        "c1aa76b7607ee40ff848628971a97eea5393aebe"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 01 05:29:03 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:19:02 2013 +0000"
      },
      "message": "ARM: Remove the hack which excluded assembly barriers for tegra124 bootblock.\n\nNow that the tegra124 bootblock is compiled using ARMv4 code, this hack is no\nlonger necessary.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt and booted into the bootblock on nyan. Built for link, snow, falco,\nand pit.\nBRANCH\u003dNone\n\nChange-Id: I5b7fe5e45e15f878089542a04bd20d6c607b0f69\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171403\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "c1aa76b7607ee40ff848628971a97eea5393aebe",
      "tree": "552cbeda51380bc710a409fdad79736955ec3195",
      "parents": [
        "221dc76b3ce4c1d73851c432333e091e1c60f0cb"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 01 05:24:47 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:58 2013 +0000"
      },
      "message": "tegra124: Switch the bootblock over the ARMv4 impelementation.\n\nThe bootblock for the tegra124 runs on the AVP coprocessor which uses the\nARMv4 architecture. Switch it over to that architecture.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt and booted into the bootblock on nyan. Built for link, snow, pit,\nand falco.\nBRANCH\u003dNone\n\nChange-Id: Ie527bbff938e6148c58727d448f9c2e6862da872\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171402\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "221dc76b3ce4c1d73851c432333e091e1c60f0cb",
      "tree": "4cc18a675ce3572c13b3b23e195a6da1537bfd8d",
      "parents": [
        "799514e6060aa97acdcf081b5c48f965be134483"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 01 05:20:17 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:55 2013 +0000"
      },
      "message": "ARM: Add an ARMv4 architecture version.\n\nThis is needed for the tegra124\u0027s bootblock and includes enough implementation\nto support that use. No caching is supported, although there are function\nprototypes and stub implementations to satisfy includes and linking.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt and booted into the bootblock on nyan. Built for link, falco, pit\nand snow.\nBRANCH\u003dNone\n\nChange-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171401\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "799514e6060aa97acdcf081b5c48f965be134483",
      "tree": "5df149a3eb51c09904a804adc5498115a0526ada",
      "parents": [
        "f0a2670862ae589c6a2745fa618a2a70f40e5397"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 01 04:47:53 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:51 2013 +0000"
      },
      "message": "ARM: Split out ARMv7 code and make it possible to have other arch versions.\n\nWe don\u0027t always want to use ARMv7 code when building for ARM, so we should\nseparate out the ARMv7 code so it can be excluded, and also make it possible\nto include code for some other version of the architecture instead, all per\nbuild component for cases where we need more than one architecture version\nat a time.\n\nThe tegra124 bootblock will ultimately need to be ARMv4, but until we have\nsome ARMv4 code to switch over to we can leave it set to ARMv7.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt for link, falco, pit, snow, and nyan. Built into the bootblock on\nnyan.\n\nChange-Id: Ia982c91057fac9c252397b7c866224f103761cc7\nReviewed-on: https://chromium-review.googlesource.com/171400\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "f0a2670862ae589c6a2745fa618a2a70f40e5397",
      "tree": "1cfcae67bae20b5013a7134cb462b39e9fabb9ae",
      "parents": [
        "8423a41529da0ff67fb9873be1e2beb30b09ae2d"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Oct 01 04:26:08 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:48 2013 +0000"
      },
      "message": "Makefile: Include ccopts variables in the static.c Make rules.\n\nThere are special rules which build the static.c files because they come from\n$(obj) and not $(src) like most source files, and its apparently the most\nstraightforward way to fold them into the build. Those special copies of the\nrules didn\u0027t have the $(class)-c-ccopts variables in them, though, so that\none file for each class would be compiled with different flags. This change\nadds that variable in so the special version of the rules match the normal\nversion.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt for pit, snow, nyan, link, and falco.\nBRANCH\u003dNone\n\nChange-Id: Ie637118d433a0a43a6a9d2c8b9ecb92155044546\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171339\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "8423a41529da0ff67fb9873be1e2beb30b09ae2d",
      "tree": "a1051c6470903bceb111ba5c0acb8dfdcb58310b",
      "parents": [
        "86f5e2875b18901b349283cfbcd4f8cc88b7a019"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 23:00:33 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:44 2013 +0000"
      },
      "message": "ARM: Generalize armv7 as arm.\n\nThere are ARM systems which are essentially heterogeneous multicores where\nsome cores implement a different ARM architecture version than other cores. A\nspecific example is the tegra124 which boots on an ARMv4 coprocessor while\nmost code, including most of the firmware, runs on the main ARMv7 core. To\nsupport SOCs like this, the plan is to generalize the ARM architecture so that\nall versions are available, and an SOC/CPU can then select what architecture\nvariant should be used for each component of the firmware; bootblock,\nromstage, and ramstage.\n\nBUG\u003dchrome-os-partner:23009\nTEST\u003dBuilt libpayload and coreboot for link, pit and nyan. Booted into the\nbootblock on nyan.\nBRANCH\u003dNone\n\nChange-Id: I22e048c3bc72bd56371e14200942e436c1e312c2\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171338\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "86f5e2875b18901b349283cfbcd4f8cc88b7a019",
      "tree": "3efae527dca4bee12945157680146948492641da",
      "parents": [
        "a93900be8d8a8260db49e30737608f9161fbf249"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 21:28:30 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:41 2013 +0000"
      },
      "message": "tegra124: Implement and enable serial console support for tegra124.\n\nThe driver is very similar to the 8250 driver, except it isn\u0027t in two parts,\nand it also spaces its registers 4 bytes apart instead of having them directly\nadjacent to each other.\n\nAlso, eliminate the UART test function in the bootblock. It\u0027s no longer needed\nsince the actual console output serves the same purpose.\n\nRight now the clock divisor is fixed for now, and we\u0027ll want to actually\nfigure out what value to use at some point.\n\nBUG\u003dNone\nTEST\u003dBuilt for link, pit, nyan and lumpy. Booted into the bootblock on nyan\nand saw serial output on the console.\nBRANCH\u003dNone\n\nChange-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171337\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "a93900be8d8a8260db49e30737608f9161fbf249",
      "tree": "ab28fd065ae2f4c1baddcb546c218b63b8a2b4d3",
      "parents": [
        "d3045f393285c3d3a6bc5104c181fe811b2fc357"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 21:25:49 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:38 2013 +0000"
      },
      "message": "UART 8250: Unconditionally provide register constants and use UART8250 prefix.\n\nThe register indexes and bitfield masks were guarded by the UART8250 config\noptions, but it might be (is) necessary to use them in a driver that is\nUART8250 like without actually using the 8250 driver itself. To avoid any name\ncollision with other drivers, also change the constant prefix from UART_ to\nUART8250_.\n\nBUG\u003dNone\nTEST\u003dBuilt for link, lumpy, pit, and nyan. With this and other changes, got\nbootblock serial output on nyan.\nBRANCH\u003dNone\n\nChange-Id: Ie606d9e0329132961c3004688176204a829569dc\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171336\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "d3045f393285c3d3a6bc5104c181fe811b2fc357",
      "tree": "4a5a494fceedc8c13f588b19c77bb8065471de9d",
      "parents": [
        "ae7d4d890be1936cc86dc15adeb33f3b46a51ae5"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 21:23:34 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:34 2013 +0000"
      },
      "message": "uart: The uart.h header file uses uint32_t without including stdint.h.\n\nMake it include stdint.h instead of relying on that file having already been\nincluded by something else.\n\nBUG\u003dNone\nTEST\u003dBuilt for link, lumpy, nyan, pit.\nBRANCH\u003dNone\n\nChange-Id: Ia09abc890a5f6b12318aa4ae0897aa8a0baf3b13\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171335\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "ae7d4d890be1936cc86dc15adeb33f3b46a51ae5",
      "tree": "647b3df070491eadc06971cbe9b6fe243d807dd6",
      "parents": [
        "049f95cfcb43185c39dddfdad9bd541fb8a18c6b"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 18:43:18 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Oct 02 09:18:21 2013 +0000"
      },
      "message": "tegra124: Seperate out the non-UART specific hardcoded init in the bootblock.\n\nThe hardcoded init in the test function in the bootblock is actually useful\ngenerally because it doesn\u0027t belong in the UART driver itself but is necessary\nfor the UART to work. Until we have real implementations for the pinmux, etc.,\nwe can use that code to get the UART and console going.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted into the bootblock on nyan with and without the test\nfunction enabled. When it was, saw the \"!\"s on the console.\nBRANCH\u003dNone\n\nChange-Id: I2efe0b571d8b022eb2a2e5569620558540b28373\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171334\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "049f95cfcb43185c39dddfdad9bd541fb8a18c6b",
      "tree": "1eee50d610739c1418fbf4056af3026fbde52472",
      "parents": [
        "d5a429498147c479eb51477927e146de809effce"
      ],
      "author": {
        "name": "Vadim Bendebury",
        "email": "vbendeb@chromium.org",
        "time": "Fri Sep 27 16:21:04 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 20:25:20 2013 +0000"
      },
      "message": "Rearrange baitrail config options alphanumerically\n\nThis is a no-op change for easier maintenance.\n\nBUG\u003dnone\nTEST\u003dmanual\n    . baitrail coreboot still builds and runs\n\nChange-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee\nSigned-off-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/171002\n"
    },
    {
      "commit": "d5a429498147c479eb51477927e146de809effce",
      "tree": "b797e1ee8b72b5d178165089298f6a862ebada72",
      "parents": [
        "c8bb8fe0b20be37465f93c738d80e7e43033670a"
      ],
      "author": {
        "name": "Ronald G. Minnich",
        "email": "rminnich@google.com",
        "time": "Mon Sep 30 15:57:21 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 17:56:28 2013 +0000"
      },
      "message": "PEPPY, Haswell: refactor and create set_translation_table function in haswell/gma.c\n\nThe code to set the graphics translation table has been in the\nmainboards,but should be in the northbridge support code.\n\nMove the function, give it a better name, and enable support for \u003e 4\nGiB while we\u0027re at it, in the remote possibility that we get some 8\nGiB haswell boards.\n\nBUG\u003dNone\nTEST\u003dbuild and boot peppy in dev mode and see that graphics still works. Build falco to make sure we did not break that build.\nBRANCH\u003dNone\n\nChange-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130\nSigned-off-by: Ronald G. Minnich \u003crminnich@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171160\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-by: Furquan Shaikh \u003cfurquan.m.shaikh@gmail.com\u003e\nCommit-Queue: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Ronald Minnich \u003crminnich@chromium.org\u003e\n"
    },
    {
      "commit": "c8bb8fe0b20be37465f93c738d80e7e43033670a",
      "tree": "c86e591823eb85fa826122672c969e45dc706532",
      "parents": [
        "2a0adceb5029c8ee633d17c82dbb11e48d30349d"
      ],
      "author": {
        "name": "Hung-Te Lin",
        "email": "hungte@chromium.org",
        "time": "Fri Sep 27 12:45:45 2013 +0800"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 08:16:46 2013 +0000"
      },
      "message": "armv7: Move Exynos from \u0027cpu\u0027 to \u0027soc\u0027.\n\nThe Exynos family and most ARM products are SoC, not just CPU.\n\nWe used to put ARM code in src/cpu to avoid polluting the code base for what was\nessentially an experiment at the time. Now that it\u0027s past the experimental phase\nand we\u0027re going to see more SoCs (including intel/baytrail) in coreboot.\n\nBUG\u003dnone\nTEST\u003demerge-daisy chromeos-coreboot-snow;\n     emerge-peach_pit chromeos-coreboot-peach_pit\n\nChange-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c\nReviewed-on: https://chromium-review.googlesource.com/170891\nTested-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Hung-Te Lin \u003chungte@chromium.org\u003e\n"
    },
    {
      "commit": "2a0adceb5029c8ee633d17c82dbb11e48d30349d",
      "tree": "95e39165ea03311a936acebdbc2e2a5e5b13f4e0",
      "parents": [
        "65f1aa116b0f7d4fa7af24cfe1c441f8fd16c6d3"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 05:08:23 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 08:16:15 2013 +0000"
      },
      "message": "tegra124: Re-enable waiting for the transmitter to empty in the test function.\n\nThe compiler was emitting code compatible with armv7-a, but the bootblock was\nrunning on a core which uses armv4t. By coincidence, it was emitting an\ninstruction which is unavailable on armv4t when checking the value of the\nUART\u0027s LSR register. Now that the bootblock is compiled with more appropriate\nflags, this code can be re-introduced.\n\nBUG\u003dNone\nTEST\u003dBuilt into the bootblock on nyan and, with the test function enabled, saw\na stream of \"!\"s on the console.\nBRANCH\u003dNone\n\nChange-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170997\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "65f1aa116b0f7d4fa7af24cfe1c441f8fd16c6d3",
      "tree": "a0ed79368e29591dd65c89ceef23d5af721919c6",
      "parents": [
        "f7255d8c5543b7e98a7f83ad1ebb604a8948928b"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 05:02:45 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 08:16:10 2013 +0000"
      },
      "message": "tegra124: Override the -march flag used by the bootblock.\n\nThe bootblock on the tegra124 runs on the AVP which is uses the armv4t\narchitecture version.\n\nBUG\u003dNone\nTEST\u003dWith this option set, saw that the compiler no longer emitted\ninstructions which don\u0027t work on the AVP.\nBRANCH\u003dNone\n\nChange-Id: Ic9c8b34a353e291a02a714d18de0d01f1e3ab4d1\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170996\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "f7255d8c5543b7e98a7f83ad1ebb604a8948928b",
      "tree": "a311554b0c5b5b3b6fc4a603e881d77e1a32f877",
      "parents": [
        "e0059181958cfe8afec2f3a7ea732e81f5d55e5d"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Mon Sep 30 15:19:11 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Oct 01 08:16:06 2013 +0000"
      },
      "message": "ARM: Hack out assembly barriers when on tegra124.\n\nThe tegra124 AVP uses ARMv4 which doesn\u0027t support the barrier assembly\ninstructions. Unfortunately we assume that we can (and should) use those\nduring the bootblock and things don\u0027t build. In place of a more robust long\nterm solution, we can just chop those out on boards with the tegra124. This\nis only supposed to be a short term, stop gap solution.\n\nBUG\u003dNone\nTEST\u003dBuilt for pit, nyan. Booted into the bootblock on nyan.\nBRANCH\u003dNone\n\nChange-Id: Ifd0bfd3f7e30df6b5bcb1222c070922b81136b03\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171151\nReviewed-by: Julius Werner \u003cjwerner@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "e0059181958cfe8afec2f3a7ea732e81f5d55e5d",
      "tree": "dfc2accab248ed2a556e4969abd2309eb74db61d",
      "parents": [
        "d1436288d3b025af27a8d28ba94b589940ead504"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Sep 29 07:06:08 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:45 2013 +0000"
      },
      "message": "tegra124: Add a test function which spams exclamation points on the UART.\n\nThis function spews characters on the console and, until we have a working\nconsole, is an easy way to see whether the system boots to a particular point.\nFor some reason waiting for transmitter to be empty hangs, but transmitting\ncharacters still works.\n\nBUG\u003dNone\nTEST\u003dEnabled the function and saw the UART output.\nBRANCH\u003dNone\n\nChange-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171030\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "d1436288d3b025af27a8d28ba94b589940ead504",
      "tree": "bc9736f96b33a01366d84a455c23912da7296898",
      "parents": [
        "a66393fdd6fe68757e394b8a611e610f1938771d"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Sep 29 06:32:27 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:43 2013 +0000"
      },
      "message": "tegra124: Add a custom bootblock implementation.\n\nThis implementation is the same as the general one except that it removes all\nthe things that don\u0027t work on an ARMv4.\n\nBUG\u003dNone\nTEST\u003dBuilt for Nyan. With this and other changes, built and booted on Nyan and\nverified that it was getting into the bootblock.\nBRANCH\u003dNone\n\nChange-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171019\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "a66393fdd6fe68757e394b8a611e610f1938771d",
      "tree": "9c051231f2d53d8304cbb1e004bb6b7cd990f0b3",
      "parents": [
        "512d942788336c8d52470135b43ee4e6a1c95f6c"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Sep 29 05:40:13 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:40 2013 +0000"
      },
      "message": "ARM: Make it possible to use a custom bootblock implementation.\n\nTegra needs to use a custom bootblock implementation because it starts on a\ncoprocessor which uses ARMv4. It doesn\u0027t have the same control registers,\ncaches, etc., and the regular bootblock gets exceptions and dies.\n\nBUG\u003dNone\nTEST\u003dBuilt for pit. With this and other changes, built and booted on nyan and\nverified that it got into the bootblock.\nBRANCH\u003dNone\n\nChange-Id: Id197db2939bc840ad64244d6e2017fc5c89e0cbd\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171018\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "512d942788336c8d52470135b43ee4e6a1c95f6c",
      "tree": "cb052bb1623b6cff3cdabf9ed4bd74d210d9f42d",
      "parents": [
        "d606f227983d8fb76e1cc754ca52d0d00036e911"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Sep 29 03:02:55 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:36 2013 +0000"
      },
      "message": "ARM: Overhaul the ARM Makefile.\n\nThe ARM Makefile was copied from x86 and then modified, and as a result it\nwas carrying a lot of baggage. On top of that, the extra complication made it\ninflexible, and we need a lot of flexiblity in order to support the fact that\nthe Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main\nCPUs.\n\nBUG\u003dNone\nTEST\u003dBuilt and booted on pit. With this and other changes, built and booted\ninto the bootblock on nyan.\nBRANCH\u003dNone\n\nChange-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171017\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "d606f227983d8fb76e1cc754ca52d0d00036e911",
      "tree": "3466ca85e8eb52c5b2d5da9270596e3ede76e1b5",
      "parents": [
        "3e69a477474697bcbc40762ec166e8a515d8b0c2"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sat Sep 28 21:31:01 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:34 2013 +0000"
      },
      "message": "Makefile: Put the class flags after the generic flags.\n\nThe class flags are more specific than the generic CFLAGS flags and should be\nafter them so that they have a chance to override them. The class specific\nflags weren\u0027t really used on anything but ARM so this should be a fairly safe\nchange even in the x86 Makefiles.\n\nBUG\u003dNone\nTEST\u003dBuilt for link. Built and booted on nyan.\nBRANCH\u003dNone\n\nChange-Id: I7a949efbb1d2841f9f0d28433772092d9f95db36\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171016\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "3e69a477474697bcbc40762ec166e8a515d8b0c2",
      "tree": "53988412174fff3f5b8c924e56ce692aaf561ade",
      "parents": [
        "154876c126a6690930141df178485658533096d2"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sat Sep 28 20:39:21 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:31 2013 +0000"
      },
      "message": "tegra124: Add stack related config options to the Kconfig.\n\nOtherwise the stack ends up down at 0 and has 0 bytes.\n\nBUG\u003dNone\nTEST\u003dBuilt for nyan with this and other changes and saw that the stack was set\nup properly and that C code could run.\nBRANCH\u003dNone\n\nChange-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171015\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "154876c126a6690930141df178485658533096d2",
      "tree": "738618bae9cbb83fda7c3208a8605fe9fab2fc51",
      "parents": [
        "cf4a9b0712c21b885bb59310671fb87e38abb665"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Sun Sep 29 03:16:41 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:28 2013 +0000"
      },
      "message": "snow: Fix a typo in devicetree.cb that was breaking the snow build.\n\nA typo in a recent change broke the snow build.\n\nBUG\u003dNone\nTEST\u003dBuilt successfully for snow.\nBRANCH\u003dNone\n\nChange-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/171014\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "cf4a9b0712c21b885bb59310671fb87e38abb665",
      "tree": "6efa515c5c47f940e90dc041ce0f768b91371114",
      "parents": [
        "6bbcffe04e8ae73c86bc05c577a67f909857e1c0"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Fri Sep 27 03:06:34 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:24 2013 +0000"
      },
      "message": "tegra124: Add some make rules which will wrap the bootblock in the BCT.\n\nThese rules slip into the normal bootblock preperation process and use the\ncbootimage utility to wrap it in a BCT.\n\nBUG\u003dNone\nTEST\u003dBuilt for nyan and saw that the new rules were run, and that the BCT\nwhich resulted had reasonable looking contents.\nBRANCH\u003dNone\n\nChange-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170924\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "6bbcffe04e8ae73c86bc05c577a67f909857e1c0",
      "tree": "5fb4c9a3397ab862ec563615a60a33b90767b3cd",
      "parents": [
        "3ae44178b7084037a75e16ce161b1432abf4246a"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Fri Sep 27 02:45:50 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:21 2013 +0000"
      },
      "message": "nyan: Add bct files for nyan.\n\nThere\u0027s a config option which selects between the emmc and spi config files\ndepending on what the firmware is intended to boot from. These are copied from\nthe files installed by the tegra-bct-nyan ebuild, except that the spi config\nfile has been modified so that there\u0027s only one copy of the BCT and so that it\nonly has one configuration. This is to save space in the final image.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built an image for nyan and saw that the bct\nexactly matched what was installed by the tegra-bct-nyan ebuild.\nBRANCH\u003dNone\n\nChange-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170923\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "3ae44178b7084037a75e16ce161b1432abf4246a",
      "tree": "d5722141950d86aacffe2d6c9e1ce3a413b0a813",
      "parents": [
        "8db03c387ad654227d064e2a7fa5ecf09d07e3c5"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Fri Sep 27 02:35:12 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Mon Sep 30 06:57:17 2013 +0000"
      },
      "message": "nyan: Add a \"special-class\" for aggregating BCT files into bct.cfg.\n\nThe config file which cbootimage processes to create a BCT could come from\nmultiple different files, individually selected based on config options,\nand/or split up into different files for organizational purposes. This change\nadds a special-class which collects those files and concatenates them all\ntogether in a bct.cfg which can be processed more easily by other parts of the\nbuild.\n\nWhile the BCT files themselves are potentially very board specific, for\ninstance ones that hold memory timing information, this bit of code which\ncollects them is not. It has to be in each board file instead of alongside the\nCPU, however, to ensure that the special class is set up before another\nMakefile tries to use it. If we end up with lots of Tegra based boards which\nduplicate this code over and over, we might want to revisit how this works.\n\nBUG\u003dNone\nTEST\u003dBuilt for nyan while forcing the bct.cfg rule to be executed. Verified\nthat the bct.cfg was created successfully. With other changes, used the\nbct.cfg in an image.\nBRANCH\u003dNone\n\nChange-Id: I58e1373434f89e69298990ea4643a19d8afdc309\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170922\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "8db03c387ad654227d064e2a7fa5ecf09d07e3c5",
      "tree": "91997ef01f7367b3e7ea66a55288c820891b0581",
      "parents": [
        "c197ccfc2502efd650d7b2ffb3fa5e446bce97c3"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 23:21:57 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sun Sep 29 03:43:02 2013 +0000"
      },
      "message": "arm: Get rid of the INTERMEDIATE variable used on exynos.\n\nThe INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for\nExynos SOCs, but we can do that directly without having a special hook.\n\nBUG\u003dNone\nTEST\u003dBuilt for pit and snow and verified that the BL1 was still copied into\nthe image as expected.\nBRANCH\u003dNone\n\nChange-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170921\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "c197ccfc2502efd650d7b2ffb3fa5e446bce97c3",
      "tree": "566dbf066191fd43affd8ec091cdd86be0767f71",
      "parents": [
        "f276df6ec6000c5ffcc1fc51260ce81aa4f94e49"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Fri Sep 27 11:38:36 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Sep 28 04:21:24 2013 +0000"
      },
      "message": "baytrail: start collecting timestamps\n\nThis commit always selects COLLECT_TIMESTAMPS and starts\ntracking TSC values from the early stages of bootblock.\nThe initial timestamp value is saved in mm0 and mm1 while\nin bootlbock. This approach works because romcc is not configured\nto use mmx registers for its compilation.\n\nAdditionally, the romstage api with the mainboard was changed to\nalways pass around a pointer to a romstage_params structure as the\ntimestamps are saved in there until ram is up.\n\nBUG\u003dchrome-os-partner:22873\nBRANCH\u003dNone\nTEST\u003dBuilt and booted with added code to print out timestamps at\n     and of ramstage. Everything looks legit.\n\nChange-Id: Iba8d5fff1654afa6471088c46a357474ba533236\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170950\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "f276df6ec6000c5ffcc1fc51260ce81aa4f94e49",
      "tree": "955d02427713d2dae6253e4edb2d5d72ead7e96a",
      "parents": [
        "77ca452cd645eea614039a1996dc0a9c63e8ddb8"
      ],
      "author": {
        "name": "Shawn Nematbakhsh",
        "email": "shawnn@chromium.org",
        "time": "Thu Sep 26 16:50:56 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Sep 28 03:20:57 2013 +0000"
      },
      "message": "bayleybay: Add initial GPIO configuration table.\n\nConfigure all GPIOs as default (function 0), except for SMBus / UART\nGPIOs.\n\nBUG\u003dchrome-os-partner:22863\nTEST\u003dManual. Using bayleybay GPIO table, set UART GPIOs to \u0027function 1\u0027,\n and verify UART still works after GPIO configuration. Also, verify\nlegacy GPIO config is functional by toggling test pin.\n\nChange-Id: I429e0b161767af296e7ff69ecbfde2c3a1c2e74a\nReviewed-on: https://chromium-review.googlesource.com/170839\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\nTested-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "77ca452cd645eea614039a1996dc0a9c63e8ddb8",
      "tree": "45c762b44d8faa826d946dc67b5658cbae095053",
      "parents": [
        "8cdaf73e3602e15925859866714db4d5ec6c947d"
      ],
      "author": {
        "name": "Shawn Nematbakhsh",
        "email": "shawnn@chromium.org",
        "time": "Thu Sep 26 16:44:14 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Sat Sep 28 03:20:53 2013 +0000"
      },
      "message": "baytrail: Add GPIO initial configuration infrastructure.\n\nDuring ramstage, call mainboard_get_gpios to get initial GPIO configuration\nfrom the mainboard code, then initialize GPIOs as requested.\n\nBUG\u003dchrome-os-partner:22863\nTEST\u003dManual. Using bayleybay GPIO table, set UART GPIOs to \u0027function 1\u0027,\nand verify UART still works after GPIO configuration. Also, verify\nlegacy GPIO config is functional by toggling test pin.\n\nChange-Id: Ic58d8ddd15c4dc48a751a83f6d26c7809c1efc42\nReviewed-on: https://chromium-review.googlesource.com/170306\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nCommit-Queue: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\nTested-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "8cdaf73e3602e15925859866714db4d5ec6c947d",
      "tree": "1c5555b73f81d2b84d983a8a464664aafd63cf0e",
      "parents": [
        "17dc60f31de1245e8d87f2d6e17a68710dd29b00"
      ],
      "author": {
        "name": "Ronald G. Minnich",
        "email": "rminnich@gmail.com",
        "time": "Thu Sep 19 16:45:22 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 23:07:14 2013 +0000"
      },
      "message": "Peppy graphics\n\nPeppy had some issues with FUI. We decided it was time to create\npeppy-specific gma.c and i915io.c files. Using yabel and the i915tool,\nwe generated a replay attack, then interpolated against the slippy\ni915io.c to get something working.\n\nAlso, in preparation for moving code out of the mainboard gma.c to\ngeneric driver code, we got rid of some hardcodes in the mainboard\ngma.c that have no business being there. The worst were the\ncomputation of gmch_[m,n] and it turns out that we had some\nlong-standing bugs related to confusion about \u0027bpp\u0027. I\u0027ve killed the\nword bpp everywhere I could because there are at least 3 things that\ncorrespond to bpp. We now have framebuffer, pipe, and panel bpp. The\nnames are long because I want to avoid all the mistakes we\u0027ve all been\nmaking in the last year :-) Sadly, that means a lot of changes not just\npeppy-related, but they are simple and in a good cause.\n\nThe test pattern generation is driven by a global variable in\nmainboard/peppy/gma.c.  I\u0027ve found in the past that it\u0027s very useful\nto have a function like this available, as one can activate it while\nusing a jtag debugger: halt at the right place in ramstage, set the\nvariable to 1, continue. It\u0027s not enough code to worry about always\nincluding.\n\nThe last hard-codes for M and N registers are gone, and the function\nto set from generic intel_dp.c code works.  To avoid screen trash on a\ndev mode boot, which we liked but nobody else did :-), we now take the\ntime to put a pleasing background color that sort of doubles as a\npower LED.\n\nRough timing is ramstage start is at 2.2, and dev setup is done at\n3.3. These new platforms are depressingly slow to boot. Rom init alone\nis taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash\nprompt. These CPUs are at least 10x faster and take much longer to get going.\n\nFuture work, once we get this through, is to move more functions to the\nintel driver, and combine the mainboard i915io.c into the mainboard gma.c.\nThat separation only existed because i915io.c was generated by a tool, and it\nhad lots of ugliness. Most ugliness is gone.\n\nBUG\u003dNone\nTEST\u003dbuild and boot on peppy and get a screen, in both dev and normal modes.\nBRANCH\u003dNone\n\nChange-Id: I6a6295b423a41e263f82cef33eacb92a14163321\nSigned-off-by: Ronald G. Minnich \u003crminnich@gmail.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170013\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nCommit-Queue: Ronald Minnich \u003crminnich@chromium.org\u003e\nTested-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nReviewed-by: Furquan Shaikh \u003cfurquan.m.shaikh@gmail.com\u003e\n"
    },
    {
      "commit": "17dc60f31de1245e8d87f2d6e17a68710dd29b00",
      "tree": "8fbec30611a545ead037a2a893388470fc28f8e6",
      "parents": [
        "3893c94c21d49c01f18eaf08323821424a78a969"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 16:28:45 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 21:54:04 2013 +0000"
      },
      "message": "nyan: config: Add a coreboot config file for the nyan board.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built for the nyan board.\nBRANCH\u003dNone\n\nChange-Id: Ida74e2a09503076ba42159fd542143c26eaf1508\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170838\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "3893c94c21d49c01f18eaf08323821424a78a969",
      "tree": "7fc83e6f728e5b83f2b858a77865bcd5516e88e5",
      "parents": [
        "e9d87534ccacb42d508f1902786470798a2dbaea"
      ],
      "author": {
        "name": "Vadim Bendebury",
        "email": "vbendeb@chromium.org",
        "time": "Fri Sep 27 09:50:58 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 19:29:01 2013 +0000"
      },
      "message": "Use changed serial port config name for Bayleybay too\n\nAn earlier change modified the serial port configuration option name\nand updated most board configurations, but Bayleybay was left behind.\n\nBUG\u003dNone\nTEST\u003dBaylebay builds smoothly again\n\nChange-Id: I8b779c1fb24820ca5ff95dcd6641ae1df94f7e1b\nSigned-off-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170961\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "e9d87534ccacb42d508f1902786470798a2dbaea",
      "tree": "c44dada00561e17d40ffdcab3dc7ed3e4336fdab",
      "parents": [
        "462456fd00164c10c80eff72240226a04445fe60"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 16:27:55 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 14:06:06 2013 +0000"
      },
      "message": "nyan: Add a stub mainboard.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built for the nyan board.\nBRANCH\u003dNone\n\nChange-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170837\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "462456fd00164c10c80eff72240226a04445fe60",
      "tree": "a65135a2985b16813ecf960841a7c248b1010e07",
      "parents": [
        "7274ba360d51d8ca8278708225661d9291fd3c60"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 16:22:09 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 14:06:02 2013 +0000"
      },
      "message": "tegra124: Add a stub implementation of the tegra124 SOC.\n\nMost things still needs to be filled in, but this will allow us to build\nboards which use this SOC.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built for the nyan board.\nBRANCH\u003dNone\n\nChange-Id: Ic790685a78193ccb223f4d9355bd3db57812af39\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170836\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "7274ba360d51d8ca8278708225661d9291fd3c60",
      "tree": "dd23d8196969548ffcf7dbd78f09286eb76690dc",
      "parents": [
        "9a10e39a2da3cb0bfb316c0869cf5025078e287f"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 16:19:02 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 14:05:57 2013 +0000"
      },
      "message": "libpayload: Add a nyan config.\n\nThis config is based on the pit config but has been tuned somewhat to be\nappropriate for the hardware on the nyan board.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built for the nyan board.\nBRANCH\u003dNone\n\nChange-Id: Ide209a05a311d475151253d45f9315a6c35da565\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170835\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "9a10e39a2da3cb0bfb316c0869cf5025078e287f",
      "tree": "6b3eab42b8b0241ab952899c4a8b58a0f1f70090",
      "parents": [
        "fd4529f37fdd1c93a8b902488ffeef7001b1a05a"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Thu Sep 26 16:13:08 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 14:05:53 2013 +0000"
      },
      "message": "libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE\n\nWhile the 8250 compatible serial port driver is primarily useful on x86\nsystems because it works with the legacy x86 com ports, some devices which\naren\u0027t x86 based have 8250 compatible UARTs as well. This change renames the\nCONFIG_X86_SERIAL_CONSOLE option to the more general and direct\nCONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86\nsystems can enable the driver, although it will default to on on x86 and off\notherwise.\n\nAlso, the default IO port address that\u0027s added to the sysinfo structure on x86\nand which is intended to be overwritten by a value in the coreboot tables is\nnot used on ARM. That variable is adjusted so that it\u0027s more clear it\u0027s a\ndefault value, and made dependent on x86 since that\u0027s the only place its value\nis actually used.\n\nBUG\u003dNone\nTEST\u003dWith this and other changes, built for an ARM board which has an ns16550\n(and essentially 8250) compatible UART. Built for pit and for link.\nBRANCH\u003dNone\n\nChange-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170834\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "fd4529f37fdd1c93a8b902488ffeef7001b1a05a",
      "tree": "74931fbdc3edc87230eb88e16dac8c914106f32b",
      "parents": [
        "71ee403179d4b76b3ad066463c72877e38192ad2"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Wed Sep 25 13:54:57 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Fri Sep 27 01:05:39 2013 +0000"
      },
      "message": "libpayload: usbmsc: Remove DETACHED state from MSC device structure\n\nThe USB MSC device structure contains a \"ready\" state that can be either\n\"ready\", \"not ready\" or \"detached\". The last one can only be assigned\nwhen the device is completely unresponsive and gets forcefully logically\ndetached via usb_detach_device(). This call (at least in the current\nversion) also calls all destructors and frees the complete usbdev_t\nstructure (including the MSC specific part), which unfortunately makes\nstoring the \"detached\" state in that very structure a little pointless.\n\nThis patch reduces the \"ready\" value to a simple boolean and makes sure\nthat all detachment cases immediately return from the MSC driver,\ncarefully avoiding any use-after-free opportunities.\n\nBUG\u003dNone\nTEST\u003dUnplug a USB stick from a Pit/Kirby in depthcharge and make sure\nthe machine doesn\u0027t crash.\n\nChange-Id: Iff1c0849f9ce7c95d399bb9a1a0a94469951194d\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170667\n"
    },
    {
      "commit": "71ee403179d4b76b3ad066463c72877e38192ad2",
      "tree": "a5c0e56132db47d0fb069a09712e5ce9eec1be80",
      "parents": [
        "a487dea6a0a4d369faffda4c25e2fa850a7ddd73"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Sep 24 16:47:49 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Sep 26 22:02:55 2013 +0000"
      },
      "message": "baytrail: introduce pattrs\n\nThe pattrs structure is intended for the supporting coreboot\ncode to reference instead of going back to the source of\nthe values (msrs, cpuid, etc). It essentially serves as a global\nstructure for collecting attributes about the platform/processor.\n\nAdditionally, the implementation provides a point during boot to\nhoook work before device enumeration/initialization by providing\na init() function to soc_intel_baytrail_ops that is called before\ndevice work in the boot state machine.\n\nBUG\u003dchrome-os-partner:22862\nBUG\u003dchrome-os-partner:22863\nBRANCH\u003dNone\nTEST\u003dBuilt and booted. Noted pattrs output.\n\nChange-Id: I073da8aca29635146fb0d4a2625b2b7564fd8414\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170403\nReviewed-by: Shawn Nematbakhsh \u003cshawnn@chromium.org\u003e\n"
    },
    {
      "commit": "a487dea6a0a4d369faffda4c25e2fa850a7ddd73",
      "tree": "6c12ba489987e9a92e37d6f70293afb5e92c3fd2",
      "parents": [
        "3e62fcdb1ef54256b9ad29870a510cab39cd80e7"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Sep 25 14:08:32 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Sep 26 21:04:43 2013 +0000"
      },
      "message": "lynxpoint: work around XHCI resume issues\n\nWhen USB3 devices are attached while in suspend, or two USB3 devices\nthat are both plugged in are switched to the other port while in\nsuspend the kernel does not seem to notice this -- despite the cold\nattach status bit.  This results in the devices showing up in the USB\nlist at the old enumerated device numbers and higher layers continuing\nto think they are present but not reseponding.\n\nWith the kernel workaround to deal with devices that are logically\ndisconnected it is possible for firmware to send a warm port reset to\ndevices that are in this state and then the kernel will see them disappear\nand handle it properly.\n\nThis same issue exists in the EFI firmware on the Whitetip Mountain 2\nreference board so it is not specifically a coreboot bug.  If this\nbehavior is fixed in the kernel then this workaround could be removed\nsince it is in RW firmware.\n\nBUG\u003dchrome-os-partner:22818\nBRANCH\u003dfalco,peppy,wolf,leon\nTEST\u003dmanual:\n\n1) attach two USB3 devices\n2) suspend system\n3) switch the ports that the USB3 devices are attatched to\n4) resume system\n5) confirm that the devices are re-enumerated and come up properly\n\nOriginal-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170335\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)\n\nChange-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170579\n"
    },
    {
      "commit": "3e62fcdb1ef54256b9ad29870a510cab39cd80e7",
      "tree": "8e81403fc84c6a00a1c1f5abb7df51cea600cdf7",
      "parents": [
        "cf1fe0524ad4793c8c422dc3fed3007b7fc96038"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Sep 25 14:08:16 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Sep 26 21:04:40 2013 +0000"
      },
      "message": "lynxpoint: xhci: more suspend/resume changes\n\nI have been attempting to work around USB3 issues that appear in the\nkernel with hacks in the firmware, but this is resulting in more\nheadaches in the kernel.\n\nInstead remove all the work that was being done at resume time and undo\nthe change that was issuing a warm reset to all ports at suspend time.\n\nThe bad device behavior will be dealt with at the kernel level to\nhandle devices that get stuck in polling state after enable/disable\nsequence.\n\nBUG\u003dchrome-os-partner:22754\nBRANCH\u003dfalco,peppy,wolf,leon\nTEST\u003dmanual:\n\nsuspend/resume with several misbehaving devices:\nKingston USB3 Media Reader\nTranscend USB3 Media Reader\nVarious ADATA USB3 drives\nVarious Kingston USB3 sticks\n\nOriginal-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170107\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n(cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7)\n\nChange-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170578\n"
    },
    {
      "commit": "cf1fe0524ad4793c8c422dc3fed3007b7fc96038",
      "tree": "3dc93517a5efd0a1db1809bac2c50d4b77e8382a",
      "parents": [
        "d9c8f93c38b1e0f9dbe84d9a2e70a8ddcda583ef"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Sep 25 14:05:31 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Thu Sep 26 15:59:00 2013 +0000"
      },
      "message": "bolt: Set GPIO29 as input in S0, output+high in S3/S5\n\nThis resolves WiFi issues after suspend/resume.\n\nIt needs related SPI descriptor soft strap change to\nenable SLP_WLAN as a GPIO instead of owned by the ME.\n\nBUG\u003dchrome-os-partner:22175\nBRANCH\u003dbolt\nTEST\u003dmanual: suspend/resume and test wifi\n\nChange-Id: I03f4458d1e52a913770d391061baa6cfa41e8558\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170577\nReviewed-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\n"
    },
    {
      "commit": "d9c8f93c38b1e0f9dbe84d9a2e70a8ddcda583ef",
      "tree": "04b9a98a910d9e84a528436d7a6e2e197447bd62",
      "parents": [
        "7316732ea0ccdc0d607bde81dbb38ca9abd29fa9"
      ],
      "author": {
        "name": "Vadim Bendebury",
        "email": "vbendeb@chromium.org",
        "time": "Tue Sep 24 22:09:28 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Sep 25 23:57:45 2013 +0000"
      },
      "message": "Provide libpayload configuration for bayleybay board\n\nThis is a copy of falco configuration with XHCI enabled and {E,O,U}HCI\ndisabled.\n\nBUG\u003dnone\nTEST\u003dmanual\n\n   $ emerge-bayleybay libpayload\n\n   now succeeds\n\nChange-Id: I25db5ac203344abc090f3f195284df88195f25b0\nSigned-off-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170553\nReviewed-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "7316732ea0ccdc0d607bde81dbb38ca9abd29fa9",
      "tree": "9ea9b38381d1858d844198be3217ff240c217c55",
      "parents": [
        "1146c570f0e448f7db4ec82749e91099c946a2dc"
      ],
      "author": {
        "name": "Julius Werner",
        "email": "jwerner@chromium.org",
        "time": "Thu Sep 19 20:15:45 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Wed Sep 25 01:23:35 2013 +0000"
      },
      "message": "exynos5420: Don\u0027t map low addresses that lead nowhere\n\nI just spent half a day (including the time to implement a stack dumper)\nto figure out that I am reading from a NULL pointer. A problem this\nsimple should be more easy to catch. Let\u0027s mark the address range below\nSRAM as uncached so that the MMU can yell at you right away for being\nthe bad programmer you are when you access a NULL pointer.\n\nBUG\u003dNone\nTEST\u003dManual\n\nChange-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53\nSigned-off-by: Julius Werner \u003cjwerner@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170112\nReviewed-by: Ronald Minnich \u003crminnich@chromium.org\u003e\n"
    },
    {
      "commit": "1146c570f0e448f7db4ec82749e91099c946a2dc",
      "tree": "2c67aa73f017357fd218bd4efa6ac86c91f9eef9",
      "parents": [
        "0ce3898276ff49d171a0d8a650806f0305c0576f"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Sep 24 03:05:12 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 23:14:31 2013 +0000"
      },
      "message": "ARM: Eliminate the unused interrupts.c.\n\nThis file isn\u0027t compiled into anything, and probably wouldn\u0027t since it has a\nlot of baggage from it\u0027s U-Boot origins.\n\nBUG\u003dNone\nTEST\u003dBuilt for pit.\nBRANCH\u003dNone\n\nChange-Id: I29d87afd2a283010a653d3d48fdd3a79622e3b99\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170423\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: David Hendrix \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "0ce3898276ff49d171a0d8a650806f0305c0576f",
      "tree": "231ad351a99e9e862c23e215f1606637db73568c",
      "parents": [
        "9187925dfe2f3c5432449a745a7c24c5635f0b0b"
      ],
      "author": {
        "name": "Gabe Black",
        "email": "gabeblack@google.com",
        "time": "Tue Sep 24 02:36:36 2013 -0700"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 23:14:28 2013 +0000"
      },
      "message": "exynos: Get rid of the unused reset.c.\n\nThe source file reset.c, present in both the exynos5250 and 5420 directories,\nis not being built for either SOC. Let\u0027s get rid of the clutter.\n\nBUG\u003dNone\nTEST\u003dBuilt for snow and pit.\nBRANCH\u003dNone\n\nChange-Id: Iab4c7982a271d08cbaf3207b6f5431f0ef52697e\nSigned-off-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/170402\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: David Hendrix \u003cdhendrix@chromium.org\u003e\nCommit-Queue: Gabe Black \u003cgabeblack@chromium.org\u003e\nTested-by: Gabe Black \u003cgabeblack@chromium.org\u003e\n"
    },
    {
      "commit": "9187925dfe2f3c5432449a745a7c24c5635f0b0b",
      "tree": "f62a993592f97bc0aa9c91def4ee810591946228",
      "parents": [
        "faef9c616949630d44be1ce5944d2e0e332176dc"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Mon Sep 23 14:17:35 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 21:00:19 2013 +0000"
      },
      "message": "baytrail: add dunit access and registers\n\nThe dunit on baytrail is the dram unit. Provide a means\nto access the configuration registers there using the\nproper IOSF mechanisms.\n\nBUG\u003dchrome-os-partner:22875\nBRANCH\u003dnone\nTEST\u003dBuilt and booted. Able to read dram registers.\n\nChange-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170490\n"
    },
    {
      "commit": "faef9c616949630d44be1ce5944d2e0e332176dc",
      "tree": "e77bedecb95ade4d1b5df0df77836d05bb836200",
      "parents": [
        "246d4edf694eacce0004421694a379aa30d750ac"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Sep 24 12:41:08 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 21:00:15 2013 +0000"
      },
      "message": "baytrail: set host memory map\n\nPrior to this commit the coreboot resource allocator\nwas not using proper addresses. That\u0027s not surprising there\nwasn\u0027t any code to initialize the resources properly. This\ncommit initializes the memory map accoring to the BUNIT\nregisters.\n\nBUG\u003dchrome-os-partner:22860\nBUG\u003dchrome-os-partner:22862\nBRANCH\u003dNone\nTEST\u003dBuilt and booted. Noted output for resource assignments\n     is sane.\n\nChange-Id: Ice8d067d8b993736de5c5b273a0f642fa034a024\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170429\n"
    },
    {
      "commit": "246d4edf694eacce0004421694a379aa30d750ac",
      "tree": "f528eda5493dc75e455f35b4a1945c20d7688cc3",
      "parents": [
        "f89e5732c80a376e276c8e9428a38cfd8d7fa1dd"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Sep 24 12:29:57 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 21:00:11 2013 +0000"
      },
      "message": "baytrail: add common pci_operations\n\nThe coreboot device modeling for pci devices wants\na pci_operations structure for all devices. This structure\njust sets the subsystem vendor and device id. Add a common\none that all the other pci drivers can use for Bay Trail.\n\nBUG\u003dchrome-os-partner:22860\nBRANCH\u003dNone\nTEST\u003dBuilt and booted while utilizing this new structure.\n\nChange-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170428\n"
    },
    {
      "commit": "f89e5732c80a376e276c8e9428a38cfd8d7fa1dd",
      "tree": "38c09068464460882ef387edc8b0e444350b996f",
      "parents": [
        "05a43dae9f82aeef671b57330f0476eac1896c32"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Tue Sep 24 12:36:14 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 21:00:08 2013 +0000"
      },
      "message": "baytrail: initialize graphics before MRC\n\nThe graphics device needs to have its resource contraints\ninitialized before running the reference code. Right now just\nuse a 256MiB aperture, 32MiB of stolen memory data, and 2MiB\nGTT memory.\n\nBUG\u003dchrome-os-partner:22869\nBRANCH\u003dNone\nTEST\u003dBuilt and booted. Noted amount of stolen memory matches\n     configuration as well as BAR size within the graphics\n     device.\n\nChange-Id: I328bf858f288363187cf705d6340947393b5ff10\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170427\n"
    },
    {
      "commit": "05a43dae9f82aeef671b57330f0476eac1896c32",
      "tree": "976c05c01ffa161741189436796d3a345564d0ee",
      "parents": [
        "1bd9e2505aa0acad14c64224a380454810ce64c1"
      ],
      "author": {
        "name": "Aaron Durbin",
        "email": "adurbin@chromium.org",
        "time": "Mon Sep 23 14:15:42 2013 -0500"
      },
      "committer": {
        "name": "chrome-internal-fetch",
        "email": "chrome-internal-fetch@google.com",
        "time": "Tue Sep 24 21:00:04 2013 +0000"
      },
      "message": "baytrail: cache ROM space early in bootblock\n\nTake advantage of the cache early in bootblock. The\nintent is to speed up cbfs walking when trying to locate\nromstage.\n\nBUG\u003dchrome-os-partner:22857\nBRANCH\u003dNone\nTEST\u003dBuilt and booted.\n\nChange-Id: If03210103c9782390230915db3b4a9759d172dce\nSigned-off-by: Aaron Durbin \u003cadurbin@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/170426\nReviewed-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\n"
    }
  ],
  "next": "1bd9e2505aa0acad14c64224a380454810ce64c1"
}