tree 62fa4f7a06b0df352464dc1f2d7010255e0f24f3
parent d4a9b4df917a41799d7d9e87e89ab4e5a3384fb7
author Subrata Banik <subrata.banik@intel.com> 1582119546 +0530
committer Commit Bot <commit-bot@chromium.org> 1582564612 +0000

UPSTREAM: soc/intel/icelake: Skip FSP-S IGD related UPD override

Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence
related FSP-S UPD override can be avoided from coreboot.

As per FSP-S UPD Header (FspsUpd.h)

/** Offset 0x020E - GT Frequency Limit
  0xFF: Auto(Default)
**/
UINT8 GtFreqMax;

/** Offset 0x0209 - CdClock Frequency selection
  0: (Default) Auto
**/
UINT8 CdClock;

TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform.

Change-Id: I60fd2a2366b2fbbd0cfbecd24f35bb9bd03a1049
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d667906f3c0029dbea41580a0d0961cf1ab2fc9
Original-Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2070308
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>