| commit | 99abbbdbe7e61338024021f031359c7581c726c2 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Wed Feb 19 19:09:06 2020 +0530 |
| committer | Commit Bot <commit-bot@chromium.org> | Mon Feb 24 17:16:52 2020 +0000 |
| tree | 62fa4f7a06b0df352464dc1f2d7010255e0f24f3 | |
| parent | d4a9b4df917a41799d7d9e87e89ab4e5a3384fb7 [diff] |
UPSTREAM: soc/intel/icelake: Skip FSP-S IGD related UPD override Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: I60fd2a2366b2fbbd0cfbecd24f35bb9bd03a1049 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9d667906f3c0029dbea41580a0d0961cf1ab2fc9 Original-Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2070308 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.