tree 995ed342562fec9d0e5e34267be0bb9a3267049e
parent 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5
author Archana Patni <archana.patni@intel.com> 1444248727 +0530
committer chrome-bot <chrome-bot@chromium.org> 1445287549 -0700

kunimitsu: csme: program sml gpios for csme power gating

For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive.

The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables.
SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are
now configured as GPIOs - input and deep.

With this change, the SMT blocks are properly power gating.

BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for Kunimitsu, boot on FAB3.

Change-Id: I00dca84a3f6ba7bda4ca1c206b49ff81482279a5
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/306391
Reviewed-by: Aaron Durbin <adurbin@chromium.org>