tree f0fafc5c5b2010c1a8c7a82587baecc38481aff0
parent 26f45c9462095c96b013e0391f4e64a08b78867a
author David Hendricks <dhendrix@chromium.org> 1376339064 -0700
committer ChromeBot <chrome-bot@google.com> 1376356810 -0700

exynos5420: don't assume MPLL for i2c parent clock

This reads the clock select field for MUX_ACLK_66_SEL in the
CLK_SRC_TOP1 register in order to obtain the source clock rate
for I2C peripherals. Before we were always assuming that the source
was the MPLL.

Unfortunately not all fields in the CLK_SRC_TOPn registers are
enumerated the same with regard to clock select. So this is just
a one-off for now.

This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

BUG=none
BRANCH=none
TEST=built and booted on Pit

Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
Reviewed-on: https://gerrit.chromium.org/gerrit/65611
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>