tree 0012a3a3945f7fc0a082122dd9f8aeb86ae4b2b1
parent 03b4a11d0017efd36c487497581866dc2c2dba05
author Gaggery Tsai <gaggery.tsai@intel.com> 1546021604 -0800
committer ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> 1547279076 +0000

src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260

This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.

BUG=b:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
     related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
     ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
     and ensure bit10 is set.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Reviewed-on: https://chromium-review.googlesource.com/c/1407535
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Commit-Queue: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>