UPSTREAM: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: I952f3aba3b3a17a9f570612439f499718f88ace3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ef250c47e4726c2648c96d1d06f7da45b221c359
Original-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Original-Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Original-Reviewed-on: https://review.coreboot.org/28424
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/1217808
Reviewed-by: Caveh Jalali <caveh@google.com>
Commit-Queue: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
2 files changed
