Skylake: gpio macro adding - Unused gpio pins
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.
BUG=none
BRANCH=none
TEST=Build and boot lars
Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/319964
Commit-Ready: David Wu <david_wu@quantatw.com>
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
1 file changed
