libpayload: usb: Support MTK xHCI host controller
1. There is a mis-understanding to caculate the value of TD Size
in Normal TRB. For MTK's xHCI controller it defines a number of
packets that remain to be transferred for a TD after processing
all Max packets in all previous TRBs,that means don't include the
current TRB's.
2. To minimize the scheduling effort for synchronous endpoints in xHC,
the MTK architecture defines some extra SW scheduling parameters for
HW. According to these parameters provided by SW, the xHC can easily
decide whether a synchronous endpoint should be scheduled in a specific
uFrame. The extra SW scheduling parameters are put into reserved DWs
in Slot and Endpoint Context. But in core-boot synchronous transfer can
be ignored, so only tow fields are set to a default value 1 to support
bulk and interrupt transfers, and others are set to zero.
3. For control transfer, it is better to read back doorbell register or add
a memory barrier after ringing the doorbell to flush posted write.
Otherwise the first command will be aborted on MTK's xHCI controller.
4. Before send commands to a port, the Port Power in PORTSC register should
be set to 1 on MTK's xHCI. so a hook function of enbale_port in
generic_hub_ops_t struct is provided.
Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/265362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Tested-by: Yidi Lin <yidi.lin@mediatek.com>
6 files changed
