##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

chip soc/nvidia/tegra124
	device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
	register "display_controller" = "TEGRA_ARM_DISPLAYA"
	register "xres" = "1366"
	register "yres" = "768"

	# bits per pixel and color depth
	register "framebuffer_bits_per_pixel" = "16"
	register "color_depth" = "6"
	# "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h

	register "panel_bits_per_pixel" = "18"

	register "cache_policy" = "DCACHE_WRITETHROUGH"

	# With some help from the mainbaord designer
	register "backlight_en_gpio" = "GPIO(H2)"
	register "lvds_shutdown_gpio" = "0"
	register "backlight_vdd_gpio" = "GPIO(P2)"
	register "panel_vdd_gpio" = "0"
	register "pwm" = "1"

	# various panel delay time
	register "vdd_delay_ms" = "200"
	register "pwm_to_bl_delay_ms" = "10"
	register "vdd_to_hpd_delay_ms" = "200"
	register "hpd_unplug_min_us" = "2000"
	register "hpd_plug_min_us" = "250"
	register "hpd_irq_min_us" = "250"

# How to compute these: xrandr --verbose will give you this:
#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
#               2560 2608 2640 2720 hborder 0
#               1700 1703 1713 1749 vborder 0
#Then you can compute your values:
#H front porch = 2608 - 2560 = 48
#H sync = 2640 - 2608 = 32
#H back porch = 2720 - 2640 = 80
#V front porch = 1703 - 1700 = 3
#V sync = 1713 - 1703 = 10
#V back porch = 1749 - 1713 = 36
#href_to_sync and vref_to_sync are from the vendor
#this is just an example for a Pixel panel; other panels differ.
# Here is a peppy panel:
#  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
#        h: width  1366 start 1502 end 1532 total 1592
#        v: height  768 start  776 end  788 total  800
	register "href_to_sync" = "1"
	register "hfront_porch" = "136"
	register "hsync_width" = "30"
	register "hback_porch" = "60"

	register "vref_to_sync" = "1"
	register "vfront_porch" = "8"
	register "vsync_width" = "12"
	register "vback_porch" = "12"

	register "pixel_clock" = "76400000"

	# link configurations
	register "lane_count" = "1"
	register "enhanced_framing" = "1"
	register "link_bw" = "10"
	# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h

	register "drive_current" = "0x40404040"
	register "preemphasis" = "0x0f0f0f0f"
	register "postcursor" = "0"
end