tree 95bb723377213892049f8577bfeb194bcfd9b900
parent e1c53f8399d5b682564aab50a427f8d58c0c2e4d
author Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> 1675820781 +0800
committer Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> 1677123497 +0000

UPSTREAM: soc/mediatek/mt8188: Fix audio sampling rate

The current clock register definition is wrong, which results in wrong
audio sampling rate. Fix it by adjusting the POSTDIV registers of
APLL1-APLL5.

TEST=build pass
BUG=b:250459803, b:250464574

(cherry picked from commit fb660c35b507e6d7775c0647bc267d0294bf172d)

Original-Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0
Original-Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134
Original-Reviewed-by: Yidi Lin <yidilin@google.com>
Original-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Yu-Ping Wu <yupingso@google.com>
GitOrigin-RevId: fb660c35b507e6d7775c0647bc267d0294bf172d
Change-Id: Ia0327a57631f6d04337126f1f16c753457a1e511
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4280739
Reviewed-by: Kangheui Won <khwon@chromium.org>
Commit-Queue: Kangheui Won <khwon@chromium.org>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>