| commit | 1a9540d27fe2aac351d004dc5442d87358f46165 | [log] [tgz] |
|---|---|---|
| author | Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> | Fri Sep 23 09:59:46 2022 +0800 |
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Thu Oct 20 02:22:54 2022 +0000 |
| tree | 13bae7868913d25a7ec18d551bf8f4ceae3e0aa8 | |
| parent | 3e9beffc00e974687ebab2a3023e2a18efce43bb [diff] |
UPSTREAM: mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4 This change disables unused PCIE RP8 and CLKSRC4. Without this change storo cannot enter into s0ix properly. BUG=b:219376808 TEST=Built and verified in storo (cherry picked from commit 55d47bd1bfb38aec5253529fded126e0c9238a89) Original-Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d Original-Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Original-Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Original-Reviewed-by: Henry Sun <henrysun@google.com> Original-Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Original-Reviewed-by: Aamir Bohra <aamirbohra@google.com> GitOrigin-RevId: 55d47bd1bfb38aec5253529fded126e0c9238a89 Change-Id: I844962105dc041fa9907e8ccf04611a8bbe39efe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3966768 Tested-by: CopyBot Service Account <copybot.service@gmail.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Commit-Queue: Reka Norman <rekanorman@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.