commit | 9610fdfa473cc52c70b9476edaad2ccb0eef6354 | [log] [tgz] |
---|---|---|
author | Bora Guvendik <bora.guvendik@intel.com> | Tue Jul 19 13:50:41 2022 -0700 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Thu Sep 15 11:14:26 2022 +0000 |
tree | 0d26aa08860004cc4f8905383791f18705c18277 | |
parent | 0f5bb8ce02667211d807fe1d78842e3cf6a2e3af [diff] |
UPSTREAM: mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl Configure GPIO pins, add Kconfig options and enable TPM device in devicetree. Add H1 TPM IRQ GPIO pin in gpio.c BUG=none BRANCH=firmware-brya-14505.B TEST=Boot the image and check the successful TPM communication in verstage,romstage & ramstage from coreboot logs. (cherry picked from commit 323bddb1bdf53e5b871339868272cd7324856262) Cq-Depend: chromium:3774914 Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Original-Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Original-Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> GitOrigin-RevId: 323bddb1bdf53e5b871339868272cd7324856262 Change-Id: Iace4b3aa7028f0043e4bad4828fb140c411c6254 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3888804 Reviewed-by: Yu-Ping Wu <yupingso@chromium.org> Tested-by: CopyBot Service Account <copybot.service@gmail.com> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.