[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see src/mainboard/starlabs/labtop/variants/cml/romstage.c
Prior to building coreboot the following files are required:
The files listed below are optional:
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
The following commands will build a working image:
make distclean make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml make
+---------------------+------------+ | Type | Value | +=====================+============+ | Socketed flash | no | +---------------------+------------+ | Vendor | Winbond | +---------------------+------------+ | Model | 25Q128JVSQ | +---------------------+------------+ | Size | 16 MiB | +---------------------+------------+ | Package | SOIC-8 | +---------------------+------------+ | Internal flashing | yes | +---------------------+------------+ | External flashing | yes | +---------------------+------------+ Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.