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cos / mirrors / cros / chromiumos / third_party / coreboot / 000a6e7bca83c6a102000ecb1de0e16f67f19f90
commit000a6e7bca83c6a102000ecb1de0e16f67f19f90[log] [tgz]
authorFelix Held <felix-coreboot@felixheld.de>Fri Jun 11 02:11:22 2021 +0200
committerCommit Bot <commit-bot@chromium.org>Wed Feb 16 08:53:17 2022 +0000
treedfbb37798b69ededea7d77cc196e556ec3d6e64b
parente4ee0cf587e3944f8bf62c08ad1fd68b8a49ee28 [diff]
UPSTREAM: soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUS

Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC
talk to each other via the system bus, there is no longer the
requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that
start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2
as the IOAPIC ID while most of their CPUs have more than 2 logical cores
resulting in the IOAPIC having the same ID as one of the LAPICs.

All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and
GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT
and IVRS ACPI tables and there's no MPTable support for those SoCs that
might also rely on those IDs being consistent.

This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID
from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes
sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a
CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4
bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of
IOAPIC IDs, this is non-standard.

TEST=AMD Mandolin and Google Liara still work.

(cherry picked from commit 399d3cf8782673bb1cf62bca028d43eb95cc5f6e)

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Original-Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb
GitOrigin-RevId: 399d3cf8782673bb1cf62bca028d43eb95cc5f6e
Change-Id: Ie12cab02aef76e5a783231cfc83dddb2e99a745b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3461748
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Reviewed-by: Ricardo Quesada <ricardoq@chromium.org>
Commit-Queue: Ricardo Quesada <ricardoq@chromium.org>
1 file changed
tree: dfbb37798b69ededea7d77cc196e556ec3d6e64b
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. OWNERS
  22. PRESUBMIT.cfg
  23. README.md
  24. toolchain.inc
  25. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.