tree 0d086b0e57b6d7db51648f6b7690268bec002ae3
parent a18f90b3714e6ae3b837723ad1968447365653f4
author Meera Ravindranath <meera.ravindranath@intel.com> 1613967823 +0530
committer Commit Bot <commit-bot@chromium.org> 1626390219 +0000

soc/intel/alderlake: Implement WA for DDR5 DIMM modules

The coreboot SMBus driver requires additional changes to accomodate
the DDR5 EEPROM read which has resulted in a broken code flow for boot.

This CL serves as a temp WA to let FSP perform the SPD read for DDR5
and pass SPD addresses to FSP UPD array.

BUG=b:180458099
TEST=Build and boot DDR5 adlrvp to OS

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2987840
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>