tree 953aeff46c91168feb7a1978b57c092e3f6a1211
parent 99f5a25b141193ad9829aeb7738898994c041a09
author Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> 1622820915 -0500
committer Commit Bot <commit-bot@chromium.org> 1623111016 +0000

soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB

EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.

BUG=b:190153208
TEST=verify HOB is present and correct size (13) is reported

Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Cq-depend: chrome-internal:3889619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2945229
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>