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cos / mirrors / cros / chromiumos / third_party / coreboot / refs/heads/stabilize-13974.B
commit56779abd67462f3f2c234038e37a80dc4343c14a[log] [tgz]
authorNick Vaccaro <nvaccaro@google.com>Tue May 11 16:41:37 2021 -0700
committerCommit Bot <commit-bot@chromium.org>Sat May 15 03:09:59 2021 +0000
tree296f0981eec806697eedbeb176efcb2c3d4fdaf7
parentc15bd7832f4c3a1e9edb636931f0787c325d3211 [diff]
UPSTREAM: mb/google/volteer: Configure TCSS OC pins

TCSS OC pins have not been correctly configured for volteer.
This patch fills the value from devicetree to correct the OC pins
mapping.

BUG=b:184660529
BRANCH=None
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and
verify CpuUsb3OverCurrentPin UPDs get set correctly.

Change-Id: Ic32f615b65297d5c47728b84029c86a1fe254f62
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Original-Commit-Id: 97b608feed7fddf40a586ca3600b35bc877aa341
Original-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9
Original-Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2898064
1 file changed
tree: 296f0981eec806697eedbeb176efcb2c3d4fdaf7
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. tests/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.