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cos / mirrors / cros / chromiumos / third_party / coreboot / refs/heads/stabilize-13821.B
commita27438d4b28f2248e3aa88cd9793c2d96ec7bccd[log] [tgz]
authorAnil Kumar <anil.kumar.k@intel.com>Fri Sep 18 15:30:56 2020 -0700
committerCommit Bot <commit-bot@chromium.org>Sun Feb 28 00:40:29 2021 +0000
tree21208f82b4a5cd63c1b6111d57324e94432473cb
parentc835b8a1e331e3fcf54bb3e6251b3d51989185da [diff]
UPSTREAM: drivers/soundwire/alc1308 : Add ALC1308 soundwire device

This patch adds new soundwire device ALC1308

The codec properties are filled out as best as possible
with the datasheet as a reference.

The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.

The unique ID is calculated from schematics by referring to ASEL[1:0]
strap settings. Datasheet of ALC1308 provides info about the mapping of
ASEL strap settings to unique ID

For example this device is connected to master link ID 1 and has strap
settings configuring it for unique ID 2.

chip drivers/soundwire/alc1308
  register "desc" = ""Left Speaker""
  device generic 1.2 on end
  end

Bug=None
Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for
PCI0.HDAS.SNDW are present for ALC1308
Test speaker out functionality

BUG=none
BRANCH=none
TEST=none

Change-Id: I3df72d4272a90ebd27a079ce14d30cb6963d61c8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d7c31d1dbe89a54db8e244c2b0d746f58a1bd8ad
Original-Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Original-Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Sathyanarayana Nujella
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2726193
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
5 files changed
tree: 21208f82b4a5cd63c1b6111d57324e94432473cb
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. tests/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.