tree 97fbf011fa98f138769b6251a7388762295fc60e
parent 892686a808f0fb97e0e34ee0747e249e48eb719b
author John Zhao <john.zhao@intel.com> 1596392999 -0700
committer Commit Bot <commit-bot@chromium.org> 1597842866 +0000

UPSTREAM: mb/intel/tglrvp: Add interrupt _CRS under CREC scope

Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.

BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Commit-Id: 90883287b5db3c022bf45d98a00f88b4b9b7c055
Original-Signed-off-by: John Zhao <john.zhao@intel.com>
Original-Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Original-Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Iaf2c549ac96bf822d67b88a98c94a05fff712a0a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2354974
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>