tree ab4e3abfa13c7f513203b63c84d6b8ca5122bd25
parent 6c13c889f707dba84e3636d6593cbd5b37caf087
author Furquan Shaikh <furquan@google.com> 1592935890 -0700
committer Commit Bot <commit-bot@chromium.org> 1593118315 +0000

mb/google/zork: Configure GPIO_40 as drive low in sleep path

This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>