| commit | e3af8f8b1debf8c90854fb12719bce6eb6fb222a | [log] [tgz] |
|---|---|---|
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | Mon Feb 25 10:46:18 2019 +0300 |
| committer | chrome-bot <chrome-bot@chromium.org> | Thu Mar 07 20:21:05 2019 -0800 |
| tree | 6348a6cd130954d9bc78ef765e96300ef6128058 | |
| parent | b6e7a400d9a72cce9590dabb00dd22b39605764d [diff] |
UPSTREAM: soc/intel/skylake: Add new Northbridge and IGD IDs This patch adds support 1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host Bridge/DRAM Registers - 191F; 2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor https://en.wikichip.org/wiki/intel/hd_graphics/530. This is required to run coreboot on the Intel Core i5-6600 (Skylake) desktop processor. It has been tested on ASRock H110M-DVS motherboard. BUG=none BRANCH=none TEST=none Change-Id: I1aa96bfc52989d5f1114ffd4ade8679aa1ebdc74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 46e6852062dfe87281860659034bf20ca16d7aa6 Original-Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Original-Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601 Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1506748 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.