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cos / mirrors / cros / chromiumos / third_party / coreboot / refs/heads/release-R109-15236.B
commit4d6cafe9510e0d1adefdfb5bbe0d566c01bdd9d7[log] [tgz]
authorzhaojohn <john.zhao@intel.com>Thu Sep 22 20:33:57 2022 -0700
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Wed Nov 09 21:39:41 2022 +0000
tree75c27d8d7a71e467e3542b84682243b3d2486f59
parenta899182c80fa6af8e2d572d2001f9b9e0b7d30f8 [diff]
UPSTREAM: soc/intel/meteorlake: Provide mitigation support for CNVi RFI

The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake.

BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.

(cherry picked from commit a923a431c6f10da70bec075583d4eb9ddaccacac)

Original-Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Original-Signed-off-by: zhaojohn <john.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GitOrigin-RevId: a923a431c6f10da70bec075583d4eb9ddaccacac
Change-Id: I915e9c15b692f4f825149026eb8a35908611c90a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4007455
Commit-Queue: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
1 file changed
tree: 75c27d8d7a71e467e3542b84682243b3d2486f59
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. .mailmap
  16. AUTHORS
  17. COPYING
  18. gnat.adc
  19. MAINTAINERS
  20. Makefile
  21. Makefile.inc
  22. OWNERS
  23. PRESUBMIT.cfg
  24. README.md
  25. toolchain.inc
  26. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.