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cos / mirrors / cros / chromiumos / third_party / coreboot / 33b84ba18d408e0ca24e62e8f7026dbf38798a32
commit33b84ba18d408e0ca24e62e8f7026dbf38798a32[log] [tgz]
authorRaul E Rangel <rrangel@chromium.org>Mon Dec 06 10:53:54 2021 -0700
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Fri Sep 08 07:53:46 2023 +0000
treed38d5cdb7faeb28dfb79f15630fe5406f2913ba9
parent4b9c7df5cc8ca0db181c34abb8d82d4f8a988d01 [diff]
soc/amd/picasso: Clear PM/GPE when enabling ACPI

According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states#

> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit.

This change makes sure we clear the PM/GPE blocks are cleared before
enabling the SCI_EN bit.

BUG=b:172021431,b:208869120
TEST=Boot morphius to OS and verify suspend resume still
works.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
GitOrigin-RevId: c7ab9f410cfea6bd6260ecb8ac336f87f4cf3736
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3327717
Tested-by: Copybara Service <copybara-worker-blackhole@google.com>
Reviewed-by: Dossym Nurmukhanov <dossym@chromium.org>
Commit-Queue: Dossym Nurmukhanov <dossym@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3677890
Commit-Queue: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Tested-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Auto-Submit: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Murphy <jpmurphy@google.com>
1 file changed
tree: d38d5cdb7faeb28dfb79f15630fe5406f2913ba9
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. PRESUBMIT.cfg
  22. README.md
  23. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.