commit | a219feac5607019585c6d3587540d2bec4f79d49 | [log] [tgz] |
---|---|---|
author | Tim Wawrzynczak <twawrzynczak@chromium.org> | Tue Feb 23 13:11:36 2021 -0700 |
committer | Commit Bot <commit-bot@chromium.org> | Fri Feb 26 01:39:18 2021 +0000 |
tree | c46f513bcb5dfdc9741865350a68337d4c7050d4 | |
parent | fc1ec8562ae3db4630008eff84bdc5840a4a3a2b [diff] |
UPSTREAM: mb/google/volteer: Fix eldrid DPTF's passive and critical policies Because the entries were formatted differently to the baseboard, the devicetree overrides didn't work as intended, and all 5 entries from the baseboard were included, and then the overrides were applied, but the baseboard's entries were kept, so there were duplicate ACPI entries, which causes errors when parsing the table. Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid") BUG=b:181034399 TEST=compile, verify static.c is correct now Change-Id: I29c185c98ce857038bd0bcfada13bfa2470abe0b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Original-Commit-Id: 74dfbd09feea216da5a91f6768038de8cf37d8aa Original-Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Original-Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044 Original-Reviewed-by: YH Lin <yueherngl@google.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2720016
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.