Google Git
Sign in
cos / mirrors / cros / chromiumos / third_party / coreboot / refs/heads/firmware-volteer-13672.47.B
commit117d23717fd800a87b5f4ca3a65954b6fd3c822e[log] [tgz]
authorYH Lin <yueherngl@chromium.org>Wed Mar 24 05:51:34 2021 +0000
committerCommit Bot <commit-bot@chromium.org>Wed Mar 24 05:57:04 2021 +0000
tree5262143b2efdd8990291732b58711cffdd877768
parent2631e58936362a080f15bd716a4b72c58523430e [diff]
Revert "UPSTREAM: mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnable"

This reverts commit 2631e58936362a080f15bd716a4b72c58523430e.

Reason for revert: the CL is not needed in this branch.

Original change's description:
> UPSTREAM: mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnable
>
> eDP panel flicker during system idle state is observed.
> Disabling USB2 SUS well power gating can remove flicker symptom.
> Please refer to doc#634894 for more details.
>
> BUG=b:182323059
> BRANCH=None
> TEST=Boot and confirm no display flicker.
>
> Change-Id: I3c0b86acd4da80d9c93ada41b9bff1d0611c3bf3
> Signed-off-by: Patrick Georgi <pgeorgi@google.com>
> Original-Commit-Id: c6bc3a56d684307770737a0ca1c34690a1289d00
> Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
> Original-Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083
> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613
> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2781720
> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
> Tested-by: Patrick Georgi <pgeorgi@chromium.org>
> (cherry picked from commit b3dce4a1e6793aa3d29302c427b20e757331c0da)
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2782410
> Reviewed-by: YH Lin <yueherngl@chromium.org>
> Commit-Queue: YH Lin <yueherngl@chromium.org>
> Tested-by: YH Lin <yueherngl@chromium.org>

Bug: b:182323059
Change-Id: I3f79c09f712222f957ebcd66d8269ba1c366aa5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2783370
Reviewed-by: YH Lin <yueherngl@chromium.org>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
1 file changed
tree: 5262143b2efdd8990291732b58711cffdd877768
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. tests/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.