tree c5b910200df883ce1820af88968bdceb8ec8cf47
parent 9dfc2210e35714bf34c5671149a811e18d8d8175
author Vijay Navnath Kamble <vkambl@codeaurora.org> 1582787108 +0530
committer Commit Bot <commit-bot@chromium.org> 1592292889 +0000

qclib: Update qclib DDR Training data section

The DDR bitflips,corruption issues seen with 739 MHz DDR Freq are
not seen with DDR Freq 672 MHz. Next release of coreboot will
have DDR freq set to 672 MHz. But with change in DDR freq, there
is a need of DDR Training Data update. Currently "RO_DDR_TRAINING"
section is used for DDR Training data. But we can not use this
section as its Factory locked and can not be updated.
So we need to use other section for DDR Training data update which
is "RW_DDR_TRAINING".

BUG=b:141614863
BRANCH=mistral
TEST=firmware autoupdate

Change-Id: I63e9751fc99a22b31b8d247de75f55b8adb30bb5
Signed-off-by: Vijay Navnath Kamble <vkambl@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2077257
Reviewed-by: nsekar nsekar <nsekar1@qualcomm.corp-partner.google.com>
Reviewed-by: Yuji Sasaki <sasakiy@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Yuji Sasaki <sasakiy@google.com>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>