commit | 7156124b2363e847ad8a359158031fe037078217 | [log] [tgz] |
---|---|---|
author | Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> | Wed Dec 23 11:45:59 2020 +0800 |
committer | Commit Bot <commit-bot@chromium.org> | Fri Jan 01 04:09:10 2021 +0000 |
tree | a61eea95534bb4dc82c0a8ba3595570f434f38b6 | |
parent | 92d6dae0876e57cf6bbb63231f50f20d407a12c2 [diff] |
soc/mediatek: dsi: Fix EoTp flag SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Original-signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Original-change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/48868 Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-reviewed-by: Yu-Ping Wu <yupingso@google.com> Change-Id: Ib0f5ade96bd3699681912900c392e52f9c8fdb2f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2608239
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.