tree b0fcae71e607e55e4febf8e5e68d80d445740d8d
parent 6239eaa093603a30ca8dc728aa65b32e99c2de22
author Marek Maslanka <mmaslanka@google.com> 1704887087 +0000
committer Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> 1705018290 +0000

CHROMIUM: soc/intel/skylake: Enable the ACPI PM Timer explicitly

Explicitly enable the ACPI PM Timer if the variable PmTimerDisabled is
set to "0". This is necessary because the ACPI PM timer is enabled by
default after reset, but after silicon initialization by FSP in
src/drivers/intel/fsp2_0/silicon_init.c:50, the timer is disabled.

Since upstream coreboot does not support the Fizz platform, this patch
is denoted as a CHROMIUM patch.

BUG=b:314260167
TEST=Build and deploy the firmware onto the device. Run the system. Use
the “iotools mmio_read8 0xfe0000fc” command to read the ACPI Timer
Control (ACPI_TMR_CTL) register. Verify if the second bit is cleared to
ensure that the ACPI PM timer is enabled.

Change-Id: I4612b0c434c28485026366993552e3655b6fd08a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5182716
Commit-Queue: Marek Maślanka <mmaslanka@google.com>
Tested-by: Marek Maślanka <mmaslanka@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>