#
# This file is part of the coreboot project.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip soc/amd/picasso

	# Start : OPN Performance Configuration
	# See devhub #55593 Chapter 3.2 for documentation
	# For the below fields, 0 indicates use SOC default

	# System config index
	register "system_config" = "2"

	# Set STAPM confiuration. All of these fields must be set >0 to take affect
	register "slow_ppt_limit" = "25000" #mw
	register "fast_ppt_limit" = "30000" #mw
	register "slow_ppt_time_constant" = "5" #second
	register "stapm_time_constant" = "200" #second
	register "sustained_power_limit" = "15000" #mw

	register "telemetry_vddcr_vdd_slope" = "71222" #mA
	register "telemetry_vddcr_vdd_offset" = "0"
	register "telemetry_vddcr_soc_slope" = "28977" #mA
	register "telemetry_vddcr_soc_offset" = "0"

	# End : OPN Performance Configuration

	# Enable I2C2 for trackpad, touchscreen, pen at 400kHz
	register "i2c[2]" = "{
		.speed = I2C_SPEED_FAST,
		.rise_time_ns = 21,  /* 0 to 2.31 (3.3 * .7) */
		.fall_time_ns = 76,  /* 2.31 to 0 */
	}"

	# Enable I2C3 for H1 400kHz
	register "i2c[3]" = "{
		.speed = I2C_SPEED_FAST,
		.rise_time_ns = 125,  /* 0 to 1.26v (1.8 * .7) */
		.fall_time_ns = 37,  /* 1.26v to 0 */
		.early_init = true,
	}"

	# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
	device domain 0 on
		subsystemid 0x1022 0x1510 inherit
		device pci 1.6 off end # GPP Bridge 5
		device pci 1.7 on  end # GPP Bridge 6 - NVME
		device pci 8.1 on      # Internal GPP Bridge 0 to Bus A
			device pci 0.3 on  end # USB 3.1
			device pci 0.4 on  end # USB 3.1
		end
		device pci 14.6 off end # Non-Functional SDHCI
	end # domain

	device mmio 0xfedc4000 on end

end	# chip soc/amd/picasso