commit | ae737c20a680ffa7fcc55a20fc4ee258f8210a73 | [log] [tgz] |
---|---|---|
author | Simon Yang <simon1.yang@intel.com> | Fri Apr 22 14:07:16 2022 +0800 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Mon May 09 15:57:02 2022 +0000 |
tree | 228a877e988a1d5a4bb2bad1204d9fa8ce7d60c1 | |
parent | b7f2ee574adf779314875e0db7dd0c1123108321 [diff] |
UPSTREAM: soc/intel/jasperlake: Revert CdClock setting Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 GitOrigin-RevId: dec327b03b2fbf6dc6f89599107f645ed6a5396f Change-Id: Idc4316dfbdff5b29c6c8085581b19ae69c8df8af Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3613501 Tested-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: CopyBot Service Account <copybot.service@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Commit-Queue: Nick Vaccaro <nvaccaro@google.com> Tested-by: Simon Yang <simon1.yang@intel.corp-partner.google.com> (cherry picked from commit ef89207f749bb6cd9525242c2365c4035d9a3808) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3616196 Commit-Queue: Henry Sun <henrysun@google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.