commit | daa4a0abe30455aeccef726093b1b0f2f3eb50ce | [log] [tgz] |
---|---|---|
author | Yu-Ping Wu <yupingso@chromium.org> | Tue Jul 19 17:09:39 2022 +0800 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Thu Aug 11 03:50:50 2022 +0000 |
tree | fc720e5c79782b3800245a7493796381aa61a6e4 | |
parent | 00ba52a3ca0ca42a989cef66eb0e9c99eaabc4e6 [diff] |
UPSTREAM: soc/mediatek/mt8195: Skip PCIe ops for eMMC SKUs To avoid unnecessary PCIe early initialization for non-NVMe devices (which would take about 150ms on dojo), skip setting PCIe ops when initializing mt8195 SoC. BUG=b:238850212 TEST=emerge-cherry coreboot TEST=Dojo SKU1 (eMMC) boot time <= 1s BRANCH=cherry (cherry picked from commit 3b9d6a41b30241e9709e27b267ae1d5f154e4287) Original-Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd Original-Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> GitOrigin-RevId: 3b9d6a41b30241e9709e27b267ae1d5f154e4287 Change-Id: Id5717ca6bf5f3583a6bbf1f9edc209872b03e43c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3791087 Tested-by: CopyBot Service Account <copybot.service@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3818513 Auto-Submit: Yu-Ping Wu <yupingso@chromium.org> Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Queue: Yu-Ping Wu <yupingso@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.