Google Git
Sign in
cos / mirrors / cros / chromiumos / third_party / coreboot / refs/heads/firmware-brya-14505.B
commit6bc022743e64ec7b08a0bb9bb76c8c1349322825[log] [tgz]
authorAnil Kumar <anil.kumar.k@intel.com>Mon Apr 22 17:37:04 2024 -0700
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Wed May 01 20:00:46 2024 +0000
treeb269cc47b7a7f2636272b429a11d92360ee91eaa
parentd221e94b0d9527140845f0c7b74e6e21882353a9 [diff]
UPSTREAM: vc/google/chromeos: Move RAMOOPS region creation to BS_DEV_INIT_CHIPS

RAMOOPS memory region was being overwritten by coreboot bmp_load_logo()
function. The CBMEM_ID_FSP_LOGO region created during bmp_load_logo()
was overlapping with RAMOOPS space created earlier. This resulted in
memory corruption of RAMOOPS buffer.

To prevent this, the RAMOOPS region allocation is moved to
BS_DEV_INIT_CHIPS phase from earlier BS_WRITE_TABLES phase of boot.

BUG=b:332910298
TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS
CBMEM region creation using cbmem -l command

(cherry picked from commit 90e835db2d2ef75ea7d0999090d1806cf7f85a4a)

Original-Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Original-Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/82042
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Reviewed-by: Eran Mitrani <mitrani@google.com>
Original-Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
GitOrigin-RevId: 90e835db2d2ef75ea7d0999090d1806cf7f85a4a
Change-Id: Ic584ee45c55ddfa5e56d2c996fd11e013d9e63a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5493454
Reviewed-by: Kapil Porwal <kapilporwal@chromium.org>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: Kapil Porwal <kapilporwal@chromium.org>
Signed-off-by: Anil Kumar <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5491288
Reviewed-by: Subrata Banik <subratabanik@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Tested-by: Subrata Banik <subratabanik@chromium.org>
1 file changed
tree: b269cc47b7a7f2636272b429a11d92360ee91eaa
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. OWNERS
  22. PRESUBMIT.cfg
  23. README.md
  24. toolchain.inc
  25. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.